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Searched refs:OUTREG (Results 1 – 25 of 37) sorted by relevance

12

/haiku/src/add-ons/accelerants/ati/
H A Dmach64_draw.cpp26 OUTREG(GEN_TEST_CNTL, genTestCntl); in Mach64_EngineReset()
27 OUTREG(GEN_TEST_CNTL, genTestCntl | GUI_ENGINE_ENABLE); in Mach64_EngineReset()
31 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK); in Mach64_EngineReset()
44 OUTREG(MEM_VGA_WP_SEL, 0x00010000); in Mach64_EngineInit()
45 OUTREG(MEM_VGA_RP_SEL, 0x00010000); in Mach64_EngineInit()
72 OUTREG(DP_PIX_WIDTH, dpPixWidth); in Mach64_EngineInit()
73 OUTREG(DP_CHAIN_MASK, dpChainMask); in Mach64_EngineInit()
75 OUTREG(CONTEXT_MASK, 0xffffffff); in Mach64_EngineInit()
78 OUTREG(DST_OFF_PITCH, (mode.timing.h_display / 8) << 22); in Mach64_EngineInit()
79 OUTREG(DST_Y_X, 0); in Mach64_EngineInit()
[all …]
H A Drage128_draw.cpp50 OUTREG(R128_GEN_RESET_CNTL, genResetCntl | R128_SOFT_RESET_GUI); in Rage128_EngineReset()
52 OUTREG(R128_GEN_RESET_CNTL, genResetCntl & ~R128_SOFT_RESET_GUI); in Rage128_EngineReset()
56 OUTREG(R128_CLOCK_CNTL_INDEX, clockCntlIndex); in Rage128_EngineReset()
57 OUTREG(R128_GEN_RESET_CNTL, genResetCntl); in Rage128_EngineReset()
70 OUTREG(R128_SCALE_3D_CNTL, 0); in Rage128_EngineInit()
93 OUTREG(R128_DEFAULT_OFFSET, gInfo.sharedInfo->frameBufferOffset); in Rage128_EngineInit()
94 OUTREG(R128_DEFAULT_PITCH, mode.timing.h_display / 8); in Rage128_EngineInit()
97 OUTREG(R128_AUX_SC_CNTL, 0); in Rage128_EngineInit()
98 OUTREG(R128_DEFAULT_SC_BOTTOM_RIGHT, (R128_DEFAULT_SC_RIGHT_MAX in Rage128_EngineInit()
100 OUTREG(R128_SC_TOP_LEFT, 0); in Rage128_EngineInit()
[all …]
H A Drage128_overlay.cpp77 OUTREG(R128_OV0_SCALE_CNTL, 0); in Rage128_DisplayOverlay()
78 OUTREG(R128_OV0_EXCLUSIVE_HORZ, 0); in Rage128_DisplayOverlay()
79 OUTREG(R128_OV0_AUTO_FLIP_CNTL, 0); in Rage128_DisplayOverlay()
80 OUTREG(R128_OV0_FILTER_CNTL, 0x0000000f); in Rage128_DisplayOverlay()
84 OUTREG(R128_OV0_COLOUR_CNTL, brightness | saturation << 8 in Rage128_DisplayOverlay()
87 OUTREG(R128_OV0_GRAPHICS_KEY_MSK, keyMask); in Rage128_DisplayOverlay()
88 OUTREG(R128_OV0_GRAPHICS_KEY_CLR, keyColor); in Rage128_DisplayOverlay()
89 OUTREG(R128_OV0_KEY_CNTL, R128_GRAPHIC_KEY_FN_NE); in Rage128_DisplayOverlay()
90 OUTREG(R128_OV0_TEST, 0); in Rage128_DisplayOverlay()
136 OUTREG(R128_OV0_REG_LOAD_CNTL, 1); in Rage128_DisplayOverlay()
[all …]
H A Dmach64_overlay.cpp68 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_EXT_REG_EN); // enable reg block 1 in Mach64_DisplayOverlay()
69 OUTREG(OVERLAY_SCALE_CNTL, SCALE_EN); // reset the video in Mach64_DisplayOverlay()
76 OUTREG(SCALER_COLOUR_CNTL, brightness | saturation << 8 in Mach64_DisplayOverlay()
78 OUTREG(SCALER_H_COEFF0, 0x0002000); in Mach64_DisplayOverlay()
79 OUTREG(SCALER_H_COEFF1, 0xd06200d); in Mach64_DisplayOverlay()
80 OUTREG(SCALER_H_COEFF2, 0xd0a1c0d); in Mach64_DisplayOverlay()
81 OUTREG(SCALER_H_COEFF3, 0xc0e1a0c); in Mach64_DisplayOverlay()
82 OUTREG(SCALER_H_COEFF4, 0xc14140c); in Mach64_DisplayOverlay()
113 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, keyMask); in Mach64_DisplayOverlay()
114 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, keyColor); in Mach64_DisplayOverlay()
[all …]
H A Drage128_mode.cpp273 OUTREG(R128_OVR_CLR, 0); in SetRegisters()
274 OUTREG(R128_OVR_WID_LEFT_RIGHT, 0); in SetRegisters()
275 OUTREG(R128_OVR_WID_TOP_BOTTOM, 0); in SetRegisters()
276 OUTREG(R128_OV0_SCALE_CNTL, 0); in SetRegisters()
277 OUTREG(R128_MPP_TB_CONFIG, 0); in SetRegisters()
278 OUTREG(R128_MPP_GP_CONFIG, 0); in SetRegisters()
279 OUTREG(R128_SUBPIC_CNTL, 0); in SetRegisters()
280 OUTREG(R128_VIPH_CONTROL, 0); in SetRegisters()
281 OUTREG(R128_I2C_CNTL_1, 0); in SetRegisters()
282 OUTREG(R128_GEN_INT_CNTL, 0); in SetRegisters()
[all …]
H A Drage128_cursor.cpp50 OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xOffset << 16) | yOffset); in Rage128_SetCursorPosition()
51 OUTREG(R128_CUR_HORZ_VERT_POSN, R128_CUR_LOCK | (x << 16) | y); in Rage128_SetCursorPosition()
52 OUTREG(R128_CUR_OFFSET, si.cursorOffset + yOffset * 16); in Rage128_SetCursorPosition()
95 OUTREG(R128_CUR_CLR0, ~0); in Rage128_LoadCursorImage()
96 OUTREG(R128_CUR_CLR1, 0); in Rage128_LoadCursorImage()
H A Dmach64_cursor.cpp46 OUTREG(CUR_OFFSET, (si.cursorOffset >> 3) + (yOffset << 1)); in Mach64_SetCursorPosition()
47 OUTREG(CUR_HORZ_VERT_OFF, (yOffset << 16) | xOffset); in Mach64_SetCursorPosition()
48 OUTREG(CUR_HORZ_VERT_POSN, (y << 16) | x); in Mach64_SetCursorPosition()
98 OUTREG(CUR_CLR0, ~0); in Mach64_LoadCursorImage()
99 OUTREG(CUR_CLR1, 0); in Mach64_LoadCursorImage()
H A Dmach64_mode.cpp110 OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN); in SetClockRegisters()
140 OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl); // Restore register in SetClockRegisters()
219 OUTREG(DSP_ON_OFF, dsp_on_off); in SetDSPRegisters()
220 OUTREG(DSP_CONFIG, dsp_config); in SetDSPRegisters()
297 OUTREG(CRTC_GEN_CNTL, crtc_gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN)); in SetCrtcRegisters()
299 OUTREG(CRTC_H_TOTAL_DISP, crtc_h_total_disp); in SetCrtcRegisters()
300 OUTREG(CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid); in SetCrtcRegisters()
301 OUTREG(CRTC_V_TOTAL_DISP, crtc_v_total_disp); in SetCrtcRegisters()
302 OUTREG(CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid); in SetCrtcRegisters()
304 OUTREG(CRTC_OFF_PITCH, crtc_off_pitch); in SetCrtcRegisters()
[all …]
H A Drage128_dpms.cpp102 OUTREG(R128_LVDS_GEN_CNTL, genCtrl); in Rage128_SetDPMSMode()
110 OUTREG(R128_LVDS_GEN_CNTL, genCtrl); in Rage128_SetDPMSMode()
113 OUTREG(R128_LVDS_GEN_CNTL, genCtrl); in Rage128_SetDPMSMode()
125 OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) in Rage128_SetDPMSMode()
132 OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) in Rage128_SetDPMSMode()
/haiku/src/add-ons/accelerants/radeon/
H A DAcceleration.c73 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT in SCREEN_TO_SCREEN_BLIT_PIO()
92 OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) in SCREEN_TO_SCREEN_BLIT_PIO()
96 OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left); in SCREEN_TO_SCREEN_BLIT_PIO()
97 OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left); in SCREEN_TO_SCREEN_BLIT_PIO()
100 OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1)); in SCREEN_TO_SCREEN_BLIT_PIO()
166 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) in FILL_RECTANGLE_PIO()
171 OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex); in FILL_RECTANGLE_PIO()
172 OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM)); in FILL_RECTANGLE_PIO()
178 OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left); in FILL_RECTANGLE_PIO()
179 …OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom -… in FILL_RECTANGLE_PIO()
[all …]
H A Dcrtc.c30 OUTREG( regs, RADEON_CRTC_H_TOTAL_DISP, values->crtc_h_total_disp ); in Radeon_ProgramCRTCRegisters()
31 OUTREG( regs, RADEON_CRTC_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid ); in Radeon_ProgramCRTCRegisters()
32 OUTREG( regs, RADEON_CRTC_V_TOTAL_DISP, values->crtc_v_total_disp ); in Radeon_ProgramCRTCRegisters()
33 OUTREG( regs, RADEON_CRTC_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid ); in Radeon_ProgramCRTCRegisters()
34 OUTREG( regs, RADEON_CRTC_OFFSET_CNTL, values->crtc_offset_cntl ); in Radeon_ProgramCRTCRegisters()
35 OUTREG( regs, RADEON_CRTC_PITCH, values->crtc_pitch ); in Radeon_ProgramCRTCRegisters()
44 OUTREG( regs, RADEON_CRTC2_H_TOTAL_DISP, values->crtc_h_total_disp ); in Radeon_ProgramCRTCRegisters()
45 OUTREG( regs, RADEON_CRTC2_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid ); in Radeon_ProgramCRTCRegisters()
46 OUTREG( regs, RADEON_CRTC2_V_TOTAL_DISP, values->crtc_v_total_disp ); in Radeon_ProgramCRTCRegisters()
47 OUTREG( regs, RADEON_CRTC2_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid ); in Radeon_ProgramCRTCRegisters()
[all …]
H A DCursor.c25 OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff ); in Radeon_SetCursorColors()
26 OUTREG( ai->regs, RADEON_CUR_CLR1, 0 ); in Radeon_SetCursorColors()
28 OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff ); in Radeon_SetCursorColors()
29 OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 ); in Radeon_SetCursorColors()
197 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK in moveOneCursor()
200 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK in moveOneCursor()
203 OUTREG( ai->regs, RADEON_CUR_OFFSET, in moveOneCursor()
206 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK in moveOneCursor()
209 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK in moveOneCursor()
212 OUTREG( ai->regs, RADEON_CUR2_OFFSET, in moveOneCursor()
[all …]
H A Doverlay.c68 OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET ); in Radeon_InitOverlay()
69 OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg ); in Radeon_InitOverlay()
70 OUTREG( regs, RADEON_OV0_FILTER_CNTL, // use fixed filter coefficients in Radeon_InitOverlay()
75 OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ | in Radeon_InitOverlay()
78 OUTREG( regs, RADEON_OV0_TEST, 0 ); in Radeon_InitOverlay()
81 OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 ); in Radeon_InitOverlay()
83 OUTREG( regs, RADEON_OV0_DEINTERLACE_PATTERN, in Radeon_InitOverlay()
89 OUTREG( regs, std_gamma[i].reg, in Radeon_InitOverlay()
263 OUTREG( regs, RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvRY ); in Radeon_SetTransform()
264 OUTREG( regs, RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr ); in Radeon_SetTransform()
[all …]
H A Dmonitor_detection.c65 OUTREG(regs, info->port, value); in set_signals()
112 OUTREG(regs, RADEON_CRTC_EXT_CNTL, value); in Radeon_DetectCRTInt()
121 OUTREG(regs, RADEON_DAC_EXT_CNTL, value); in Radeon_DetectCRTInt()
128 OUTREG(regs, RADEON_DAC_CNTL, value); in Radeon_DetectCRTInt()
143 OUTREG(regs, RADEON_DAC_CNTL, old_dac_cntl); in Radeon_DetectCRTInt()
144 OUTREG(regs, RADEON_DAC_EXT_CNTL, old_dac_ext_cntl); in Radeon_DetectCRTInt()
145 OUTREG(regs, RADEON_CRTC_EXT_CNTL, old_crtc_ext_cntl); in Radeon_DetectCRTInt()
189 OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value); in Radeon_DetectTVCRT_RV200()
196 OUTREG(regs, RADEON_TV_DAC_CNTL, value); in Radeon_DetectTVCRT_RV200()
202 OUTREG(regs, RADEON_DAC_EXT_CNTL, value); in Radeon_DetectTVCRT_RV200()
[all …]
H A Dflat_panel.c112 OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch ); in Radeon_ProgramRMXRegisters()
113 OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch ); in Radeon_ProgramRMXRegisters()
266 OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid ); in Radeon_ProgramFPRegisters()
267 OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid ); in Radeon_ProgramFPRegisters()
270 OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid ); in Radeon_ProgramFPRegisters()
271 OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid ); in Radeon_ProgramFPRegisters()
277 OUTREG( regs, RADEON_GRPH_BUFFER_CNTL, in Radeon_ProgramFPRegisters()
282 OUTREG( regs, RADEON_BIOS_4_SCRATCH, values->bios_4_scratch); in Radeon_ProgramFPRegisters()
283 OUTREG( regs, RADEON_BIOS_5_SCRATCH, values->bios_5_scratch); in Radeon_ProgramFPRegisters()
284 OUTREG( regs, RADEON_BIOS_6_SCRATCH, values->bios_6_scratch); in Radeon_ProgramFPRegisters()
[all …]
H A Dpalette.c41 OUTREG( ai->regs, RADEON_DAC_CNTL2, in Radeon_InitPalette()
45 OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 ); in Radeon_InitPalette()
48 OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i ); in Radeon_InitPalette()
104 OUTREG( ai->regs, RADEON_DAC_CNTL2, in setPalette()
108 OUTREG( ai->regs, RADEON_PALETTE_INDEX, first ); in setPalette()
111 OUTREG( ai->regs, RADEON_PALETTE_DATA, in setPalette()
H A Dinternal_tv_out.c99 OUTREG( regs, mapping->address, *(uint32 *)((char *)(values) + mapping->offset) ); in writeMMIORegList()
135 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_RD);
148 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0);
168 OUTREG( regs, RADEON_TV_HOST_WRITE_DATA, value ); in Radeon_InternalTVOutWriteFIFO()
169 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_WT ); in Radeon_InternalTVOutWriteFIFO()
182 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0 ); in Radeon_InternalTVOutWriteFIFO()
210 OUTREG( ai->regs, RADEON_TV_MASTER_CNTL, in Radeon_InternalTVOutProgramRegisters()
H A Dmonitor_routing.c424 OUTREG( regs, RADEON_DAC_CNTL, values->dac_cntl ); in Radeon_ProgramMonitorRouting()
425 OUTREG( regs, RADEON_DAC_CNTL2, values->dac_cntl2 ); in Radeon_ProgramMonitorRouting()
428 OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl ); in Radeon_ProgramMonitorRouting()
438 OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug ); in Radeon_ProgramMonitorRouting()
442 OUTREG( regs, RADEON_DISP_TV_OUT_CNTL, values->disp_tv_out_cntl ); in Radeon_ProgramMonitorRouting()
462 OUTREG( regs, RADEON_TV_DAC_CNTL, values->tv_dac_cntl ); in Radeon_ProgramMonitorRouting()
466 OUTREG( regs, RADEON_TV_MASTER_CNTL, values->tv_master_cntl ); in Radeon_ProgramMonitorRouting()
H A DEngineManagment.c86 OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); in writeSyncToken()
87 OUTREG( ai->regs, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | in writeSyncToken()
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dvip.c36 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 ); in do_VIPRead()
113 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x3000); in do_VIPFifoRead()
126 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, in do_VIPFifoRead()
144 …OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DI… in do_VIPFifoRead()
165 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, in do_VIPFifoRead()
195 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) ); in do_VIPWrite()
202 OUTREG( regs, RADEON_VIPH_REG_DATA, data ); in do_VIPWrite()
239 OUTREG( regs, RADEON_VIPH_REG_ADDR, in do_VIPFifoWrite()
257 OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i)); in do_VIPFifoWrite()
309 OUTREG( regs, RADEON_VIPH_CONTROL, 4 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) | in Radeon_VIPReset()
[all …]
H A Dmem_controller.c163 OUTREG( regs, RADEON_AIC_PT_BASE, di->pci_gart.GATT.phys ); in Radeon_InitMemController()
167 OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start ); in Radeon_InitMemController()
168 OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start + in Radeon_InitMemController()
172 OUTREG( regs, RADEON_MC_AGP_LOCATION, 0xffffffc0 /* EK magic numbers from X.org in Radeon_InitMemController()
177 OUTREG( regs, RADEON_AGP_COMMAND, 0 ); in Radeon_InitMemController()
182 OUTREG( regs, RADEON_MC_FB_LOCATION, in Radeon_InitMemController()
188 OUTREG( regs, RADEON_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start ); in Radeon_InitMemController()
189 OUTREG( regs, RADEON_CRTC2_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start ); in Radeon_InitMemController()
190 OUTREG( regs, RADEON_OV0_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start ); in Radeon_InitMemController()
H A DCP_setup.c234 OUTREG( regs, RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | in Radeon_ResetEngine()
243 OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset & in Radeon_ResetEngine()
253 OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET ); in Radeon_ResetEngine()
255 OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl ); in Radeon_ResetEngine()
258 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); in Radeon_ResetEngine()
260 OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); in Radeon_ResetEngine()
266 OUTREG( regs, RADEON_CP_RB_WPTR, cur_read_ptr ); in Radeon_ResetEngine()
312 OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 ); in loadMicroEngineRAMData()
315 OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] ); in loadMicroEngineRAMData()
316 OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] ); in loadMicroEngineRAMData()
[all …]
H A Dpll_access.c52 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp ); in RADEONPllErrataAfterData()
54 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save ); in RADEONPllErrataAfterData()
78 OUTREG( regs, RADEON_CLOCK_CNTL_DATA, val ); in Radeon_OUTPLL()
H A DDMA.c41 OUTREG( di->regs, RADEON_GEN_INT_STATUS, RADEON_VIDDMA_AK ); in Radeon_InitDMA()
170 OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start + in Radeon_DMACopy()
/haiku/headers/private/graphics/radeon/
H A Dmmio.h20 #define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 ) macro
27 OUTREG( (regs), (addr), tmp ); \

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