68 	OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET );  in Radeon_InitOverlay()
69 	OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );  in Radeon_InitOverlay()
70 	OUTREG( regs, RADEON_OV0_FILTER_CNTL, 			// use fixed filter coefficients  in Radeon_InitOverlay()
75 	OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |  in Radeon_InitOverlay()
78 	OUTREG( regs, RADEON_OV0_TEST, 0 );  in Radeon_InitOverlay()
81 	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );  in Radeon_InitOverlay()
83 	OUTREG( regs, RADEON_OV0_DEINTERLACE_PATTERN,   in Radeon_InitOverlay()
89 			OUTREG( regs, std_gamma[i].reg,	  in Radeon_InitOverlay()
263 	OUTREG( regs, RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvRY );  in Radeon_SetTransform()
264 	OUTREG( regs, RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr );  in Radeon_SetTransform()
265 	OUTREG( regs, RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvGY );  in Radeon_SetTransform()
266 	OUTREG( regs, RADEON_OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr );  in Radeon_SetTransform()
267 	OUTREG( regs, RADEON_OV0_LIN_TRANS_E, dwOvBCb | dwOvBY );  in Radeon_SetTransform()
268 	OUTREG( regs, RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr );  in Radeon_SetTransform()
336 	OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_LOW, min32 );  in Radeon_SetColourKey()
337 	OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_HIGH, max32 );  in Radeon_SetColourKey()
338 	OUTREG( regs, RADEON_OV0_KEY_CNTL,   in Radeon_SetColourKey()
849 	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK );  in Radeon_ShowOverlay()
856 	OUTREG( regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset );  in Radeon_ShowOverlay()
857 	OUTREG( regs, RADEON_OV0_VID_BUF_PITCH0_VALUE, node->buffer.bytes_per_row );  in Radeon_ShowOverlay()
858 	OUTREG( regs, RADEON_OV0_H_INC, p1_h_inc | (p23_h_inc << 16) );  in Radeon_ShowOverlay()
859 	OUTREG( regs, RADEON_OV0_STEP_BY, factors->p1_step_by | (factors->p23_step_by << 8) );  in Radeon_ShowOverlay()
860 	OUTREG( regs, RADEON_OV0_V_INC, v_inc );  in Radeon_ShowOverlay()
862 	OUTREG( regs,  in Radeon_ShowOverlay()
865 	OUTREG( regs,   in Radeon_ShowOverlay()
869 	OUTREG( regs, RADEON_OV0_P1_BLANK_LINES_AT_TOP,   in Radeon_ShowOverlay()
871 	OUTREG( regs, RADEON_OV0_P1_X_START_END, p1_x_end | (p1_x_start << 16) );  in Radeon_ShowOverlay()
872 	OUTREG( regs, RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init );  in Radeon_ShowOverlay()
873 	OUTREG( regs, RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init );  in Radeon_ShowOverlay()
875 	OUTREG( regs, RADEON_OV0_P23_BLANK_LINES_AT_TOP,   in Radeon_ShowOverlay()
877 	OUTREG( regs, RADEON_OV0_P2_X_START_END,   in Radeon_ShowOverlay()
879 	OUTREG( regs, RADEON_OV0_P3_X_START_END,   in Radeon_ShowOverlay()
881 	OUTREG( regs, RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init );  in Radeon_ShowOverlay()
882 	OUTREG( regs, RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init );  in Radeon_ShowOverlay()
884 	OUTREG( regs, RADEON_OV0_TEST, node->test_reg );  in Radeon_ShowOverlay()
897 			OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |   in Radeon_ShowOverlay()
902 			OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl);  in Radeon_ShowOverlay()
906 			OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |  in Radeon_ShowOverlay()
913 	OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL,   in Radeon_ShowOverlay()
916 	OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );  in Radeon_ShowOverlay()
936 	OUTREG( ai->regs, RADEON_OV0_SCALE_CNTL, 0 );  in Radeon_TempHideOverlay()
989 	OUTREG( regs,   in Radeon_ReplaceOverlayBuffer()
996 	OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );  in Radeon_ReplaceOverlayBuffer()
1022 		OUTREG( ai->regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset);  in Radeon_ReplaceOverlayBuffer()
1025 		OUTREG( ai->regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );  in Radeon_ReplaceOverlayBuffer()