234 	OUTREG( regs, RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |  in Radeon_ResetEngine()
243 	OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset &  in Radeon_ResetEngine()
253     OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET );  in Radeon_ResetEngine()
255     OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl );  in Radeon_ResetEngine()
258    	OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );  in Radeon_ResetEngine()
260    	OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);  in Radeon_ResetEngine()
266 		OUTREG( regs, RADEON_CP_RB_WPTR, cur_read_ptr );  in Radeon_ResetEngine()
312 	OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 );  in loadMicroEngineRAMData()
315 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] );  in loadMicroEngineRAMData()
316 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] );  in loadMicroEngineRAMData()
351 	OUTREG( regs, RADEON_CP_RB_BASE, cp->ring.vm_base );  in initRingBuffer()
356 	OUTREG( regs, RADEON_CP_RB_CNTL, radeon_log2( cp->ring.size / 2 ));  in initRingBuffer()
362 	OUTREG( regs, RADEON_CP_RB_WPTR_DELAY, 0 );  in initRingBuffer()
367 	OUTREG( regs, RADEON_CP_RB_RPTR, 0 );  in initRingBuffer()
368 	OUTREG( regs, RADEON_CP_RB_WPTR, 0 );  in initRingBuffer()
383 	OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );  in uninitRingBuffer()
415 	OUTREG( regs, RADEON_CP_RB_RPTR_ADDR, cp->feedback.head_vm_address );  in initCPFeedback()
422 	OUTREG( regs, RADEON_SCRATCH_ADDR, cp->feedback.scratch_vm_start );  in initCPFeedback()
423 	OUTREG( regs, RADEON_SCRATCH_UMSK, 0x3f );  in initCPFeedback()
437 	OUTREG( regs, RADEON_SCRATCH_UMSK, 0x0 );  in uninitCPFeedback()
521 	OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );  in Radeon_InitCP()
545 		OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM );  in Radeon_InitCP()
555 	OUTREG( di->regs, RADEON_ISYNC_CNTL,  in Radeon_InitCP()
588 	OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );  in Radeon_UninitCP()