36 	OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );  in do_VIPRead()
113 	OUTREG( regs, RADEON_VIPH_REG_ADDR,  (channel << 14) | address | 0x3000);  in do_VIPFifoRead()
126 	OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,   in do_VIPFifoRead()
144 …OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DI…  in do_VIPFifoRead()
165 	OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,   in do_VIPFifoRead()
195 	OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) );  in do_VIPWrite()
202 	OUTREG( regs, RADEON_VIPH_REG_DATA, data );  in do_VIPWrite()
239 	OUTREG( regs, RADEON_VIPH_REG_ADDR,  in do_VIPFifoWrite()
257 		OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));  in do_VIPFifoWrite()
309 	    OUTREG( regs, RADEON_VIPH_CONTROL, 4 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |  in Radeon_VIPReset()
311 …   OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |   in Radeon_VIPReset()
313 	    OUTREG( regs, RADEON_VIPH_DV_LAT,   in Radeon_VIPReset()
319 	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);  in Radeon_VIPReset()
320 …OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_C…  in Radeon_VIPReset()
322 		    OUTREG( regs, RADEON_VIPH_CONTROL, 9 | 	(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |  in Radeon_VIPReset()
324 …   OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |   in Radeon_VIPReset()
326 	    OUTREG( regs, RADEON_VIPH_DV_LAT,   in Radeon_VIPReset()
332 	    OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);  in Radeon_VIPReset()
333 …OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_C…  in Radeon_VIPReset()
357 		OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,   in Radeon_VIPIdle()
372 		OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);  in RADEON_VIPFifoIdle()