73 	OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT  in SCREEN_TO_SCREEN_BLIT_PIO()
92 		OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0)  in SCREEN_TO_SCREEN_BLIT_PIO()
96 		OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left);  in SCREEN_TO_SCREEN_BLIT_PIO()
97 		OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left);  in SCREEN_TO_SCREEN_BLIT_PIO()
100 		OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1));  in SCREEN_TO_SCREEN_BLIT_PIO()
166     OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)  in FILL_RECTANGLE_PIO()
171     OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR,  colorIndex);  in FILL_RECTANGLE_PIO()
172     OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));  in FILL_RECTANGLE_PIO()
178 		OUTREG(ai->regs, RADEON_DST_Y_X,          (list->top << 16) | list->left);  in FILL_RECTANGLE_PIO()
179 …OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom -…  in FILL_RECTANGLE_PIO()
249     OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)  in INVERT_RECTANGLE_PIO()
255     OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));  in INVERT_RECTANGLE_PIO()
261 		OUTREG(ai->regs, RADEON_DST_Y_X,          (list->top << 16) | list->left);  in INVERT_RECTANGLE_PIO()
262 …OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom -…  in INVERT_RECTANGLE_PIO()
330     OUTREG( ai->regs, RADEON_DP_GUI_MASTER_CNTL, 0  in FILL_SPAN_PIO()
338 		OUTREG( ai->regs, RADEON_DST_LINE_PATCOUNT, 0x55 << RADEON_BRES_CNTL_SHIFT);  in FILL_SPAN_PIO()
342 	OUTREG( ai->regs, RADEON_DP_BRUSH_FRGD_CLR,  colorIndex);  in FILL_SPAN_PIO()
352 	    OUTREG( ai->regs, RADEON_DST_LINE_START,           (y << 16) | x);  in FILL_SPAN_PIO()
353     	OUTREG( ai->regs, RADEON_DST_LINE_END,             ((y) << 16) | (x + width));  in FILL_SPAN_PIO()
408 		OUTREG( ai->regs, RADEON_RB3D_CNTL, 0 );  in Radeon_Init2D()
463 		OUTREG( ai->regs, RADEON_DEFAULT_OFFSET, pitch_offset );  in Radeon_FillStateBuffer()
464 		OUTREG( ai->regs, RADEON_DST_PITCH_OFFSET, pitch_offset );  in Radeon_FillStateBuffer()
465 		OUTREG( ai->regs, RADEON_SRC_PITCH_OFFSET, pitch_offset );  in Radeon_FillStateBuffer()
467 		OUTREG( ai->regs, RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX  in Radeon_FillStateBuffer()
470 		OUTREG( ai->regs, RADEON_DP_GUI_MASTER_CNTL,  in Radeon_FillStateBuffer()
483 		OUTREG( ai->regs, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);  in Radeon_FillStateBuffer()
484 		OUTREG( ai->regs, RADEON_DP_BRUSH_BKGD_CLR, 0x00000000);  in Radeon_FillStateBuffer()
485 		OUTREG( ai->regs, RADEON_DP_SRC_FRGD_CLR,   0xffffffff);  in Radeon_FillStateBuffer()
486 		OUTREG( ai->regs, RADEON_DP_SRC_BKGD_CLR,   0x00000000);  in Radeon_FillStateBuffer()
487 		OUTREG( ai->regs, RADEON_DP_WRITE_MASK,     0xffffffff);  in Radeon_FillStateBuffer()