1 /*
2 * Copyright 2002-04, Thomas Kurschel. All rights reserved.
3 * Distributed under the terms of the MIT License.
4 */
5
6 /*
7 Generic ATA adapter library.
8 */
9
10 #include <KernelExport.h>
11 #include <malloc.h>
12 #include <stdio.h>
13 #include <string.h>
14
15 #include <ata_adapter.h>
16 #include <tracing.h>
17
18 #define debug_level_flow 0
19 #define debug_level_error 3
20 #define debug_level_info 3
21
22 #define DEBUG_MSG_PREFIX "ATA PCI -- "
23
24 #include "wrapper.h"
25
26 #define TRACE dprintf
27
28 #define INTERRUPT_TRACING 0
29 #if INTERRUPT_TRACING
30 #define TRACE_INT(a...) ktrace_printf(a)
31 #else
32 #define TRACE_INT(a...)
33 #endif
34
35
36 #if ATA_DMA_TRACING
37 #define TRACE_DMA(x...) ktrace_printf(x)
38 #else
39 #define TRACE_DMA(x...)
40 #endif
41
42 static ata_for_controller_interface *sATA;
43 static device_manager_info *sDeviceManager;
44
45
46 static void
set_channel(ata_adapter_channel_info * channel,ata_channel ataChannel)47 set_channel(ata_adapter_channel_info *channel, ata_channel ataChannel)
48 {
49 channel->ataChannel = ataChannel;
50 }
51
52
53 static status_t
ata_adapter_write_command_block_regs(ata_adapter_channel_info * channel,ata_task_file * tf,ata_reg_mask mask)54 ata_adapter_write_command_block_regs(ata_adapter_channel_info *channel,
55 ata_task_file *tf, ata_reg_mask mask)
56 {
57 pci_device_module_info *pci = channel->pci;
58 pci_device *device = channel->device;
59 int i;
60
61 uint16 ioaddr = channel->command_block_base;
62
63 if (channel->lost)
64 return B_ERROR;
65
66 for (i = 0; i < 7; i++) {
67 // LBA48 registers must be written twice
68 if (((1 << (i + 7)) & mask) != 0) {
69 SHOW_FLOW( 4, "%x->HI(%x)", tf->raw.r[i + 7], i );
70 pci->write_io_8(device, ioaddr + 1 + i, tf->raw.r[i + 7]);
71 }
72
73 if (((1 << i) & mask) != 0) {
74 SHOW_FLOW( 4, "%x->LO(%x)", tf->raw.r[i], i );
75 pci->write_io_8(device, ioaddr + 1 + i, tf->raw.r[i]);
76 }
77 }
78
79 return B_OK;
80 }
81
82
83 static status_t
ata_adapter_read_command_block_regs(ata_adapter_channel_info * channel,ata_task_file * tf,ata_reg_mask mask)84 ata_adapter_read_command_block_regs(ata_adapter_channel_info *channel,
85 ata_task_file *tf, ata_reg_mask mask)
86 {
87 pci_device_module_info *pci = channel->pci;
88 pci_device *device = channel->device;
89 int i;
90
91 uint16 ioaddr = channel->command_block_base;
92
93 if (channel->lost)
94 return B_ERROR;
95
96 for (i = 0; i < 7; i++) {
97 if (((1 << i) & mask) != 0) {
98 tf->raw.r[i] = pci->read_io_8(device, ioaddr + 1 + i);
99 SHOW_FLOW( 4, "%x: %x", i, (int)tf->raw.r[i] );
100 }
101 }
102
103 return B_OK;
104 }
105
106
107 static uint8
ata_adapter_get_altstatus(ata_adapter_channel_info * channel)108 ata_adapter_get_altstatus(ata_adapter_channel_info *channel)
109 {
110 pci_device_module_info *pci = channel->pci;
111 pci_device *device = channel->device;
112 uint16 altstatusaddr = channel->control_block_base;
113
114 if (channel->lost)
115 return 0x01; // Error bit
116
117 return pci->read_io_8(device, altstatusaddr);
118 }
119
120
121 static status_t
ata_adapter_write_device_control(ata_adapter_channel_info * channel,uint8 val)122 ata_adapter_write_device_control(ata_adapter_channel_info *channel, uint8 val)
123 {
124 pci_device_module_info *pci = channel->pci;
125 pci_device *device = channel->device;
126 uint16 device_control_addr = channel->control_block_base;
127
128 SHOW_FLOW(3, "%x", (int)val);
129
130 if (channel->lost)
131 return B_ERROR;
132
133 pci->write_io_8(device, device_control_addr, val);
134
135 return B_OK;
136 }
137
138
139 static status_t
ata_adapter_write_pio(ata_adapter_channel_info * channel,uint16 * data,int count,bool force_16bit)140 ata_adapter_write_pio(ata_adapter_channel_info *channel, uint16 *data,
141 int count, bool force_16bit)
142 {
143 pci_device_module_info *pci = channel->pci;
144 pci_device *device = channel->device;
145
146 uint16 ioaddr = channel->command_block_base;
147
148 if (channel->lost)
149 return B_ERROR;
150
151 force_16bit = true;
152
153 if ((count & 1) != 0 || force_16bit) {
154 for (; count > 0; --count)
155 pci->write_io_16(device, ioaddr, *(data++));
156 } else {
157 uint32 *cur_data = (uint32 *)data;
158
159 for (; count > 0; count -= 2)
160 pci->write_io_32(device, ioaddr, *(cur_data++));
161 }
162
163 return B_OK;
164 }
165
166
167 static status_t
ata_adapter_read_pio(ata_adapter_channel_info * channel,uint16 * data,int count,bool force_16bit)168 ata_adapter_read_pio(ata_adapter_channel_info *channel, uint16 *data,
169 int count, bool force_16bit)
170 {
171 pci_device_module_info *pci = channel->pci;
172 pci_device *device = channel->device;
173
174 uint16 ioaddr = channel->command_block_base;
175
176 if (channel->lost)
177 return B_ERROR;
178
179 force_16bit = true;
180
181 if ((count & 1) != 0 || force_16bit) {
182 for (; count > 0; --count)
183 *(data++) = pci->read_io_16(device, ioaddr );
184 } else {
185 uint32 *cur_data = (uint32 *)data;
186
187 for (; count > 0; count -= 2)
188 *(cur_data++) = pci->read_io_32(device, ioaddr);
189 }
190
191 return B_OK;
192 }
193
194
195 static int32
ata_adapter_inthand(void * arg)196 ata_adapter_inthand(void *arg)
197 {
198 ata_adapter_channel_info *channel = (ata_adapter_channel_info *)arg;
199 pci_device_module_info *pci = channel->pci;
200 pci_device *device = channel->device;
201 uint8 statusATA, statusBM;
202
203 TRACE_INT("ata_adapter_inthand\n");
204
205 // need to read bus master status first, because some controllers
206 // will clear the interrupt status bit once ATA status is read
207 statusBM = pci->read_io_8(device, channel->bus_master_base
208 + ATA_BM_STATUS_REG);
209 TRACE_INT("ata_adapter_inthand: BM-status 0x%02x\n", statusBM);
210
211 // test if the interrupt was really generated by our controller
212 if (statusBM & ATA_BM_STATUS_INTERRUPT) {
213 // read ATA status register to acknowledge interrupt
214 statusATA = pci->read_io_8(device, channel->command_block_base + 7);
215 TRACE_INT("ata_adapter_inthand: ATA-status 0x%02x\n", statusATA);
216
217 // clear pending PCI bus master DMA interrupt, for those
218 // controllers who don't clear it themselves
219 pci->write_io_8(device, channel->bus_master_base + ATA_BM_STATUS_REG,
220 (statusBM & 0xf8) | ATA_BM_STATUS_INTERRUPT);
221
222 if (!channel->dmaing) {
223 // we check this late so that potential spurious interrupts
224 // are acknoledged above
225 TRACE_INT("ata_adapter_inthand: no DMA transfer active\n");
226 return B_UNHANDLED_INTERRUPT;
227 }
228
229 // signal interrupt to ATA stack
230 return sATA->interrupt_handler(channel->ataChannel, statusATA);
231 } else {
232 TRACE_INT("ata_adapter_inthand: not BM\n");
233 return B_UNHANDLED_INTERRUPT;
234 }
235 }
236
237
238 static status_t
ata_adapter_prepare_dma(ata_adapter_channel_info * channel,const physical_entry * sgList,size_t sgListCount,bool writeToDevice)239 ata_adapter_prepare_dma(ata_adapter_channel_info *channel,
240 const physical_entry *sgList, size_t sgListCount, bool writeToDevice)
241 {
242 pci_device_module_info *pci = channel->pci;
243 pci_device *device = channel->device;
244 uint8 command;
245 uint8 status;
246 prd_entry *prd = channel->prdt;
247 int i;
248
249 TRACE_DMA("ata_adapter: prepare_dma (%s) %lu entrys:\n",
250 writeToDevice ? "write" : "read", sgListCount);
251
252 for (i = sgListCount - 1, prd = channel->prdt; i >= 0; --i, ++prd, ++sgList) {
253 prd->address = B_HOST_TO_LENDIAN_INT32((uint32)pci->ram_address(
254 device, sgList->address));
255 // 0 means 64K - this is done automatically be discarding upper 16 bits
256 prd->count = B_HOST_TO_LENDIAN_INT16((uint16)sgList->size);
257 prd->EOT = i == 0;
258
259 TRACE_DMA("ata_adapter: %#" B_PRIxPHYSADDR ", %" B_PRIuPHYSADDR " => "
260 "%#010" B_PRIx32 ", %" B_PRIu16 ", %d\n",
261 sgList->address, sgList->size,
262 prd->address, prd->count, prd->EOT);
263 SHOW_FLOW( 4, "%#010" B_PRIx32 ", %" B_PRIu16 ", %d",
264 prd->address, prd->count, prd->EOT);
265 }
266
267 pci->write_io_32(device, channel->bus_master_base + ATA_BM_PRDT_ADDRESS,
268 (pci->read_io_32(device, channel->bus_master_base + ATA_BM_PRDT_ADDRESS) & 3)
269 | (B_HOST_TO_LENDIAN_INT32((uint32)pci->ram_address(device,
270 channel->prdt_phys)) & ~3));
271
272 // reset interrupt and error signal
273 status = pci->read_io_8(device, channel->bus_master_base
274 + ATA_BM_STATUS_REG) | ATA_BM_STATUS_INTERRUPT | ATA_BM_STATUS_ERROR;
275 pci->write_io_8(device,
276 channel->bus_master_base + ATA_BM_STATUS_REG, status);
277
278 // set data direction
279 command = pci->read_io_8(device, channel->bus_master_base
280 + ATA_BM_COMMAND_REG);
281 if (writeToDevice)
282 command &= ~ATA_BM_COMMAND_READ_FROM_DEVICE;
283 else
284 command |= ATA_BM_COMMAND_READ_FROM_DEVICE;
285
286 pci->write_io_8(device, channel->bus_master_base + ATA_BM_COMMAND_REG,
287 command);
288
289 return B_OK;
290 }
291
292
293 static status_t
ata_adapter_start_dma(ata_adapter_channel_info * channel)294 ata_adapter_start_dma(ata_adapter_channel_info *channel)
295 {
296 pci_device_module_info *pci = channel->pci;
297 pci_device *device = channel->device;
298 uint8 command;
299
300 command = pci->read_io_8(device, channel->bus_master_base
301 + ATA_BM_COMMAND_REG);
302
303 command |= ATA_BM_COMMAND_START_STOP;
304
305 channel->dmaing = true;
306
307 pci->write_io_8(device, channel->bus_master_base + ATA_BM_COMMAND_REG,
308 command);
309
310 return B_OK;
311 }
312
313
314 static status_t
ata_adapter_finish_dma(ata_adapter_channel_info * channel)315 ata_adapter_finish_dma(ata_adapter_channel_info *channel)
316 {
317 pci_device_module_info *pci = channel->pci;
318 pci_device *device = channel->device;
319 uint8 command;
320 uint8 status;
321
322 // read BM status first
323 status = pci->read_io_8(device, channel->bus_master_base
324 + ATA_BM_STATUS_REG);
325
326 // stop DMA engine, this also clears ATA_BM_STATUS_ACTIVE
327 // in the BM status register
328 command = pci->read_io_8(device, channel->bus_master_base
329 + ATA_BM_COMMAND_REG);
330 pci->write_io_8(device, channel->bus_master_base + ATA_BM_COMMAND_REG,
331 command & ~ATA_BM_COMMAND_START_STOP);
332 channel->dmaing = false;
333
334 // reset error flag
335 pci->write_io_8(device, channel->bus_master_base + ATA_BM_STATUS_REG,
336 status | ATA_BM_STATUS_ERROR);
337
338 if ((status & ATA_BM_STATUS_ACTIVE) != 0)
339 return B_DEV_DATA_OVERRUN;
340
341 if ((status & ATA_BM_STATUS_ERROR) != 0)
342 return B_ERROR;
343
344 return B_OK;
345 }
346
347
348 static status_t
ata_adapter_init_channel(device_node * node,ata_adapter_channel_info ** cookie,size_t total_data_size,int32 (* inthand)(void * arg))349 ata_adapter_init_channel(device_node *node,
350 ata_adapter_channel_info **cookie, size_t total_data_size,
351 int32 (*inthand)(void *arg))
352 {
353 ata_adapter_controller_info *controller;
354 ata_adapter_channel_info *channel;
355 uint16 command_block_base, control_block_base;
356 uint8 intnum;
357 int prdt_size;
358 physical_entry pe[1];
359 uint8 channel_index;
360 status_t res;
361
362 TRACE("PCI-ATA: init channel...\n");
363
364 #if 0
365 if (1 /* debug */){
366 uint8 bus, device, function;
367 uint16 vendorID, deviceID;
368 sDeviceManager->get_attr_uint8(node, PCI_DEVICE_BUS_ITEM, &bus, true);
369 sDeviceManager->get_attr_uint8(node, PCI_DEVICE_DEVICE_ITEM, &device, true);
370 sDeviceManager->get_attr_uint8(node, PCI_DEVICE_FUNCTION_ITEM, &function, true);
371 sDeviceManager->get_attr_uint16(node, PCI_DEVICE_VENDOR_ID_ITEM, &vendorID, true);
372 sDeviceManager->get_attr_uint16(node, PCI_DEVICE_DEVICE_ID_ITEM, &deviceID, true);
373 TRACE("PCI-ATA: bus %3d, device %2d, function %2d: vendor %04x, device %04x\n",
374 bus, device, function, vendorID, deviceID);
375 }
376 #endif
377
378 // get device data
379 if (sDeviceManager->get_attr_uint16(node, ATA_ADAPTER_COMMAND_BLOCK_BASE, &command_block_base, false) != B_OK
380 || sDeviceManager->get_attr_uint16(node, ATA_ADAPTER_CONTROL_BLOCK_BASE, &control_block_base, false) != B_OK
381 || sDeviceManager->get_attr_uint8(node, ATA_ADAPTER_INTNUM, &intnum, true) != B_OK
382 || sDeviceManager->get_attr_uint8(node, ATA_ADAPTER_CHANNEL_INDEX, &channel_index, false) != B_OK)
383 return B_ERROR;
384
385 {
386 device_node *parent = sDeviceManager->get_parent_node(node);
387 sDeviceManager->get_driver(parent, NULL, (void **)&controller);
388 sDeviceManager->put_node(parent);
389 }
390
391 channel = (ata_adapter_channel_info *)malloc(total_data_size);
392 if (channel == NULL) {
393 res = B_NO_MEMORY;
394 goto err;
395 }
396
397 TRACE("PCI-ATA: channel index %d\n", channel_index);
398
399 channel->node = node;
400 channel->pci = controller->pci;
401 channel->device = controller->device;
402 channel->lost = false;
403 channel->command_block_base = command_block_base;
404 channel->control_block_base = control_block_base;
405 channel->bus_master_base = controller->bus_master_base + (channel_index * 8);
406 channel->intnum = intnum;
407 channel->dmaing = false;
408 channel->inthand = inthand;
409
410 TRACE("PCI-ATA: bus master base %#x\n", channel->bus_master_base);
411
412 // PRDT must be contiguous, dword-aligned and must not cross 64K boundary
413 // TODO: Where's the handling for the 64 K boundary? create_area_etc() can be
414 // used.
415 prdt_size = (ATA_ADAPTER_MAX_SG_COUNT * sizeof( prd_entry ) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1);
416 channel->prd_area = create_area("prd", (void **)&channel->prdt, B_ANY_KERNEL_ADDRESS,
417 prdt_size, B_32_BIT_CONTIGUOUS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA);
418 if (channel->prd_area < B_OK) {
419 res = channel->prd_area;
420 goto err2;
421 }
422
423 get_memory_map(channel->prdt, prdt_size, pe, 1);
424 channel->prdt_phys = pe[0].address;
425
426 SHOW_FLOW(3, "virt=%p, phys=%x", channel->prdt, (int)channel->prdt_phys);
427
428 res = install_io_interrupt_handler(channel->intnum,
429 inthand, channel, 0);
430
431 if (res < 0) {
432 SHOW_ERROR(0, "couldn't install irq handler @%d", channel->intnum);
433 goto err3;
434 }
435
436 TRACE("PCI-ATA: init channel done\n");
437
438 // disable interrupts
439 ata_adapter_write_device_control(channel, ATA_DEVICE_CONTROL_BIT3 | ATA_DEVICE_CONTROL_DISABLE_INTS);
440
441 *cookie = channel;
442
443 return B_OK;
444
445 err3:
446 delete_area(channel->prd_area);
447 err2:
448 err:
449 free(channel);
450
451 return res;
452 }
453
454
455 static void
ata_adapter_uninit_channel(ata_adapter_channel_info * channel)456 ata_adapter_uninit_channel(ata_adapter_channel_info *channel)
457 {
458 // disable IRQs
459 ata_adapter_write_device_control(channel, ATA_DEVICE_CONTROL_BIT3 | ATA_DEVICE_CONTROL_DISABLE_INTS);
460
461 // catch spurious interrupt
462 // (some controllers generate an IRQ when you _disable_ interrupts,
463 // they are delayed by less then 40 µs, so 1 ms is safe)
464 snooze(1000);
465
466 remove_io_interrupt_handler(channel->intnum, channel->inthand, channel);
467
468 delete_area(channel->prd_area);
469 free(channel);
470 }
471
472
473 static void
ata_adapter_channel_removed(ata_adapter_channel_info * channel)474 ata_adapter_channel_removed(ata_adapter_channel_info *channel)
475 {
476 SHOW_FLOW0( 3, "" );
477
478 if (channel != NULL)
479 // disable access instantly
480 atomic_or((int32*)&channel->lost, 1);
481 }
482
483
484 /** publish node of ata channel */
485
486 static status_t
ata_adapter_publish_channel(device_node * controller_node,const char * channel_module_name,uint16 command_block_base,uint16 control_block_base,uint8 intnum,bool can_dma,uint8 channel_index,const char * name,const io_resource * resources,device_node ** node)487 ata_adapter_publish_channel(device_node *controller_node,
488 const char *channel_module_name, uint16 command_block_base,
489 uint16 control_block_base, uint8 intnum, bool can_dma,
490 uint8 channel_index, const char *name, const io_resource *resources,
491 device_node **node)
492 {
493 char prettyName[25];
494 sprintf(prettyName, "ATA Channel %" B_PRIu8, channel_index);
495
496 device_attr attrs[] = {
497 // info about ourself and our consumer
498 { B_DEVICE_PRETTY_NAME, B_STRING_TYPE,
499 { .string = prettyName }},
500 { B_DEVICE_FIXED_CHILD, B_STRING_TYPE,
501 { .string = ATA_FOR_CONTROLLER_MODULE_NAME }},
502
503 // private data to identify channel
504 { ATA_ADAPTER_COMMAND_BLOCK_BASE, B_UINT16_TYPE,
505 { .ui16 = command_block_base }},
506 { ATA_ADAPTER_CONTROL_BLOCK_BASE, B_UINT16_TYPE,
507 { .ui16 = control_block_base }},
508 { ATA_CONTROLLER_CAN_DMA_ITEM, B_UINT8_TYPE, { .ui8 = can_dma }},
509 { ATA_ADAPTER_INTNUM, B_UINT8_TYPE, { .ui8 = intnum }},
510 { ATA_ADAPTER_CHANNEL_INDEX, B_UINT8_TYPE, { .ui8 = channel_index }},
511 { NULL }
512 };
513
514 SHOW_FLOW0(2, "");
515
516 return sDeviceManager->register_node(controller_node, channel_module_name, attrs,
517 resources, node);
518 }
519
520
521 /** detect IDE channel */
522
523 static status_t
ata_adapter_detect_channel(pci_device_module_info * pci,pci_device * pci_device,device_node * controller_node,const char * channel_module_name,bool controller_can_dma,uint16 command_block_base,uint16 control_block_base,uint16 bus_master_base,uint8 intnum,uint8 channel_index,const char * name,device_node ** node,bool supports_compatibility_mode)524 ata_adapter_detect_channel(pci_device_module_info *pci, pci_device *pci_device,
525 device_node *controller_node, const char *channel_module_name,
526 bool controller_can_dma, uint16 command_block_base, uint16 control_block_base,
527 uint16 bus_master_base, uint8 intnum, uint8 channel_index, const char *name,
528 device_node **node, bool supports_compatibility_mode)
529 {
530 uint8 api;
531 uint16 pcicmdOld;
532 uint16 pcicmdNew;
533 uint16 pciVendor;
534
535 SHOW_FLOW0( 3, "" );
536
537 // if channel works in compatibility mode, addresses and interrupt are fixed
538 api = pci->read_pci_config(pci_device, PCI_class_api, 1);
539
540 if (supports_compatibility_mode
541 && channel_index == 0 && (api & PCI_ide_primary_native) == 0) {
542 command_block_base = 0x1f0;
543 control_block_base = 0x3f6;
544 intnum = 14;
545 TRACE("PCI-ATA: Controller in legacy mode: cmd %#x, ctrl %#x, irq %d\n",
546 command_block_base, control_block_base, intnum);
547 } else if (supports_compatibility_mode
548 && channel_index == 1 && (api & PCI_ide_secondary_native) == 0) {
549 command_block_base = 0x170;
550 control_block_base = 0x376;
551 intnum = 15;
552 TRACE("PCI-ATA: Controller in legacy mode: cmd %#x, ctrl %#x, irq %d\n",
553 command_block_base, control_block_base, intnum);
554 } else {
555 if (command_block_base == 0 || control_block_base == 0) {
556 TRACE("PCI-ATA: Command/Control Block base is not configured\n");
557 return B_ERROR;
558 }
559 if (intnum == 0 || intnum == 0xff) {
560 TRACE("PCI-ATA: Interrupt is not configured\n");
561 return B_ERROR;
562 }
563
564 // historically, they start at 3f6h/376h, but PCI spec requires registers
565 // to be aligned at 4 bytes, so only 3f4h/374h can be specified; thus
566 // PCI IDE defines that control block starts at offset 2
567 control_block_base += 2;
568 TRACE("PCI-ATA: Controller in native mode: cmd %#x, ctrl %#x, irq %d\n",
569 command_block_base, control_block_base, intnum);
570 }
571
572
573 // this should be done in ata_adapter_init_controller but there is crashes
574 pcicmdOld = pcicmdNew = pci->read_pci_config(pci_device, PCI_command, 2);
575 if ((pcicmdNew & (1 << 10)) != 0) {
576 TRACE("PCI-ATA: enabling interrupts\n");
577 pcicmdNew &= ~(1 << 10);
578 }
579 if ((pcicmdNew & PCI_command_io) == 0) {
580 TRACE("PCI-ATA: enabling io decoder\n");
581 pcicmdNew |= PCI_command_io;
582 }
583 if ((pcicmdNew & PCI_command_master) == 0) {
584 TRACE("PCI-ATA: enabling bus mastering\n");
585 pcicmdNew |= PCI_command_master;
586 }
587 if (pcicmdOld != pcicmdNew) {
588 pci->write_pci_config(pci_device, PCI_command, 2, pcicmdNew);
589 TRACE("PCI-ATA: pcicmd changed from 0x%04x to 0x%04x\n",
590 pcicmdOld, pcicmdNew);
591 }
592
593
594 if (supports_compatibility_mode) {
595 // read status of primary(!) channel to detect simplex
596 uint8 status = pci->read_io_8(pci_device, bus_master_base
597 + ATA_BM_STATUS_REG);
598
599 if (status & ATA_BM_STATUS_SIMPLEX_DMA && channel_index != 0) {
600 // in simplex mode, channels cannot operate independantly of each other;
601 // we simply disable bus mastering of second channel to satisfy that;
602 // better were to use a controller lock, but this had to be done in the IDE
603 // bus manager, and I don't see any reason to add extra code for old
604 // simplex controllers
605
606 // Intel controllers use this bit for something else and are not simplex.
607 pciVendor = pci->read_pci_config(pci_device, PCI_vendor_id, 2);
608
609 if (pciVendor != 0x8086) {
610 TRACE("PCI-ATA: Simplex controller - disabling DMA of secondary channel\n");
611 controller_can_dma = false;
612 } else {
613 TRACE("PCI-ATA: Simplex bit ignored - Intel controller\n");
614 }
615 }
616 }
617
618 {
619 io_resource resources[3] = {
620 { B_IO_PORT, command_block_base, 8 },
621 { B_IO_PORT, control_block_base, 1 },
622 {}
623 };
624
625 return ata_adapter_publish_channel(controller_node, channel_module_name,
626 command_block_base, control_block_base, intnum, controller_can_dma,
627 channel_index, name, resources, node);
628 }
629 }
630
631
632 static status_t
ata_adapter_init_controller(device_node * node,ata_adapter_controller_info ** cookie,size_t total_data_size)633 ata_adapter_init_controller(device_node *node,
634 ata_adapter_controller_info **cookie, size_t total_data_size)
635 {
636 pci_device_module_info *pci;
637 pci_device *device;
638 ata_adapter_controller_info *controller;
639 uint16 bus_master_base;
640
641 // get device data
642 if (sDeviceManager->get_attr_uint16(node, ATA_ADAPTER_BUS_MASTER_BASE, &bus_master_base, false) != B_OK)
643 return B_ERROR;
644
645 {
646 device_node *parent = sDeviceManager->get_parent_node(node);
647 sDeviceManager->get_driver(parent, (driver_module_info **)&pci, (void **)&device);
648 sDeviceManager->put_node(parent);
649 }
650
651 controller = (ata_adapter_controller_info *)malloc(total_data_size);
652 if (controller == NULL)
653 return B_NO_MEMORY;
654
655 #if 0
656 pcicmdOld = pcicmdNew = pci->read_pci_config(node, PCI_command, 2);
657 if ((pcicmdNew & PCI_command_io) == 0) {
658 TRACE("PCI-ATA: adapter init: enabling io decoder\n");
659 pcicmdNew |= PCI_command_io;
660 }
661 if ((pcicmdNew & PCI_command_master) == 0) {
662 TRACE("PCI-ATA: adapter init: enabling bus mastering\n");
663 pcicmdNew |= PCI_command_master;
664 }
665 if (pcicmdOld != pcicmdNew) {
666 pci->write_pci_config(node, PCI_command, 2, pcicmdNew);
667 TRACE("PCI-ATA: adapter init: pcicmd old 0x%04x, new 0x%04x\n",
668 pcicmdOld, pcicmdNew);
669 }
670 #endif
671
672 controller->node = node;
673 controller->pci = pci;
674 controller->device = device;
675 controller->lost = false;
676 controller->bus_master_base = bus_master_base;
677
678 *cookie = controller;
679
680 return B_OK;
681 }
682
683
684 static void
ata_adapter_uninit_controller(ata_adapter_controller_info * controller)685 ata_adapter_uninit_controller(ata_adapter_controller_info *controller)
686 {
687 free(controller);
688 }
689
690
691 static void
ata_adapter_controller_removed(ata_adapter_controller_info * controller)692 ata_adapter_controller_removed(ata_adapter_controller_info *controller)
693 {
694 SHOW_FLOW0(3, "");
695
696 if (controller != NULL) {
697 // disable access instantly; unit_device takes care of unregistering ioports
698 atomic_or((int32*)&controller->lost, 1);
699 }
700 }
701
702
703 /** publish node of ata controller */
704
705 static status_t
ata_adapter_publish_controller(device_node * parent,uint16 bus_master_base,io_resource * resources,const char * controller_driver,const char * controller_driver_type,const char * controller_name,bool can_dma,bool can_cq,uint32 dma_alignment,uint32 dma_boundary,uint32 max_sg_block_size,device_node ** node)706 ata_adapter_publish_controller(device_node *parent, uint16 bus_master_base,
707 io_resource *resources, const char *controller_driver,
708 const char *controller_driver_type, const char *controller_name, bool can_dma,
709 bool can_cq, uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size,
710 device_node **node)
711 {
712 device_attr attrs[] = {
713 // properties of this controller for ata bus manager
714 // there are always max. 2 devices
715 // (unless this is a Compact Flash Card with a built-in IDE controller,
716 // which has exactly 1 device)
717 { ATA_CONTROLLER_MAX_DEVICES_ITEM, B_UINT8_TYPE, { .ui8 = 2 }},
718 // of course we can DMA
719 { ATA_CONTROLLER_CAN_DMA_ITEM, B_UINT8_TYPE, { .ui8 = can_dma }},
720 // choose any name here
721 { ATA_CONTROLLER_CONTROLLER_NAME_ITEM, B_STRING_TYPE,
722 { .string = controller_name }},
723
724 // DMA properties
725 // data must be word-aligned;
726 // warning: some controllers are more picky!
727 { B_DMA_ALIGNMENT, B_UINT32_TYPE, { .ui32 = dma_alignment /*1*/}},
728 // one S/G block must not cross 64K boundary
729 { B_DMA_BOUNDARY, B_UINT32_TYPE, { .ui32 = dma_boundary/*0xffff*/ }},
730 // max size of S/G block is 16 bits with zero being 64K
731 { B_DMA_MAX_SEGMENT_BLOCKS, B_UINT32_TYPE,
732 { .ui32 = max_sg_block_size/*0x10000*/ }},
733 { B_DMA_MAX_SEGMENT_COUNT, B_UINT32_TYPE,
734 { .ui32 = ATA_ADAPTER_MAX_SG_COUNT }},
735 { B_DMA_HIGH_ADDRESS, B_UINT64_TYPE, { .ui64 = 0x100000000LL }},
736
737 // private data to find controller
738 { ATA_ADAPTER_BUS_MASTER_BASE, B_UINT16_TYPE, { .ui16 = bus_master_base }},
739 { NULL }
740 };
741
742 SHOW_FLOW0( 2, "" );
743
744 return sDeviceManager->register_node(parent, controller_driver, attrs, resources, node);
745 }
746
747
748 /** detect pure IDE controller, i.e. without channels */
749
750 static status_t
ata_adapter_detect_controller(pci_device_module_info * pci,pci_device * pci_device,device_node * parent,uint16 bus_master_base,const char * controller_driver,const char * controller_driver_type,const char * controller_name,bool can_dma,bool can_cq,uint32 dma_alignment,uint32 dma_boundary,uint32 max_sg_block_size,device_node ** node)751 ata_adapter_detect_controller(pci_device_module_info *pci, pci_device *pci_device,
752 device_node *parent, uint16 bus_master_base, const char *controller_driver,
753 const char *controller_driver_type, const char *controller_name, bool can_dma,
754 bool can_cq, uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size,
755 device_node **node)
756 {
757 io_resource resources[2] = {
758 { B_IO_PORT, bus_master_base, 16 },
759 {}
760 };
761
762 SHOW_FLOW0( 3, "" );
763
764 if (bus_master_base == 0) {
765 TRACE("PCI-ATA: Controller detection failed! bus master base not configured\n");
766 return B_ERROR;
767 }
768
769 return ata_adapter_publish_controller(parent, bus_master_base, resources,
770 controller_driver, controller_driver_type, controller_name, can_dma, can_cq,
771 dma_alignment, dma_boundary, max_sg_block_size, node);
772 }
773
774
775 static status_t
ata_adapter_probe_controller(device_node * parent,const char * controller_driver,const char * controller_driver_type,const char * controller_name,const char * channel_module_name,bool can_dma,bool can_cq,uint32 dma_alignment,uint32 dma_boundary,uint32 max_sg_block_size,bool supports_compatibility_mode)776 ata_adapter_probe_controller(device_node *parent, const char *controller_driver,
777 const char *controller_driver_type, const char *controller_name,
778 const char *channel_module_name, bool can_dma, bool can_cq, uint32 dma_alignment,
779 uint32 dma_boundary, uint32 max_sg_block_size, bool supports_compatibility_mode)
780 {
781 pci_device_module_info *pci;
782 pci_device *device;
783 uint16 command_block_base[2];
784 uint16 control_block_base[2];
785 uint16 bus_master_base;
786 device_node *controller_node;
787 device_node *channels[2];
788 uint8 intnum;
789 status_t res;
790
791 SHOW_FLOW0( 3, "" );
792
793 sDeviceManager->get_driver(parent, (driver_module_info **)&pci, (void **)&device);
794
795 command_block_base[0] = pci->read_pci_config(device, PCI_base_registers, 4 );
796 control_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 4, 4);
797 command_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 8, 4);
798 control_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 12, 4);
799 bus_master_base = pci->read_pci_config(device, PCI_base_registers + 16, 4);
800 intnum = pci->read_pci_config(device, PCI_interrupt_line, 1);
801
802 command_block_base[0] &= PCI_address_io_mask;
803 control_block_base[0] &= PCI_address_io_mask;
804 command_block_base[1] &= PCI_address_io_mask;
805 control_block_base[1] &= PCI_address_io_mask;
806 bus_master_base &= PCI_address_io_mask;
807
808 res = ata_adapter_detect_controller(pci, device, parent, bus_master_base,
809 controller_driver, controller_driver_type, controller_name, can_dma,
810 can_cq, dma_alignment, dma_boundary, max_sg_block_size, &controller_node);
811 // don't register if controller is already registered!
812 // (happens during rescan; registering new channels would kick out old channels)
813 if (res != B_OK || controller_node == NULL)
814 return res;
815
816 // ignore errors during registration of channels - could be a simple rescan collision
817 ata_adapter_detect_channel(pci, device, controller_node, channel_module_name,
818 can_dma, command_block_base[0], control_block_base[0], bus_master_base,
819 intnum, 0, "Primary Channel", &channels[0], supports_compatibility_mode);
820
821 ata_adapter_detect_channel(pci, device, controller_node, channel_module_name,
822 can_dma, command_block_base[1], control_block_base[1], bus_master_base,
823 intnum, 1, "Secondary Channel", &channels[1], supports_compatibility_mode);
824
825 return B_OK;
826 }
827
828
829 static status_t
std_ops(int32 op,...)830 std_ops(int32 op, ...)
831 {
832 switch (op) {
833 case B_MODULE_INIT:
834 case B_MODULE_UNINIT:
835 return B_OK;
836
837 default:
838 return B_ERROR;
839 }
840 }
841
842
843 module_dependency module_dependencies[] = {
844 { ATA_FOR_CONTROLLER_MODULE_NAME, (module_info **)&sATA },
845 { B_DEVICE_MANAGER_MODULE_NAME, (module_info **)&sDeviceManager },
846 {}
847 };
848
849
850 static ata_adapter_interface adapter_interface = {
851 {
852 ATA_ADAPTER_MODULE_NAME,
853 0,
854 std_ops
855 },
856
857 set_channel,
858
859 ata_adapter_write_command_block_regs,
860 ata_adapter_read_command_block_regs,
861
862 ata_adapter_get_altstatus,
863 ata_adapter_write_device_control,
864
865 ata_adapter_write_pio,
866 ata_adapter_read_pio,
867
868 ata_adapter_prepare_dma,
869 ata_adapter_start_dma,
870 ata_adapter_finish_dma,
871
872 ata_adapter_inthand,
873
874 ata_adapter_init_channel,
875 ata_adapter_uninit_channel,
876 ata_adapter_channel_removed,
877
878 ata_adapter_publish_channel,
879 ata_adapter_detect_channel,
880
881 ata_adapter_init_controller,
882 ata_adapter_uninit_controller,
883 ata_adapter_controller_removed,
884
885 ata_adapter_publish_controller,
886 ata_adapter_detect_controller,
887
888 ata_adapter_probe_controller
889 };
890
891 module_info *modules[] = {
892 &adapter_interface.info,
893 NULL
894 };
895