1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 /*
37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/taskqueue.h>
46 #include <sys/bus.h>
47
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/if_media.h>
52
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55 #include "miidevs.h"
56
57 #include <dev/mii/rgephyreg.h>
58
59 #include "miibus_if.h"
60
61 #include <machine/bus.h>
62 #include <dev/rl/if_rlreg.h>
63
64 static int rgephy_probe(device_t);
65 static int rgephy_attach(device_t);
66
67 static device_method_t rgephy_methods[] = {
68 /* device interface */
69 DEVMETHOD(device_probe, rgephy_probe),
70 DEVMETHOD(device_attach, rgephy_attach),
71 DEVMETHOD(device_detach, mii_phy_detach),
72 DEVMETHOD(device_shutdown, bus_generic_shutdown),
73 DEVMETHOD_END
74 };
75
76 static driver_t rgephy_driver = {
77 "rgephy",
78 rgephy_methods,
79 sizeof(struct mii_softc)
80 };
81
82 DRIVER_MODULE(rgephy, miibus, rgephy_driver, 0, 0);
83
84 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
85 static void rgephy_status(struct mii_softc *);
86 static int rgephy_mii_phy_auto(struct mii_softc *, int);
87 static void rgephy_reset(struct mii_softc *);
88 static int rgephy_linkup(struct mii_softc *);
89 static void rgephy_loop(struct mii_softc *);
90 static void rgephy_load_dspcode(struct mii_softc *);
91 static void rgephy_disable_eee(struct mii_softc *);
92
93 static const struct mii_phydesc rgephys[] = {
94 MII_PHY_DESC(REALTEK, RTL8169S),
95 MII_PHY_DESC(REALTEK, RTL8251),
96 MII_PHY_END
97 };
98
99 static const struct mii_phy_funcs rgephy_funcs = {
100 rgephy_service,
101 rgephy_status,
102 rgephy_reset
103 };
104
105 static int
rgephy_probe(device_t dev)106 rgephy_probe(device_t dev)
107 {
108
109 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
110 }
111
112 static int
rgephy_attach(device_t dev)113 rgephy_attach(device_t dev)
114 {
115 struct mii_softc *sc;
116 u_int flags;
117
118 sc = device_get_softc(dev);
119 flags = 0;
120 if (mii_dev_mac_match(dev, "re"))
121 flags |= MIIF_PHYPRIV0;
122 else if (mii_dev_mac_match(dev, "ure"))
123 flags |= MIIF_PHYPRIV1;
124 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0);
125
126 /* RTL8169S do not report auto-sense; add manually. */
127 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
128 sc->mii_capmask;
129 if (sc->mii_capabilities & BMSR_EXTSTAT)
130 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
131 device_printf(dev, " ");
132 mii_phy_add_media(sc);
133 printf("\n");
134 /*
135 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with
136 * manual configuration, which is used to work around issues with
137 * certain setups by default, should not be triggered as it may in
138 * turn cause harm in some edge cases.
139 */
140 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0;
141
142 PHY_RESET(sc);
143
144 MIIBUS_MEDIAINIT(sc->mii_dev);
145 return (0);
146 }
147
148 static int
rgephy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)149 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
150 {
151 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
152 int speed, gig, anar;
153
154 switch (cmd) {
155 case MII_POLLSTAT:
156 break;
157
158 case MII_MEDIACHG:
159 PHY_RESET(sc); /* XXX hardware bug work-around */
160
161 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
162 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
163 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
164 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
165
166 switch (IFM_SUBTYPE(ife->ifm_media)) {
167 case IFM_AUTO:
168 #ifdef foo
169 /*
170 * If we're already in auto mode, just return.
171 */
172 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
173 return (0);
174 #endif
175 (void)rgephy_mii_phy_auto(sc, ife->ifm_media);
176 break;
177 case IFM_1000_T:
178 speed = RGEPHY_S1000;
179 goto setit;
180 case IFM_100_TX:
181 speed = RGEPHY_S100;
182 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
183 goto setit;
184 case IFM_10_T:
185 speed = RGEPHY_S10;
186 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
187 setit:
188 if ((ife->ifm_media & IFM_FLOW) != 0 &&
189 (mii->mii_media.ifm_media & IFM_FLAG0) != 0)
190 return (EINVAL);
191
192 if ((ife->ifm_media & IFM_FDX) != 0) {
193 speed |= RGEPHY_BMCR_FDX;
194 gig = RGEPHY_1000CTL_AFD;
195 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
196 if ((ife->ifm_media & IFM_FLOW) != 0 ||
197 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
198 anar |=
199 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
200 } else {
201 gig = RGEPHY_1000CTL_AHD;
202 anar &=
203 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
204 }
205 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
206 gig |= RGEPHY_1000CTL_MSE;
207 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
208 gig |= RGEPHY_1000CTL_MSC;
209 } else {
210 gig = 0;
211 anar &= ~RGEPHY_ANAR_ASP;
212 }
213 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0)
214 speed |=
215 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG;
216 rgephy_loop(sc);
217 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
218 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
219 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
220 break;
221 case IFM_NONE:
222 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
223 break;
224 default:
225 return (EINVAL);
226 }
227 break;
228
229 case MII_TICK:
230 /*
231 * Only used for autonegotiation.
232 */
233 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
234 sc->mii_ticks = 0;
235 break;
236 }
237
238 /*
239 * Check to see if we have link. If we do, we don't
240 * need to restart the autonegotiation process.
241 */
242 if (rgephy_linkup(sc) != 0) {
243 sc->mii_ticks = 0;
244 break;
245 }
246
247 /* Announce link loss right after it happens. */
248 if (sc->mii_ticks++ == 0)
249 break;
250
251 /* Only retry autonegotiation every mii_anegticks seconds. */
252 if (sc->mii_ticks <= sc->mii_anegticks)
253 return (0);
254
255 sc->mii_ticks = 0;
256 rgephy_mii_phy_auto(sc, ife->ifm_media);
257 break;
258 }
259
260 /* Update the media status. */
261 PHY_STATUS(sc);
262
263 /*
264 * Callback if something changed. Note that we need to poke
265 * the DSP on the RealTek PHYs if the media changes.
266 *
267 */
268 if (sc->mii_media_active != mii->mii_media_active ||
269 sc->mii_media_status != mii->mii_media_status ||
270 cmd == MII_MEDIACHG) {
271 rgephy_load_dspcode(sc);
272 }
273 mii_phy_update(sc, cmd);
274 return (0);
275 }
276
277 static int
rgephy_linkup(struct mii_softc * sc)278 rgephy_linkup(struct mii_softc *sc)
279 {
280 int linkup;
281 uint16_t reg;
282
283 linkup = 0;
284 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
285 sc->mii_mpd_rev >= RGEPHY_8211B) {
286 if (sc->mii_mpd_rev == RGEPHY_8211F) {
287 reg = PHY_READ(sc, RGEPHY_F_MII_SSR);
288 if (reg & RGEPHY_F_SSR_LINK)
289 linkup++;
290 } else {
291 reg = PHY_READ(sc, RGEPHY_MII_SSR);
292 if (reg & RGEPHY_SSR_LINK)
293 linkup++;
294 }
295 } else {
296 if (sc->mii_flags & MIIF_PHYPRIV1)
297 reg = PHY_READ(sc, URE_GMEDIASTAT);
298 else
299 reg = PHY_READ(sc, RL_GMEDIASTAT);
300 if (reg & RL_GMEDIASTAT_LINK)
301 linkup++;
302 }
303
304 return (linkup);
305 }
306
307 static void
rgephy_status(struct mii_softc * sc)308 rgephy_status(struct mii_softc *sc)
309 {
310 struct mii_data *mii = sc->mii_pdata;
311 int bmsr, bmcr;
312 uint16_t ssr;
313
314 mii->mii_media_status = IFM_AVALID;
315 mii->mii_media_active = IFM_ETHER;
316
317 if (rgephy_linkup(sc) != 0)
318 mii->mii_media_status |= IFM_ACTIVE;
319
320 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
321 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
322 if (bmcr & RGEPHY_BMCR_ISO) {
323 mii->mii_media_active |= IFM_NONE;
324 mii->mii_media_status = 0;
325 return;
326 }
327
328 if (bmcr & RGEPHY_BMCR_LOOP)
329 mii->mii_media_active |= IFM_LOOP;
330
331 if (bmcr & RGEPHY_BMCR_AUTOEN) {
332 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
333 /* Erg, still trying, I guess... */
334 mii->mii_media_active |= IFM_NONE;
335 return;
336 }
337 }
338
339 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
340 sc->mii_mpd_rev >= RGEPHY_8211B) {
341 if (sc->mii_mpd_rev == RGEPHY_8211F) {
342 ssr = PHY_READ(sc, RGEPHY_F_MII_SSR);
343 switch (ssr & RGEPHY_F_SSR_SPD_MASK) {
344 case RGEPHY_F_SSR_S1000:
345 mii->mii_media_active |= IFM_1000_T;
346 break;
347 case RGEPHY_F_SSR_S100:
348 mii->mii_media_active |= IFM_100_TX;
349 break;
350 case RGEPHY_F_SSR_S10:
351 mii->mii_media_active |= IFM_10_T;
352 break;
353 default:
354 mii->mii_media_active |= IFM_NONE;
355 break;
356 }
357 if (ssr & RGEPHY_F_SSR_FDX)
358 mii->mii_media_active |= IFM_FDX;
359 else
360 mii->mii_media_active |= IFM_HDX;
361
362 } else {
363 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
364 switch (ssr & RGEPHY_SSR_SPD_MASK) {
365 case RGEPHY_SSR_S1000:
366 mii->mii_media_active |= IFM_1000_T;
367 break;
368 case RGEPHY_SSR_S100:
369 mii->mii_media_active |= IFM_100_TX;
370 break;
371 case RGEPHY_SSR_S10:
372 mii->mii_media_active |= IFM_10_T;
373 break;
374 default:
375 mii->mii_media_active |= IFM_NONE;
376 break;
377 }
378 if (ssr & RGEPHY_SSR_FDX)
379 mii->mii_media_active |= IFM_FDX;
380 else
381 mii->mii_media_active |= IFM_HDX;
382 }
383 } else {
384 if (sc->mii_flags & MIIF_PHYPRIV1)
385 bmsr = PHY_READ(sc, URE_GMEDIASTAT);
386 else
387 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
388 if (bmsr & RL_GMEDIASTAT_1000MBPS)
389 mii->mii_media_active |= IFM_1000_T;
390 else if (bmsr & RL_GMEDIASTAT_100MBPS)
391 mii->mii_media_active |= IFM_100_TX;
392 else if (bmsr & RL_GMEDIASTAT_10MBPS)
393 mii->mii_media_active |= IFM_10_T;
394 else
395 mii->mii_media_active |= IFM_NONE;
396 if (bmsr & RL_GMEDIASTAT_FDX)
397 mii->mii_media_active |= IFM_FDX;
398 else
399 mii->mii_media_active |= IFM_HDX;
400 }
401
402 if ((mii->mii_media_active & IFM_FDX) != 0)
403 mii->mii_media_active |= mii_phy_flowstatus(sc);
404
405 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
406 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
407 mii->mii_media_active |= IFM_ETH_MASTER;
408 }
409
410 static int
rgephy_mii_phy_auto(struct mii_softc * sc,int media)411 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
412 {
413 int anar;
414
415 rgephy_loop(sc);
416 PHY_RESET(sc);
417
418 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
419 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
420 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
421 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
422 DELAY(1000);
423 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
424 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
425 DELAY(1000);
426 PHY_WRITE(sc, RGEPHY_MII_BMCR,
427 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
428 DELAY(100);
429
430 return (EJUSTRETURN);
431 }
432
433 static void
rgephy_loop(struct mii_softc * sc)434 rgephy_loop(struct mii_softc *sc)
435 {
436 int i;
437
438 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
439 sc->mii_mpd_rev < RGEPHY_8211B) {
440 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
441 DELAY(1000);
442 }
443
444 for (i = 0; i < 15000; i++) {
445 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
446 #if 0
447 device_printf(sc->mii_dev, "looped %d\n", i);
448 #endif
449 break;
450 }
451 DELAY(10);
452 }
453 }
454
455 #define PHY_SETBIT(x, y, z) \
456 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
457 #define PHY_CLRBIT(x, y, z) \
458 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
459
460 /*
461 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
462 * existing revisions of the 8169S/8110S chips need to be tuned in
463 * order to reliably negotiate a 1000Mbps link. This is only needed
464 * for rev 0 and rev 1 of the PHY. Later versions work without
465 * any fixups.
466 */
467 static void
rgephy_load_dspcode(struct mii_softc * sc)468 rgephy_load_dspcode(struct mii_softc *sc)
469 {
470 int val;
471
472 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 ||
473 sc->mii_mpd_rev >= RGEPHY_8211B)
474 return;
475
476 PHY_WRITE(sc, 31, 0x0001);
477 PHY_WRITE(sc, 21, 0x1000);
478 PHY_WRITE(sc, 24, 0x65C7);
479 PHY_CLRBIT(sc, 4, 0x0800);
480 val = PHY_READ(sc, 4) & 0xFFF;
481 PHY_WRITE(sc, 4, val);
482 PHY_WRITE(sc, 3, 0x00A1);
483 PHY_WRITE(sc, 2, 0x0008);
484 PHY_WRITE(sc, 1, 0x1020);
485 PHY_WRITE(sc, 0, 0x1000);
486 PHY_SETBIT(sc, 4, 0x0800);
487 PHY_CLRBIT(sc, 4, 0x0800);
488 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
489 PHY_WRITE(sc, 4, val);
490 PHY_WRITE(sc, 3, 0xFF41);
491 PHY_WRITE(sc, 2, 0xDE60);
492 PHY_WRITE(sc, 1, 0x0140);
493 PHY_WRITE(sc, 0, 0x0077);
494 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
495 PHY_WRITE(sc, 4, val);
496 PHY_WRITE(sc, 3, 0xDF01);
497 PHY_WRITE(sc, 2, 0xDF20);
498 PHY_WRITE(sc, 1, 0xFF95);
499 PHY_WRITE(sc, 0, 0xFA00);
500 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
501 PHY_WRITE(sc, 4, val);
502 PHY_WRITE(sc, 3, 0xFF41);
503 PHY_WRITE(sc, 2, 0xDE20);
504 PHY_WRITE(sc, 1, 0x0140);
505 PHY_WRITE(sc, 0, 0x00BB);
506 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
507 PHY_WRITE(sc, 4, val);
508 PHY_WRITE(sc, 3, 0xDF01);
509 PHY_WRITE(sc, 2, 0xDF20);
510 PHY_WRITE(sc, 1, 0xFF95);
511 PHY_WRITE(sc, 0, 0xBF00);
512 PHY_SETBIT(sc, 4, 0x0800);
513 PHY_CLRBIT(sc, 4, 0x0800);
514 PHY_WRITE(sc, 31, 0x0000);
515
516 DELAY(40);
517 }
518
519 static void
rgephy_reset(struct mii_softc * sc)520 rgephy_reset(struct mii_softc *sc)
521 {
522 uint16_t pcr, ssr;
523
524 switch (sc->mii_mpd_rev) {
525 case RGEPHY_8211F:
526 pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1);
527 pcr &= ~(RGEPHY_F_PCR1_MDI_MM | RGEPHY_F_PCR1_ALDPS_EN);
528 PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr);
529 rgephy_disable_eee(sc);
530 break;
531 case RGEPHY_8211C:
532 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) {
533 /* RTL8211C(L) */
534 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
535 if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
536 ssr &= ~RGEPHY_SSR_ALDPS;
537 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
538 }
539 }
540 /* FALLTHROUGH */
541 default:
542 if (sc->mii_mpd_rev >= RGEPHY_8211B) {
543 pcr = PHY_READ(sc, RGEPHY_MII_PCR);
544 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) {
545 pcr &= ~RGEPHY_PCR_MDI_MASK;
546 pcr |= RGEPHY_PCR_MDIX_AUTO;
547 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
548 }
549 }
550 break;
551 }
552
553 mii_phy_reset(sc);
554 DELAY(1000);
555 rgephy_load_dspcode(sc);
556 }
557
558 static void
rgephy_disable_eee(struct mii_softc * sc)559 rgephy_disable_eee(struct mii_softc *sc)
560 {
561 uint16_t anar;
562
563 PHY_WRITE(sc, RGEPHY_F_EPAGSR, 0x0000);
564 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS |
565 (MMDACR_DADDRMASK & RGEPHY_F_MMD_DEV_7));
566 PHY_WRITE(sc, MII_MMDAADR, RGEPHY_F_MMD_EEEAR);
567 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI |
568 (MMDACR_DADDRMASK & RGEPHY_F_MMD_DEV_7));
569 PHY_WRITE(sc, MII_MMDAADR, 0x0000);
570 PHY_WRITE(sc, MII_MMDACR, 0x0000);
571 /*
572 * XXX
573 * Restart auto-negotiation to take changes effect.
574 * This may result in link establishment.
575 */
576 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
577 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
578 PHY_WRITE(sc, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AHD |
579 RGEPHY_1000CTL_AFD);
580 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_RESET |
581 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
582 }
583