1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 10 11 #include "hda_controller_defs.h" 12 13 #include <algorithm> 14 15 #include "driver.h" 16 #include "hda_codec_defs.h" 17 18 19 #define MAKE_RATE(base, multiply, divide) \ 20 ((base == 44100 ? FORMAT_44_1_BASE_RATE : 0) \ 21 | ((multiply - 1) << FORMAT_MULTIPLY_RATE_SHIFT) \ 22 | ((divide - 1) << FORMAT_DIVIDE_RATE_SHIFT)) 23 24 #define HDAC_INPUT_STREAM_OFFSET(controller, index) \ 25 ((index) * HDAC_STREAM_SIZE) 26 #define HDAC_OUTPUT_STREAM_OFFSET(controller, index) \ 27 (((controller)->num_input_streams + (index)) * HDAC_STREAM_SIZE) 28 #define HDAC_BIDIR_STREAM_OFFSET(controller, index) \ 29 (((controller)->num_input_streams + (controller)->num_output_streams \ 30 + (index)) * HDAC_STREAM_SIZE) 31 32 #define ALIGN(size, align) (((size) + align - 1) & ~(align - 1)) 33 #define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1)) 34 35 36 #define PCI_VENDOR_AMD 0x1002 37 #define PCI_VENDOR_CREATIVE 0x1102 38 #define PCI_VENDOR_INTEL 0x8086 39 #define PCI_VENDOR_NVIDIA 0x10de 40 #define PCI_ALL_DEVICES 0xffffffff 41 #define HDA_QUIRK_SNOOP 0x0001 42 #define HDA_QUIRK_NO_MSI 0x0002 43 44 45 static const struct { 46 uint32 vendor_id, device_id; 47 uint32 quirks; 48 } kControllerQuirks[] = { 49 { PCI_VENDOR_INTEL, 0x1c20, HDA_QUIRK_SNOOP }, 50 { PCI_VENDOR_INTEL, 0x1d20, HDA_QUIRK_SNOOP }, 51 { PCI_VENDOR_INTEL, 0x1e20, HDA_QUIRK_SNOOP }, 52 { PCI_VENDOR_INTEL, 0x8c20, HDA_QUIRK_SNOOP }, 53 { PCI_VENDOR_INTEL, 0x9c20, HDA_QUIRK_SNOOP }, 54 { PCI_VENDOR_INTEL, 0x9c21, HDA_QUIRK_SNOOP }, 55 { PCI_VENDOR_INTEL, 0x0c0c, HDA_QUIRK_SNOOP }, 56 { PCI_VENDOR_INTEL, 0x811b, HDA_QUIRK_SNOOP }, 57 { PCI_VENDOR_INTEL, 0x080a, HDA_QUIRK_SNOOP }, 58 // Enable snooping for ATI and Nvidia, right now for all their hda-devices, 59 // but only based on guessing. 60 { PCI_VENDOR_AMD, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP }, 61 { PCI_VENDOR_NVIDIA, PCI_ALL_DEVICES, HDA_QUIRK_SNOOP | HDA_QUIRK_NO_MSI }, 62 { PCI_VENDOR_CREATIVE, 0x0010, HDA_QUIRK_NO_MSI }, 63 { PCI_VENDOR_CREATIVE, 0x0012, HDA_QUIRK_NO_MSI } 64 }; 65 66 67 static const struct { 68 uint32 multi_rate; 69 uint32 hw_rate; 70 uint32 rate; 71 } kRates[] = { 72 {B_SR_8000, MAKE_RATE(48000, 1, 6), 8000}, 73 {B_SR_11025, MAKE_RATE(44100, 1, 4), 11025}, 74 {B_SR_16000, MAKE_RATE(48000, 1, 3), 16000}, 75 {B_SR_22050, MAKE_RATE(44100, 1, 2), 22050}, 76 {B_SR_32000, MAKE_RATE(48000, 2, 3), 32000}, 77 {B_SR_44100, MAKE_RATE(44100, 1, 1), 44100}, 78 {B_SR_48000, MAKE_RATE(48000, 1, 1), 48000}, 79 {B_SR_88200, MAKE_RATE(44100, 2, 1), 88200}, 80 {B_SR_96000, MAKE_RATE(48000, 2, 1), 96000}, 81 {B_SR_176400, MAKE_RATE(44100, 4, 1), 176400}, 82 {B_SR_192000, MAKE_RATE(48000, 4, 1), 192000}, 83 // this one is not supported by hardware. 84 // {B_SR_384000, MAKE_RATE(44100, ??, ??), 384000}, 85 }; 86 87 88 static uint32 89 get_controller_quirks(pci_info& info) 90 { 91 for (size_t i = 0; 92 i < sizeof(kControllerQuirks) / sizeof(kControllerQuirks[0]); i++) { 93 if (info.vendor_id == kControllerQuirks[i].vendor_id 94 && (kControllerQuirks[i].device_id == PCI_ALL_DEVICES 95 || kControllerQuirks[i].device_id == info.device_id)) 96 return kControllerQuirks[i].quirks; 97 } 98 return 0; 99 } 100 101 102 static inline void 103 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, 104 uint32 value, uint8 size) 105 { 106 uint32 originalValue = (gPci->read_pci_config)(controller->pci_info.bus, 107 controller->pci_info.device, controller->pci_info.function, reg, size); 108 (gPci->write_pci_config)(controller->pci_info.bus, 109 controller->pci_info.device, controller->pci_info.function, 110 reg, size, (originalValue & mask) | value); 111 } 112 113 114 static inline rirb_t& 115 current_rirb(hda_controller* controller) 116 { 117 return controller->rirb[controller->rirb_read_pos]; 118 } 119 120 121 static inline uint32 122 next_rirb(hda_controller* controller) 123 { 124 return (controller->rirb_read_pos + 1) % controller->rirb_length; 125 } 126 127 128 static inline uint32 129 next_corb(hda_controller* controller) 130 { 131 return (controller->corb_write_pos + 1) % controller->corb_length; 132 } 133 134 135 /*! Called with interrupts off. 136 Returns \c true, if the scheduler shall be invoked. 137 */ 138 static bool 139 stream_handle_interrupt(hda_controller* controller, hda_stream* stream, 140 uint32 index) 141 { 142 if (!stream->running) 143 return false; 144 145 uint8 status = stream->Read8(HDAC_STREAM_STATUS); 146 if (status == 0) 147 return false; 148 149 stream->Write8(HDAC_STREAM_STATUS, status); 150 151 if ((status & STATUS_FIFO_ERROR) != 0) 152 dprintf("hda: stream fifo error (id:%ld)\n", stream->id); 153 if ((status & STATUS_DESCRIPTOR_ERROR) != 0) 154 dprintf("hda: stream descriptor error (id:%ld)\n", stream->id); 155 156 if ((status & STATUS_BUFFER_COMPLETED) == 0) { 157 dprintf("hda: stream buffer not completed (id:%ld)\n", stream->id); 158 return false; 159 } 160 161 // Normally we should use the DMA position for the stream. Apparently there 162 // are broken chipsets, which don't support it correctly. If we detect this, 163 // we switch to using the LPIB instead. The link position is ahead of the 164 // DMA position for recording and behind for playback streams, but just 165 // for determining the currently active buffer, it should be good enough. 166 if (stream->use_dma_position && stream->incorrect_position_count >= 32) { 167 dprintf("hda: DMA position for stream (id:%ld) seems to be broken. " 168 "Switching to using LPIB.\n", stream->id); 169 stream->use_dma_position = false; 170 } 171 172 // Determine the buffer we're switching to. Some chipsets seem to trigger 173 // the interrupt before the DMA position in memory has been updated. We 174 // round it, so we still get the right buffer. 175 uint32 dmaPosition = stream->use_dma_position 176 ? controller->stream_positions[index * 2] 177 : stream->Read32(HDAC_STREAM_POSITION); 178 uint32 bufferIndex = ((dmaPosition + stream->buffer_size / 2) 179 / stream->buffer_size) % stream->num_buffers; 180 181 // get the current recording/playing position and the system time 182 uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION); 183 bigtime_t now = system_time(); 184 185 // compute the frame position for the byte position 186 uint32 linkFramePosition = 0; 187 while (linkBytePosition >= stream->buffer_size) { 188 linkFramePosition += stream->buffer_length; 189 linkBytePosition -= stream->buffer_size; 190 } 191 linkFramePosition += std::min( 192 linkBytePosition / (stream->num_channels * stream->sample_size), 193 stream->buffer_length); 194 195 // compute the number of frames processed since the previous interrupt 196 int32 framesProcessed = (int32)linkFramePosition 197 - (int32)stream->last_link_frame_position; 198 if (framesProcessed < 0) 199 framesProcessed += stream->num_buffers * stream->buffer_length; 200 stream->last_link_frame_position = linkFramePosition; 201 202 // update stream playing/recording state and notify buffer_exchange() 203 acquire_spinlock(&stream->lock); 204 205 if (bufferIndex == (stream->buffer_cycle + 1) % stream->num_buffers) 206 stream->incorrect_position_count = 0; 207 else 208 stream->incorrect_position_count++; 209 210 stream->real_time = now; 211 stream->frames_count += framesProcessed; 212 stream->buffer_cycle = bufferIndex; 213 214 release_spinlock(&stream->lock); 215 216 release_sem_etc(controller->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE); 217 218 return true; 219 } 220 221 222 static int32 223 hda_interrupt_handler(hda_controller* controller) 224 { 225 int32 handled = B_HANDLED_INTERRUPT; 226 227 // Check if this interrupt is ours 228 uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS); 229 if ((intrStatus & INTR_STATUS_GLOBAL) == 0) 230 return B_UNHANDLED_INTERRUPT; 231 232 // Controller or stream related? 233 if (intrStatus & INTR_STATUS_CONTROLLER) { 234 uint8 rirbStatus = controller->Read8(HDAC_RIRB_STATUS); 235 uint8 corbStatus = controller->Read8(HDAC_CORB_STATUS); 236 237 // Check for incoming responses 238 if (rirbStatus) { 239 controller->Write8(HDAC_RIRB_STATUS, rirbStatus); 240 241 if ((rirbStatus & RIRB_STATUS_RESPONSE) != 0) { 242 uint16 writePos = (controller->Read16(HDAC_RIRB_WRITE_POS) + 1) 243 % controller->rirb_length; 244 245 for (; controller->rirb_read_pos != writePos; 246 controller->rirb_read_pos = next_rirb(controller)) { 247 uint32 response = current_rirb(controller).response; 248 uint32 responseFlags = current_rirb(controller).flags; 249 uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK; 250 hda_codec* codec = controller->codecs[cad]; 251 252 if (codec == NULL) { 253 dprintf("hda: Response for unknown codec %ld: " 254 "%08lx/%08lx\n", cad, response, responseFlags); 255 continue; 256 } 257 258 if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) { 259 dprintf("hda: Unsolicited response: %08lx/%08lx\n", 260 response, responseFlags); 261 codec->unsol_responses[codec->unsol_response_write++] = 262 response; 263 codec->unsol_response_write %= MAX_CODEC_UNSOL_RESPONSES; 264 release_sem_etc(codec->unsol_response_sem, 1, 265 B_DO_NOT_RESCHEDULE); 266 handled = B_INVOKE_SCHEDULER; 267 continue; 268 } 269 if (codec->response_count >= MAX_CODEC_RESPONSES) { 270 dprintf("hda: too many responses received for codec %ld" 271 ": %08lx/%08lx!\n", cad, response, responseFlags); 272 continue; 273 } 274 275 // Store response in codec 276 codec->responses[codec->response_count++] = response; 277 release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE); 278 handled = B_INVOKE_SCHEDULER; 279 } 280 } 281 282 if ((rirbStatus & RIRB_STATUS_OVERRUN) != 0) 283 dprintf("hda: RIRB Overflow\n"); 284 } 285 286 // Check for sending errors 287 if (corbStatus) { 288 controller->Write8(HDAC_CORB_STATUS, corbStatus); 289 290 if ((corbStatus & CORB_STATUS_MEMORY_ERROR) != 0) 291 dprintf("hda: CORB Memory Error!\n"); 292 } 293 } 294 295 if ((intrStatus & INTR_STATUS_STREAM_MASK) != 0) { 296 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 297 if ((intrStatus & (1 << index)) != 0) { 298 if (controller->streams[index]) { 299 if (stream_handle_interrupt(controller, 300 controller->streams[index], index)) { 301 handled = B_INVOKE_SCHEDULER; 302 } 303 } else { 304 dprintf("hda: Stream interrupt for unconfigured stream " 305 "%ld!\n", index); 306 } 307 } 308 } 309 } 310 311 // NOTE: See HDA001 => CIS/GIS cannot be cleared! 312 313 return handled; 314 } 315 316 317 static status_t 318 reset_controller(hda_controller* controller) 319 { 320 // stop streams 321 322 for (uint32 i = 0; i < controller->num_input_streams; i++) { 323 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 324 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 325 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 326 + HDAC_INPUT_STREAM_OFFSET(controller, i), 0); 327 } 328 for (uint32 i = 0; i < controller->num_output_streams; i++) { 329 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 330 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 331 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 332 + HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0); 333 } 334 for (uint32 i = 0; i < controller->num_bidir_streams; i++) { 335 controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE 336 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 337 controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE 338 + HDAC_BIDIR_STREAM_OFFSET(controller, i), 0); 339 } 340 341 // stop DMA 342 controller->Write8(HDAC_CORB_CONTROL, 0); 343 controller->Write8(HDAC_RIRB_CONTROL, 0); 344 345 // reset DMA position buffer 346 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0); 347 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0); 348 349 // Set reset bit - it must be asserted for at least 100us 350 351 uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL); 352 controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET); 353 354 for (int timeout = 0; timeout < 10; timeout++) { 355 snooze(100); 356 357 control = controller->Read32(HDAC_GLOBAL_CONTROL); 358 if ((control & GLOBAL_CONTROL_RESET) == 0) 359 break; 360 } 361 if ((control & GLOBAL_CONTROL_RESET) != 0) { 362 dprintf("hda: unable to reset controller\n"); 363 return B_BUSY; 364 } 365 366 // Unset reset bit 367 368 control = controller->Read32(HDAC_GLOBAL_CONTROL); 369 controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET); 370 371 for (int timeout = 0; timeout < 10; timeout++) { 372 snooze(100); 373 374 control = controller->Read32(HDAC_GLOBAL_CONTROL); 375 if ((control & GLOBAL_CONTROL_RESET) != 0) 376 break; 377 } 378 if ((control & GLOBAL_CONTROL_RESET) == 0) { 379 dprintf("hda: unable to exit reset\n"); 380 return B_BUSY; 381 } 382 383 // Wait for codecs to finish their own reset (apparently needs more 384 // time than documented in the specs) 385 snooze(1000); 386 387 // Enable unsolicited responses 388 control = controller->Read32(HDAC_GLOBAL_CONTROL); 389 controller->Write32(HDAC_GLOBAL_CONTROL, 390 control | GLOBAL_CONTROL_UNSOLICITED); 391 392 return B_OK; 393 } 394 395 396 /*! Allocates and initializes the Command Output Ring Buffer (CORB), and 397 Response Input Ring Buffer (RIRB) to the maximum supported size, and also 398 the DMA position buffer. 399 400 Programs the controller hardware to make use of these buffers (the DMA 401 positioning is actually enabled in hda_stream_setup_buffers()). 402 */ 403 static status_t 404 init_corb_rirb_pos(hda_controller* controller) 405 { 406 // Determine and set size of CORB 407 uint8 corbSize = controller->Read8(HDAC_CORB_SIZE); 408 if ((corbSize & CORB_SIZE_CAP_256_ENTRIES) != 0) { 409 controller->corb_length = 256; 410 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_256_ENTRIES); 411 } else if (corbSize & CORB_SIZE_CAP_16_ENTRIES) { 412 controller->corb_length = 16; 413 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_16_ENTRIES); 414 } else if (corbSize & CORB_SIZE_CAP_2_ENTRIES) { 415 controller->corb_length = 2; 416 controller->Write8(HDAC_CORB_SIZE, CORB_SIZE_2_ENTRIES); 417 } 418 419 // Determine and set size of RIRB 420 uint8 rirbSize = controller->Read8(HDAC_RIRB_SIZE); 421 if (rirbSize & RIRB_SIZE_CAP_256_ENTRIES) { 422 controller->rirb_length = 256; 423 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_256_ENTRIES); 424 } else if (rirbSize & RIRB_SIZE_CAP_16_ENTRIES) { 425 controller->rirb_length = 16; 426 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_16_ENTRIES); 427 } else if (rirbSize & RIRB_SIZE_CAP_2_ENTRIES) { 428 controller->rirb_length = 2; 429 controller->Write8(HDAC_RIRB_SIZE, RIRB_SIZE_2_ENTRIES); 430 } 431 432 // Determine rirb offset in memory and total size of corb+alignment+rirb 433 uint32 rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128); 434 uint32 posOffset = ALIGN(rirbOffset 435 + controller->rirb_length * sizeof(rirb_t), 128); 436 uint8 posSize = 8 * (controller->num_input_streams 437 + controller->num_output_streams + controller->num_bidir_streams); 438 439 uint32 memSize = PAGE_ALIGN(posOffset + posSize); 440 441 // Allocate memory area 442 controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos", 443 (void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize, 444 B_CONTIGUOUS, 0); 445 if (controller->corb_rirb_pos_area < 0) 446 return controller->corb_rirb_pos_area; 447 448 // Rirb is after corb+aligment 449 controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset); 450 451 physical_entry pe; 452 status_t status = get_memory_map(controller->corb, memSize, &pe, 1); 453 if (status != B_OK) { 454 delete_area(controller->corb_rirb_pos_area); 455 return status; 456 } 457 458 // Program CORB/RIRB for these locations 459 controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address); 460 controller->Write32(HDAC_CORB_BASE_UPPER, 461 (uint32)((uint64)pe.address >> 32)); 462 controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset); 463 controller->Write32(HDAC_RIRB_BASE_UPPER, 464 (uint32)(((uint64)pe.address + rirbOffset) >> 32)); 465 466 // Program DMA position update 467 controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 468 (uint32)pe.address + posOffset); 469 controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 470 (uint32)(((uint64)pe.address + posOffset) >> 32)); 471 472 controller->stream_positions = (uint32*) 473 ((uint8*)controller->corb + posOffset); 474 475 controller->Write16(HDAC_CORB_WRITE_POS, 0); 476 // Reset CORB read pointer 477 controller->Write16(HDAC_CORB_READ_POS, CORB_READ_POS_RESET); 478 // Reading CORB_READ_POS_RESET as zero fails on some chips. 479 // We reset the bit here. 480 controller->Write16(HDAC_CORB_READ_POS, 0); 481 482 // Reset RIRB write pointer 483 controller->Write16(HDAC_RIRB_WRITE_POS, RIRB_WRITE_POS_RESET); 484 485 // Generate interrupt for every response 486 controller->Write16(HDAC_RESPONSE_INTR_COUNT, 1); 487 488 // Setup cached read/write indices 489 controller->rirb_read_pos = 1; 490 controller->corb_write_pos = 0; 491 492 // Gentlemen, start your engines... 493 controller->Write8(HDAC_CORB_CONTROL, 494 CORB_CONTROL_RUN | CORB_CONTROL_MEMORY_ERROR_INTR); 495 controller->Write8(HDAC_RIRB_CONTROL, RIRB_CONTROL_DMA_ENABLE 496 | RIRB_CONTROL_OVERRUN_INTR | RIRB_CONTROL_RESPONSE_INTR); 497 498 return B_OK; 499 } 500 501 502 // #pragma mark - public stream functions 503 504 505 void 506 hda_stream_delete(hda_stream* stream) 507 { 508 if (stream->buffer_area >= 0) 509 delete_area(stream->buffer_area); 510 511 if (stream->buffer_descriptors_area >= 0) 512 delete_area(stream->buffer_descriptors_area); 513 514 free(stream); 515 } 516 517 518 hda_stream* 519 hda_stream_new(hda_audio_group* audioGroup, int type) 520 { 521 hda_controller* controller = audioGroup->codec->controller; 522 523 hda_stream* stream = (hda_stream*)calloc(1, sizeof(hda_stream)); 524 if (stream == NULL) 525 return NULL; 526 527 stream->buffer_area = B_ERROR; 528 stream->buffer_descriptors_area = B_ERROR; 529 stream->type = type; 530 stream->controller = controller; 531 stream->incorrect_position_count = 0; 532 stream->use_dma_position = true; 533 534 switch (type) { 535 case STREAM_PLAYBACK: 536 stream->id = 1; 537 stream->offset = HDAC_OUTPUT_STREAM_OFFSET(controller, 0); 538 break; 539 540 case STREAM_RECORD: 541 stream->id = 2; 542 stream->offset = HDAC_INPUT_STREAM_OFFSET(controller, 0); 543 break; 544 545 default: 546 dprintf("%s: Unknown stream type %d!\n", __func__, type); 547 free(stream); 548 return NULL; 549 } 550 551 // find I/O and Pin widgets for this stream 552 553 if (hda_audio_group_get_widgets(audioGroup, stream) == B_OK) { 554 switch (type) { 555 case STREAM_PLAYBACK: 556 controller->streams[controller->num_input_streams] = stream; 557 break; 558 case STREAM_RECORD: 559 controller->streams[0] = stream; 560 break; 561 } 562 563 return stream; 564 } 565 566 dprintf("hda: hda_audio_group_get_widgets failed for %s stream\n", 567 type == STREAM_PLAYBACK ? " playback" : "record"); 568 569 free(stream); 570 return NULL; 571 } 572 573 574 /*! Starts a stream's DMA engine, and enables generating and receiving 575 interrupts for this stream. 576 */ 577 status_t 578 hda_stream_start(hda_controller* controller, hda_stream* stream) 579 { 580 dprintf("hda_stream_start() offset %lx\n", stream->offset); 581 582 stream->frames_count = 0; 583 stream->last_link_frame_position = 0; 584 585 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 586 | (1 << (stream->offset / HDAC_STREAM_SIZE))); 587 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 588 | CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 589 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN); 590 591 stream->running = true; 592 return B_OK; 593 } 594 595 596 /*! Stops the stream's DMA engine, and turns off interrupts for this 597 stream. 598 */ 599 status_t 600 hda_stream_stop(hda_controller* controller, hda_stream* stream) 601 { 602 dprintf("hda_stream_stop()\n"); 603 stream->Write8(HDAC_STREAM_CONTROL0, stream->Read8(HDAC_STREAM_CONTROL0) 604 & ~(CONTROL0_BUFFER_COMPLETED_INTR | CONTROL0_FIFO_ERROR_INTR 605 | CONTROL0_DESCRIPTOR_ERROR_INTR | CONTROL0_RUN)); 606 controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL) 607 & ~(1 << (stream->offset / HDAC_STREAM_SIZE))); 608 609 stream->running = false; 610 611 return B_OK; 612 } 613 614 615 status_t 616 hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream, 617 const char* desc) 618 { 619 // Clear previously allocated memory 620 if (stream->buffer_area >= 0) { 621 delete_area(stream->buffer_area); 622 stream->buffer_area = B_ERROR; 623 } 624 625 if (stream->buffer_descriptors_area >= 0) { 626 delete_area(stream->buffer_descriptors_area); 627 stream->buffer_descriptors_area = B_ERROR; 628 } 629 630 // Find out stream format and sample rate 631 uint16 format = (stream->num_channels - 1) & 0xf; 632 switch (stream->sample_format) { 633 case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break; 634 case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break; 635 case B_FMT_20BIT: format |= FORMAT_20BIT; stream->bps = 20; break; 636 case B_FMT_24BIT: format |= FORMAT_24BIT; stream->bps = 24; break; 637 case B_FMT_32BIT: format |= FORMAT_32BIT; stream->bps = 32; break; 638 639 default: 640 dprintf("hda: Invalid sample format: 0x%lx\n", 641 stream->sample_format); 642 break; 643 } 644 645 for (uint32 index = 0; index < sizeof(kRates) / sizeof(kRates[0]); index++) { 646 if (kRates[index].multi_rate == stream->sample_rate) { 647 format |= kRates[index].hw_rate; 648 stream->rate = kRates[index].rate; 649 break; 650 } 651 } 652 653 // Calculate size of buffer (aligned to 128 bytes) 654 stream->buffer_size = ALIGN(stream->buffer_length * stream->num_channels 655 * stream->sample_size, 128); 656 657 dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld\n", 658 stream->sample_size, stream->num_channels, stream->buffer_length); 659 dprintf("IRA: %s: setup stream %ld: SR=%ld, SF=%ld F=0x%x (0x%lx)\n", 660 __func__, stream->id, stream->rate, stream->bps, format, 661 stream->sample_format); 662 663 // Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) 664 uint32 alloc = stream->buffer_size * stream->num_buffers; 665 alloc = PAGE_ALIGN(alloc); 666 667 // Allocate memory for buffers 668 uint8* buffer; 669 stream->buffer_area = create_area("hda buffers", (void**)&buffer, 670 B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA); 671 if (stream->buffer_area < B_OK) 672 return stream->buffer_area; 673 674 // Get the physical address of memory 675 physical_entry pe; 676 status_t status = get_memory_map(buffer, alloc, &pe, 1); 677 if (status != B_OK) { 678 delete_area(stream->buffer_area); 679 return status; 680 } 681 682 phys_addr_t bufferPhysicalAddress = pe.address; 683 684 dprintf("%s(%s): Allocated %lu bytes for %ld buffers\n", __func__, desc, 685 alloc, stream->num_buffers); 686 687 // Store pointers (both virtual/physical) 688 for (uint32 index = 0; index < stream->num_buffers; index++) { 689 stream->buffers[index] = buffer + (index * stream->buffer_size); 690 stream->physical_buffers[index] = bufferPhysicalAddress 691 + (index * stream->buffer_size); 692 } 693 694 // Now allocate BDL for buffer range 695 uint32 bdlCount = stream->num_buffers; 696 alloc = bdlCount * sizeof(bdl_entry_t); 697 alloc = PAGE_ALIGN(alloc); 698 699 bdl_entry_t* bufferDescriptors; 700 stream->buffer_descriptors_area = create_area("hda buffer descriptors", 701 (void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc, 702 B_CONTIGUOUS, 0); 703 if (stream->buffer_descriptors_area < B_OK) { 704 delete_area(stream->buffer_area); 705 return stream->buffer_descriptors_area; 706 } 707 708 // Get the physical address of memory 709 status = get_memory_map(bufferDescriptors, alloc, &pe, 1); 710 if (status != B_OK) { 711 delete_area(stream->buffer_area); 712 delete_area(stream->buffer_descriptors_area); 713 return status; 714 } 715 716 stream->physical_buffer_descriptors = pe.address; 717 718 dprintf("%s(%s): Allocated %ld bytes for %ld BDLEs\n", __func__, desc, 719 alloc, bdlCount); 720 721 // Setup buffer descriptor list (BDL) entries 722 uint32 fragments = 0; 723 for (uint32 index = 0; index < stream->num_buffers; 724 index++, bufferDescriptors++) { 725 bufferDescriptors->lower = (uint32)stream->physical_buffers[index]; 726 bufferDescriptors->upper 727 = (uint32)((uint64)stream->physical_buffers[index] >> 32); 728 fragments++; 729 bufferDescriptors->length = stream->buffer_size; 730 bufferDescriptors->ioc = 1; 731 // we want an interrupt after every buffer 732 } 733 734 // Configure stream registers 735 stream->Write16(HDAC_STREAM_FORMAT, format); 736 stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER, 737 (uint32)stream->physical_buffer_descriptors); 738 stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 739 (uint32)(stream->physical_buffer_descriptors >> 32)); 740 stream->Write16(HDAC_STREAM_LAST_VALID, fragments - 1); 741 // total cyclic buffer size in _bytes_ 742 stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size 743 * stream->num_buffers); 744 stream->Write8(HDAC_STREAM_CONTROL2, stream->id << CONTROL2_STREAM_SHIFT); 745 746 stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 747 stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER) 748 | DMA_POSITION_ENABLED); 749 750 dprintf("hda: stream: %ld fifo size: %d num_io_widgets: %ld\n", stream->id, 751 stream->Read16(HDAC_STREAM_FIFO_SIZE), stream->num_io_widgets); 752 dprintf("hda: widgets: "); 753 754 hda_codec* codec = audioGroup->codec; 755 uint32 channelNum = 0; 756 for (uint32 i = 0; i < stream->num_io_widgets; i++) { 757 corb_t verb[2]; 758 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 759 VID_SET_CONVERTER_FORMAT, format); 760 uint32 val = stream->id << 4; 761 if (channelNum < stream->num_channels) 762 val |= channelNum; 763 else 764 val = 0; 765 verb[1] = MAKE_VERB(codec->addr, stream->io_widgets[i], 766 VID_SET_CONVERTER_STREAM_CHANNEL, val); 767 768 uint32 response[2]; 769 hda_send_verbs(codec, verb, response, 2); 770 //channelNum += 2; // TODO stereo widget ? Every output gets the same stream for now 771 dprintf("%ld ", stream->io_widgets[i]); 772 773 hda_widget* widget = hda_audio_group_get_widget(audioGroup, 774 stream->io_widgets[i]); 775 if ((widget->capabilities.audio & AUDIO_CAP_DIGITAL) != 0) { 776 verb[0] = MAKE_VERB(codec->addr, stream->io_widgets[i], 777 VID_SET_DIGITAL_CONVERTER_CONTROL1, format); 778 hda_send_verbs(codec, verb, response, 1); 779 } 780 } 781 dprintf("\n"); 782 783 snooze(1000); 784 return B_OK; 785 } 786 787 788 // #pragma mark - public controller functions 789 790 791 status_t 792 hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count) 793 { 794 hda_controller* controller = codec->controller; 795 uint32 sent = 0; 796 797 codec->response_count = 0; 798 799 while (sent < count) { 800 uint32 readPos = controller->Read16(HDAC_CORB_READ_POS); 801 uint32 queued = 0; 802 803 while (sent < count) { 804 uint32 writePos = next_corb(controller); 805 806 if (writePos == readPos) { 807 // There is no space left in the ring buffer; execute the 808 // queued commands and wait until 809 break; 810 } 811 812 controller->corb[writePos] = verbs[sent++]; 813 controller->corb_write_pos = writePos; 814 queued++; 815 } 816 817 controller->Write16(HDAC_CORB_WRITE_POS, controller->corb_write_pos); 818 status_t status = acquire_sem_etc(codec->response_sem, queued, 819 B_RELATIVE_TIMEOUT, 50000ULL); 820 if (status != B_OK) 821 return status; 822 } 823 824 if (responses != NULL) 825 memcpy(responses, codec->responses, count * sizeof(uint32)); 826 827 return B_OK; 828 } 829 830 831 status_t 832 hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload) 833 { 834 corb_t verb = MAKE_VERB(codec->addr, nid, vid, payload); 835 return hda_send_verbs(codec, &verb, NULL, 1); 836 } 837 838 839 status_t 840 hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32* response) 841 { 842 corb_t verb = MAKE_VERB(codec->addr, nid, vid, 0); 843 return hda_send_verbs(codec, &verb, response, 1); 844 } 845 846 847 /*! Setup hardware for use; detect codecs; etc */ 848 status_t 849 hda_hw_init(hda_controller* controller) 850 { 851 uint16 capabilities; 852 uint16 stateStatus; 853 uint16 cmd; 854 status_t status; 855 uint32 quirks = get_controller_quirks(controller->pci_info); 856 857 // Map MMIO registers 858 controller->regs_area = map_physical_memory("hda_hw_regs", 859 controller->pci_info.u.h0.base_registers[0], 860 controller->pci_info.u.h0.base_register_sizes[0], B_ANY_KERNEL_ADDRESS, 861 0, (void**)&controller->regs); 862 if (controller->regs_area < B_OK) { 863 status = controller->regs_area; 864 goto error; 865 } 866 867 cmd = (gPci->read_pci_config)(controller->pci_info.bus, 868 controller->pci_info.device, controller->pci_info.function, 869 PCI_command, 2); 870 if (!(cmd & PCI_command_master)) { 871 dprintf("hda: enabling PCI bus mastering\n"); 872 cmd |= PCI_command_master; 873 } 874 if (!(cmd & PCI_command_memory)) { 875 dprintf("hda: enabling PCI memory access\n"); 876 cmd |= PCI_command_memory; 877 } 878 if ((cmd & PCI_command_int_disable)) { 879 dprintf("hda: enabling PCI interrupts\n"); 880 cmd &= ~PCI_command_int_disable; 881 } 882 (gPci->write_pci_config)(controller->pci_info.bus, 883 controller->pci_info.device, controller->pci_info.function, 884 PCI_command, 2, cmd); 885 886 // Absolute minimum hw is online; we can now install interrupt handler 887 888 controller->irq = controller->pci_info.u.h0.interrupt_line; 889 controller->msi = false; 890 891 if (gPCIx86Module != NULL && (quirks & HDA_QUIRK_NO_MSI) == 0 892 && gPCIx86Module->get_msi_count( 893 controller->pci_info.bus, controller->pci_info.device, 894 controller->pci_info.function) >= 1) { 895 // Try MSI first 896 uint8 vector; 897 if (gPCIx86Module->configure_msi(controller->pci_info.bus, 898 controller->pci_info.device, controller->pci_info.function, 899 1, &vector) == B_OK 900 && gPCIx86Module->enable_msi(controller->pci_info.bus, 901 controller->pci_info.device, controller->pci_info.function) 902 == B_OK) { 903 dprintf("hda: using MSI vector %u\n", vector); 904 controller->irq = vector; 905 controller->msi = true; 906 } 907 } 908 909 status = install_io_interrupt_handler(controller->irq, 910 (interrupt_handler)hda_interrupt_handler, controller, 0); 911 if (status != B_OK) 912 goto no_irq; 913 914 // TCSEL is reset to TC0 (clear 0-2 bits) 915 update_pci_register(controller, PCI_HDA_TCSEL, PCI_HDA_TCSEL_MASK, 0, 1); 916 917 if ((quirks & HDA_QUIRK_SNOOP) != 0) { 918 switch (controller->pci_info.vendor_id) { 919 case PCI_VENDOR_NVIDIA: 920 update_pci_register(controller, NVIDIA_HDA_TRANSREG, 921 NVIDIA_HDA_TRANSREG_MASK, NVIDIA_HDA_ENABLE_COHBITS, 1); 922 update_pci_register(controller, NVIDIA_HDA_ISTRM_COH, 923 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 924 update_pci_register(controller, NVIDIA_HDA_OSTRM_COH, 925 ~NVIDIA_HDA_ENABLE_COHBIT, NVIDIA_HDA_ENABLE_COHBIT, 1); 926 break; 927 case PCI_VENDOR_AMD: 928 update_pci_register(controller, ATI_HDA_MISC_CNTR2, 929 ATI_HDA_MISC_CNTR2_MASK, ATI_HDA_ENABLE_SNOOP, 1); 930 break; 931 case PCI_VENDOR_INTEL: 932 update_pci_register(controller, INTEL_SCH_HDA_DEVC, 933 ~INTEL_SCH_HDA_DEVC_SNOOP, 0, 2); 934 break; 935 } 936 } 937 938 capabilities = controller->Read16(HDAC_GLOBAL_CAP); 939 controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities); 940 controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities); 941 controller->num_bidir_streams = GLOBAL_CAP_BIDIR_STREAMS(capabilities); 942 943 // show some hw features 944 dprintf("hda: HDA v%d.%d, O:%ld/I:%ld/B:%ld, #SDO:%d, 64bit:%s\n", 945 controller->Read8(HDAC_VERSION_MAJOR), 946 controller->Read8(HDAC_VERSION_MINOR), 947 controller->num_output_streams, controller->num_input_streams, 948 controller->num_bidir_streams, 949 GLOBAL_CAP_NUM_SDO(capabilities), 950 GLOBAL_CAP_64BIT(capabilities) ? "yes" : "no"); 951 952 // Get controller into valid state 953 status = reset_controller(controller); 954 if (status != B_OK) { 955 dprintf("hda: reset_controller failed\n"); 956 goto reset_failed; 957 } 958 959 // Setup CORB/RIRB/DMA POS 960 status = init_corb_rirb_pos(controller); 961 if (status != B_OK) { 962 dprintf("hda: init_corb_rirb_pos failed\n"); 963 goto corb_rirb_failed; 964 } 965 966 // Don't enable codec state change interrupts. We don't handle 967 // them, as we want to use the STATE_STATUS register to identify 968 // available codecs. We'd have to clear that register in the interrupt 969 // handler to 'ack' the codec change. 970 controller->Write16(HDAC_WAKE_ENABLE, 0x0); 971 972 // Enable controller interrupts 973 controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE 974 | INTR_CONTROL_CONTROLLER_ENABLE); 975 976 snooze(1000); 977 978 stateStatus = controller->Read16(HDAC_STATE_STATUS); 979 if (!stateStatus) { 980 dprintf("hda: bad codec status\n"); 981 status = ENODEV; 982 goto corb_rirb_failed; 983 } 984 controller->Write16(HDAC_STATE_STATUS, stateStatus); 985 986 // Create codecs 987 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 988 if ((stateStatus & (1 << index)) != 0) 989 hda_codec_new(controller, index); 990 } 991 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 992 if (controller->codecs[index] 993 && controller->codecs[index]->num_audio_groups > 0) { 994 controller->active_codec = controller->codecs[index]; 995 break; 996 } 997 } 998 999 controller->buffer_ready_sem = create_sem(0, "hda_buffer_sem"); 1000 if (controller->buffer_ready_sem < B_OK) { 1001 dprintf("hda: failed to create semaphore\n"); 1002 status = ENODEV; 1003 goto corb_rirb_failed; 1004 } 1005 1006 if (controller->active_codec != NULL) 1007 return B_OK; 1008 1009 dprintf("hda: no active codec\n"); 1010 status = ENODEV; 1011 1012 delete_sem(controller->buffer_ready_sem); 1013 1014 corb_rirb_failed: 1015 controller->Write32(HDAC_INTR_CONTROL, 0); 1016 1017 reset_failed: 1018 if (controller->msi) { 1019 gPCIx86Module->disable_msi(controller->pci_info.bus, 1020 controller->pci_info.device, controller->pci_info.function); 1021 } 1022 1023 remove_io_interrupt_handler(controller->irq, 1024 (interrupt_handler)hda_interrupt_handler, controller); 1025 1026 no_irq: 1027 delete_area(controller->regs_area); 1028 controller->regs_area = B_ERROR; 1029 controller->regs = NULL; 1030 1031 error: 1032 dprintf("hda: ERROR: %s(%ld)\n", strerror(status), status); 1033 1034 return status; 1035 } 1036 1037 1038 /*! Stop any activity */ 1039 void 1040 hda_hw_stop(hda_controller* controller) 1041 { 1042 // Stop all audio streams 1043 for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) { 1044 if (controller->streams[index] && controller->streams[index]->running) 1045 hda_stream_stop(controller, controller->streams[index]); 1046 } 1047 } 1048 1049 1050 /*! Free resources */ 1051 void 1052 hda_hw_uninit(hda_controller* controller) 1053 { 1054 if (controller == NULL) 1055 return; 1056 1057 // Stop all audio streams 1058 hda_hw_stop(controller); 1059 1060 if (controller->buffer_ready_sem >= B_OK) { 1061 delete_sem(controller->buffer_ready_sem); 1062 controller->buffer_ready_sem = B_ERROR; 1063 } 1064 1065 reset_controller(controller); 1066 1067 // Disable interrupts, and remove interrupt handler 1068 controller->Write32(HDAC_INTR_CONTROL, 0); 1069 1070 if (controller->msi) { 1071 // Disable MSI 1072 gPCIx86Module->disable_msi(controller->pci_info.bus, 1073 controller->pci_info.device, controller->pci_info.function); 1074 } 1075 1076 remove_io_interrupt_handler(controller->irq, 1077 (interrupt_handler)hda_interrupt_handler, controller); 1078 1079 if (gPCIx86Module != NULL) { 1080 put_module(B_PCI_X86_MODULE_NAME); 1081 gPCIx86Module = NULL; 1082 } 1083 1084 // Delete corb/rirb area 1085 if (controller->corb_rirb_pos_area >= 0) { 1086 delete_area(controller->corb_rirb_pos_area); 1087 controller->corb_rirb_pos_area = B_ERROR; 1088 controller->corb = NULL; 1089 controller->rirb = NULL; 1090 controller->stream_positions = NULL; 1091 } 1092 1093 // Unmap registers 1094 if (controller->regs_area >= 0) { 1095 delete_area(controller->regs_area); 1096 controller->regs_area = B_ERROR; 1097 controller->regs = NULL; 1098 } 1099 1100 // Now delete all codecs 1101 for (uint32 index = 0; index < HDA_MAX_CODECS; index++) { 1102 if (controller->codecs[index] != NULL) 1103 hda_codec_delete(controller->codecs[index]); 1104 } 1105 controller->active_codec = NULL; 1106 } 1107