1 /* CTRC functionality */
2 /* Author:
3 Rudolf Cornelissen 11/2002-9/2004
4 */
5
6 #define MODULE_BIT 0x00040000
7
8 #include "std.h"
9
10 /*Adjust passed parameters to a valid mode line*/
eng_crtc_validate_timing(uint16 * hd_e,uint16 * hs_s,uint16 * hs_e,uint16 * ht,uint16 * vd_e,uint16 * vs_s,uint16 * vs_e,uint16 * vt)11 status_t eng_crtc_validate_timing(
12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
14 )
15 {
16 /* horizontal */
17 /* make all parameters multiples of 8 */
18 *hd_e &= 0xfff8;
19 *hs_s &= 0xfff8;
20 *hs_e &= 0xfff8;
21 *ht &= 0xfff8;
22
23 /* confine to required number of bits, taking logic into account */
24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3);
25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3);
26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3);
27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3);
28
29 /* NOTE: keep horizontal timing at multiples of 8! */
30 /* confine to a reasonable width */
31 if (*hd_e < 640) *hd_e = 640;
32 if (si->ps.card_type > NV04)
33 {
34 if (*hd_e > 2048) *hd_e = 2048;
35 }
36 else
37 {
38 if (*hd_e > 1920) *hd_e = 1920;
39 }
40
41 /* if hor. total does not leave room for a sensible sync pulse, increase it! */
42 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
43
44 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */
45 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8);
46
47 /* make sure sync pulse is not during display */
48 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8);
49 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8);
50
51 /* correct sync pulse if it is too long:
52 * there are only 5 bits available to save this in the card registers! */
53 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8);
54
55 /*vertical*/
56 /* confine to required number of bits, taking logic into account */
57 //fixme if needed: on GeForce cards there are 12 instead of 11 bits...
58 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2);
59 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1);
60 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ;
61 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2);
62
63 /* confine to a reasonable height */
64 if (*vd_e < 480) *vd_e = 480;
65 if (si->ps.card_type > NV04)
66 {
67 if (*vd_e > 1536) *vd_e = 1536;
68 }
69 else
70 {
71 if (*vd_e > 1440) *vd_e = 1440;
72 }
73
74 /*if vertical total does not leave room for a sync pulse, increase it!*/
75 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
76
77 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */
78 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff);
79
80 /* make sure sync pulse is not during display */
81 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1);
82 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1);
83
84 /* correct sync pulse if it is too long:
85 * there are only 4 bits available to save this in the card registers! */
86 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f);
87
88 return B_OK;
89 }
90
91 /*set a mode line - inputs are in pixels*/
eng_crtc_set_timing(display_mode target)92 status_t eng_crtc_set_timing(display_mode target)
93 {
94 uint8 temp;
95
96 uint32 htotal; /*total horizontal total VCLKs*/
97 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/
98 uint32 hsync_s; /*begin of horizontal sync pulse*/
99 uint32 hsync_e; /*end of horizontal sync pulse*/
100 uint32 hblnk_s; /*begin horizontal blanking*/
101 uint32 hblnk_e; /*end horizontal blanking*/
102
103 uint32 vtotal; /*total vertical total scanlines*/
104 uint32 vdisp_e; /*end of vertical display*/
105 uint32 vsync_s; /*begin of vertical sync pulse*/
106 uint32 vsync_e; /*end of vertical sync pulse*/
107 uint32 vblnk_s; /*begin vertical blanking*/
108 uint32 vblnk_e; /*end vertical blanking*/
109
110 uint32 linecomp; /*split screen and vdisp_e interrupt*/
111
112 LOG(4,("CRTC: setting timing\n"));
113
114 /* setup tuned internal modeline for flatpanel if connected and active */
115 /* notes:
116 * - the CRTC modeline must end earlier than the panel modeline to keep correct
117 * sync going;
118 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel
119 * wide horizontal stripes. This can be observed earliest on fullscreen overlay,
120 * and if it gets worse, also normal desktop output will suffer. The stripes
121 * are mainly visible at the left of the screen, over the entire screen height. */
122 if (si->ps.tmds1_active)
123 {
124 LOG(2,("CRTC: DFP active: tuning modeline\n"));
125
126 /* horizontal timing */
127 target.timing.h_sync_start =
128 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) *
129 target.timing.h_display)) & 0xfff8;
130
131 target.timing.h_sync_end =
132 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) *
133 target.timing.h_display)) & 0xfff8;
134
135 target.timing.h_total =
136 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) *
137 target.timing.h_display)) & 0xfff8) - 8;
138
139 /* in native mode the CRTC needs some extra time to keep synced correctly;
140 * OTOH the overlay unit distorts if we reserve too much time! */
141 if (target.timing.h_display == si->ps.p1_timing.h_display)
142 {
143 /* NV11 timing has different constraints than later cards */
144 if (si->ps.card_type == NV11)
145 target.timing.h_total -= 56;
146 else
147 /* confirmed NV34 with 1680x1050 panel */
148 target.timing.h_total -= 32;
149 }
150
151 if (target.timing.h_sync_start == target.timing.h_display)
152 target.timing.h_sync_start += 8;
153 if (target.timing.h_sync_end == target.timing.h_total)
154 target.timing.h_sync_end -= 8;
155
156 /* vertical timing */
157 target.timing.v_sync_start =
158 ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) *
159 target.timing.v_display));
160
161 target.timing.v_sync_end =
162 ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) *
163 target.timing.v_display));
164
165 target.timing.v_total =
166 ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) *
167 target.timing.v_display)) - 1;
168
169 if (target.timing.v_sync_start == target.timing.v_display)
170 target.timing.v_sync_start += 1;
171 if (target.timing.v_sync_end == target.timing.v_total)
172 target.timing.v_sync_end -= 1;
173
174 /* disable GPU scaling testmode so automatic scaling will be done */
175 DACW(FP_DEBUG1, 0);
176 }
177
178 /* Modify parameters as required by standard VGA */
179 htotal = ((target.timing.h_total >> 3) - 5);
180 hdisp_e = ((target.timing.h_display >> 3) - 1);
181 hblnk_s = hdisp_e;
182 hblnk_e = (htotal + 4);//0;
183 hsync_s = (target.timing.h_sync_start >> 3);
184 hsync_e = (target.timing.h_sync_end >> 3);
185
186 vtotal = target.timing.v_total - 2;
187 vdisp_e = target.timing.v_display - 1;
188 vblnk_s = vdisp_e;
189 vblnk_e = (vtotal + 1);
190 vsync_s = target.timing.v_sync_start;//-1;
191 vsync_e = target.timing.v_sync_end;//-1;
192
193 /* prevent memory adress counter from being reset (linecomp may not occur) */
194 linecomp = target.timing.v_display;
195
196 /* enable access to primary head */
197 set_crtc_owner(0);
198
199 /* Note for laptop and DVI flatpanels:
200 * CRTC timing has a seperate set of registers from flatpanel timing.
201 * The flatpanel timing registers have scaling registers that are used to match
202 * these two modelines. */
203 {
204 LOG(4,("CRTC: Setting full timing...\n"));
205
206 /* log the mode that will be set */
207 LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
208 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e));
209
210 /* actually program the card! */
211 /* unlock CRTC registers at index 0-7 */
212 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f));
213 /* horizontal standard VGA regs */
214 CRTCW(HTOTAL, (htotal & 0xff));
215 CRTCW(HDISPE, (hdisp_e & 0xff));
216 CRTCW(HBLANKS, (hblnk_s & 0xff));
217 /* also unlock vertical retrace registers in advance */
218 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80));
219 CRTCW(HSYNCS, (hsync_s & 0xff));
220 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));
221
222 /* vertical standard VGA regs */
223 CRTCW(VTOTAL, (vtotal & 0xff));
224 CRTCW(OVERFLOW,
225 (
226 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) |
227 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) |
228 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) |
229 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))
230 ));
231 CRTCW(PRROWSCN, 0x00); /* not used */
232 CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));
233 CRTCW(VSYNCS, (vsync_s & 0xff));
234 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f)));
235 CRTCW(VDISPE, (vdisp_e & 0xff));
236 CRTCW(VBLANKS, (vblnk_s & 0xff));
237 CRTCW(VBLANKE, (vblnk_e & 0xff));
238 CRTCW(LINECOMP, (linecomp & 0xff));
239
240 /* horizontal extended regs */
241 //fixme: we reset bit4. is this correct??
242 CRTCW(HEB, (CRTCR(HEB) & 0xe0) |
243 (
244 ((htotal & 0x100) >> (8 - 0)) |
245 ((hdisp_e & 0x100) >> (8 - 1)) |
246 ((hblnk_s & 0x100) >> (8 - 2)) |
247 ((hsync_s & 0x100) >> (8 - 3))
248 ));
249
250 /* (mostly) vertical extended regs */
251 CRTCW(LSR,
252 (
253 ((vtotal & 0x400) >> (10 - 0)) |
254 ((vdisp_e & 0x400) >> (10 - 1)) |
255 ((vsync_s & 0x400) >> (10 - 2)) |
256 ((vblnk_s & 0x400) >> (10 - 3)) |
257 ((hblnk_e & 0x040) >> (6 - 4))
258 //fixme: we still miss one linecomp bit!?! is this it??
259 //| ((linecomp & 0x400) >> 3)
260 ));
261
262 /* more vertical extended regs (on GeForce cards only) */
263 if (si->ps.card_arch >= NV10A)
264 {
265 CRTCW(EXTRA,
266 (
267 ((vtotal & 0x800) >> (11 - 0)) |
268 ((vdisp_e & 0x800) >> (11 - 2)) |
269 ((vsync_s & 0x800) >> (11 - 4)) |
270 ((vblnk_s & 0x800) >> (11 - 6))
271 //fixme: do we miss another linecomp bit!?!
272 ));
273 }
274
275 /* setup 'large screen' mode */
276 if (target.timing.h_display >= 1280)
277 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb));
278 else
279 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04));
280
281 /* setup HSYNC & VSYNC polarity */
282 LOG(2,("CRTC: sync polarity: "));
283 temp = ENG_REG8(RG8_MISCR);
284 if (target.timing.flags & B_POSITIVE_HSYNC)
285 {
286 LOG(2,("H:pos "));
287 temp &= ~0x40;
288 }
289 else
290 {
291 LOG(2,("H:neg "));
292 temp |= 0x40;
293 }
294 if (target.timing.flags & B_POSITIVE_VSYNC)
295 {
296 LOG(2,("V:pos "));
297 temp &= ~0x80;
298 }
299 else
300 {
301 LOG(2,("V:neg "));
302 temp |= 0x80;
303 }
304 ENG_REG8(RG8_MISCW) = temp;
305
306 LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR)));
307 }
308
309 /* always disable interlaced operation */
310 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
311 CRTCW(INTERLACE, 0xff);
312
313 /* disable CRTC slaved mode unless a panel is in use */
314 // fixme: this kills TVout when it was in use...
315 if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f));
316
317 /* setup flatpanel if connected and active */
318 if (si->ps.tmds1_active)
319 {
320 uint32 iscale_x, iscale_y;
321
322 /* calculate inverse scaling factors used by hardware in 20.12 format */
323 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display);
324 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display);
325
326 /* unblock flatpanel timing programming (or something like that..) */
327 CRTCW(FP_HTIMING, 0);
328 CRTCW(FP_VTIMING, 0);
329 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING)));
330 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING)));
331
332 /* enable full width visibility on flatpanel */
333 DACW(FP_HVALID_S, 0);
334 DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1));
335 /* enable full height visibility on flatpanel */
336 DACW(FP_VVALID_S, 0);
337 DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1));
338
339 /* nVidia cards support upscaling except on ??? */
340 /* NV11 cards can upscale after all! */
341 if (0)//si->ps.card_type == NV11)
342 {
343 /* disable last fetched line limiting */
344 DACW(FP_DEBUG2, 0x00000000);
345 /* inform panel to scale if needed */
346 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12)))
347 {
348 LOG(2,("CRTC: DFP needs to do scaling\n"));
349 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100));
350 }
351 else
352 {
353 LOG(2,("CRTC: no scaling for DFP needed\n"));
354 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff));
355 }
356 }
357 else
358 {
359 float dm_aspect;
360
361 LOG(2,("CRTC: GPU scales for DFP if needed\n"));
362
363 /* calculate display mode aspect */
364 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display));
365
366 /* limit last fetched line if vertical scaling is done */
367 if (iscale_y != (1 << 12))
368 DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
369 else
370 DACW(FP_DEBUG2, 0x00000000);
371
372 /* inform panel not to scale */
373 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff));
374
375 /* GPU scaling is automatically setup by hardware, so only modify this
376 * scalingfactor for non 4:3 (1.33) aspect panels;
377 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */
378
379 /* correct for widescreen panels relative to mode...
380 * (so if panel is more widescreen than mode being set) */
381 /* BTW: known widescreen panels:
382 * 1280 x 800 (1.60),
383 * 1440 x 900 (1.60),
384 * 1680 x 1050 (1.60),
385 * 1920 x 1200 (1.60). */
386 /* known 4:3 aspect non-standard resolution panels:
387 * 1400 x 1050 (1.33). */
388 /* NOTE:
389 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */
390 if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10)))
391 {
392 uint16 diff;
393
394 LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n"));
395
396 /* X-scaling should be the same as Y-scaling */
397 iscale_x = iscale_y;
398 /* enable testmode (b12) and program modified X-scaling factor */
399 DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12)));
400 /* center/cut-off left and right side of screen */
401 diff = ((si->ps.p1_timing.h_display -
402 (target.timing.h_display * ((1 << 12) / ((float)iscale_x))))
403 / 2);
404 DACW(FP_HVALID_S, diff);
405 DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1));
406 }
407 /* correct for portrait panels... */
408 /* NOTE:
409 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */
410 if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10)))
411 {
412 LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n"));
413 /* fixme: implement if this kind of portrait panels exist on nVidia... */
414 }
415 }
416
417 /* do some logging.. */
418 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S)));
419 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E)));
420 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S)));
421 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E)));
422 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0)));
423 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1)));
424 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2)));
425 LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3)));
426 LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL)));
427 }
428
429 return B_OK;
430 }
431
eng_crtc_depth(int mode)432 status_t eng_crtc_depth(int mode)
433 {
434 uint8 viddelay = 0;
435 uint32 genctrl = 0;
436
437 /* set VCLK scaling */
438 switch(mode)
439 {
440 case BPP8:
441 viddelay = 0x01;
442 /* genctrl b4 & b5 reset: 'direct mode' */
443 genctrl = 0x00101100;
444 break;
445 case BPP15:
446 viddelay = 0x02;
447 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
448 genctrl = 0x00100130;
449 break;
450 case BPP16:
451 viddelay = 0x02;
452 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
453 genctrl = 0x00101130;
454 break;
455 case BPP24:
456 viddelay = 0x03;
457 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
458 genctrl = 0x00100130;
459 break;
460 case BPP32:
461 viddelay = 0x03;
462 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
463 genctrl = 0x00101130;
464 break;
465 }
466 /* enable access to primary head */
467 set_crtc_owner(0);
468
469 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay));
470 DACW(GENCTRL, genctrl);
471
472 return B_OK;
473 }
474
eng_crtc_dpms(bool display,bool h,bool v)475 status_t eng_crtc_dpms(bool display, bool h, bool v)
476 {
477 uint8 temp;
478
479 LOG(4,("CRTC: setting DPMS: "));
480
481 /* enable access to primary head */
482 set_crtc_owner(0);
483
484 /* start synchronous reset: required before turning screen off! */
485 SEQW(RESET, 0x01);
486
487 /* turn screen off */
488 temp = SEQR(CLKMODE);
489 if (display)
490 {
491 SEQW(CLKMODE, (temp & ~0x20));
492
493 /* end synchronous reset if display should be enabled */
494 SEQW(RESET, 0x03);
495
496 //'safe mode' test! feedback needed with this 'setting'!
497 if (0)//si->ps.tmds1_active)
498 {
499 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink)
500 * internal transmitters... */
501 /* note:
502 * the powerbits in this register are hardwired to the DVI connectors,
503 * instead of to the DACs! (confirmed NV34) */
504 //fixme...
505 DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff));
506 /* ... and powerup external TMDS transmitter if it exists */
507 /* (confirmed OK on NV28 and NV34) */
508 CRTCW(0x59, (CRTCR(0x59) | 0x01));
509 }
510
511 LOG(4,("display on, "));
512 }
513 else
514 {
515 SEQW(CLKMODE, (temp | 0x20));
516
517 //'safe mode' test! feedback needed with this 'setting'!
518 if (0)//si->ps.tmds1_active)
519 {
520 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink)
521 * internal transmitters... */
522 /* note:
523 * the powerbits in this register are hardwired to the DVI connectors,
524 * instead of to the DACs! (confirmed NV34) */
525 //fixme...
526 DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000));
527 /* ... and powerdown external TMDS transmitter if it exists */
528 /* (confirmed OK on NV28 and NV34) */
529 CRTCW(0x59, (CRTCR(0x59) & 0xfe));
530 }
531
532 LOG(4,("display off, "));
533 }
534
535 if (h)
536 {
537 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f));
538 LOG(4,("hsync enabled, "));
539 }
540 else
541 {
542 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80));
543 LOG(4,("hsync disabled, "));
544 }
545 if (v)
546 {
547 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf));
548 LOG(4,("vsync enabled\n"));
549 }
550 else
551 {
552 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40));
553 LOG(4,("vsync disabled\n"));
554 }
555
556 return B_OK;
557 }
558
eng_crtc_dpms_fetch(bool * display,bool * h,bool * v)559 status_t eng_crtc_dpms_fetch(bool *display, bool *h, bool *v)
560 {
561 /* enable access to primary head */
562 set_crtc_owner(0);
563
564 *display = !(SEQR(CLKMODE) & 0x20);
565 *h = !(CRTCR(REPAINT1) & 0x80);
566 *v = !(CRTCR(REPAINT1) & 0x40);
567
568 LOG(4,("CTRC: fetched DPMS state: "));
569 if (*display) LOG(4,("display on, "));
570 else LOG(4,("display off, "));
571 if (*h) LOG(4,("hsync enabled, "));
572 else LOG(4,("hsync disabled, "));
573 if (*v) LOG(4,("vsync enabled\n"));
574 else LOG(4,("vsync disabled\n"));
575
576 return B_OK;
577 }
578
eng_crtc_set_display_pitch()579 status_t eng_crtc_set_display_pitch()
580 {
581 uint32 offset;
582
583 LOG(4,("CRTC: setting card pitch (offset between lines)\n"));
584
585 /* figure out offset value hardware needs */
586 offset = si->fbc.bytes_per_row / 8;
587
588 LOG(2,("CRTC: offset register set to: $%04x\n", offset));
589
590 /* enable access to primary head */
591 set_crtc_owner(0);
592
593 /* program the card */
594 CRTCW(PITCHL, (offset & 0x00ff));
595 CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3)));
596
597 return B_OK;
598 }
599
eng_crtc_set_display_start(uint32 startadd,uint8 bpp)600 status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
601 {
602 uint8 temp;
603 uint32 timeout = 0;
604
605 LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp));
606
607 LOG(2,("CRTC: startadd: $%08x\n", startadd));
608 LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));
609 LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));
610
611 /* we might have no retraces during setmode! */
612 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
613 while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
614 (timeout < (25000/10)))
615 {
616 /* don't snooze much longer or retrace might get missed! */
617 snooze(10);
618 timeout++;
619 }
620
621 /* enable access to primary head */
622 set_crtc_owner(0);
623
624 if (si->ps.card_arch == NV04A)
625 {
626 /* upto 32Mb RAM adressing: must be used this way on pre-NV10! */
627
628 /* set standard registers */
629 /* (NVidia: startadress in 32bit words (b2 - b17) */
630 CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2));
631 CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10));
632
633 /* set extended registers */
634 /* NV4 extended bits: (b18-22) */
635 temp = (CRTCR(REPAINT0) & 0xe0);
636 CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18)));
637 /* NV4 extended bits: (b23-24) */
638 temp = (CRTCR(HEB) & 0x9f);
639 CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18)));
640 }
641 else
642 {
643 /* upto 4Gb RAM adressing: must be used on NV10 and later! */
644 /* NOTE:
645 * While this register also exists on pre-NV10 cards, it will
646 * wrap-around at 16Mb boundaries!! */
647
648 /* 30bit adress in 32bit words */
649 ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc);
650 }
651
652 /* set NV4/NV10 byte adress: (b0 - 1) */
653 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
654
655 return B_OK;
656 }
657
eng_crtc_cursor_init()658 status_t eng_crtc_cursor_init()
659 {
660 int i;
661 uint32 * fb;
662 /* cursor bitmap will be stored at the start of the framebuffer */
663 const uint32 curadd = 0;
664
665 /* enable access to primary head */
666 set_crtc_owner(0);
667
668 /* set cursor bitmap adress ... */
669 if ((si->ps.card_arch == NV04A) || (si->ps.laptop))
670 {
671 /* must be used this way on pre-NV10 and on all 'Go' cards! */
672
673 /* cursorbitmap must start on 2Kbyte boundary: */
674 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */
675 CRTCW(CURCTL0, ((curadd & 0x0001f800) >> 9));
676 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */
677 CRTCW(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80));
678 /* set adress bit24-31 */
679 CRTCW(CURCTL2, ((curadd & 0xff000000) >> 24));
680 }
681 else
682 {
683 /* upto 4Gb RAM adressing:
684 * can be used on NV10 and later (except for 'Go' cards)! */
685 /* NOTE:
686 * This register does not exist on pre-NV10 and 'Go' cards. */
687
688 /* cursorbitmap must still start on 2Kbyte boundary: */
689 ENG_RG32(RG32_NV10CURADD32) = (curadd & 0xfffff800);
690 }
691
692 /* set cursor colour: not needed because of direct nature of cursor bitmap. */
693
694 /*clear cursor*/
695 fb = (uint32 *) si->framebuffer + curadd;
696 for (i=0;i<(2048/4);i++)
697 {
698 fb[i]=0;
699 }
700
701 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
702 ENG_RG32(RG32_CURCONF) = 0x02000100;
703
704 /* activate hardware cursor */
705 eng_crtc_cursor_show();
706
707 return B_OK;
708 }
709
eng_crtc_cursor_show()710 status_t eng_crtc_cursor_show()
711 {
712 LOG(4,("CRTC: enabling cursor\n"));
713
714 /* enable access to CRTC1 on dualhead cards */
715 set_crtc_owner(0);
716
717 /* b0 = 1 enables cursor */
718 CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01));
719
720 return B_OK;
721 }
722
eng_crtc_cursor_hide()723 status_t eng_crtc_cursor_hide()
724 {
725 LOG(4,("CRTC: disabling cursor\n"));
726
727 /* enable access to primary head */
728 set_crtc_owner(0);
729
730 /* b0 = 0 disables cursor */
731 CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe));
732
733 return B_OK;
734 }
735
736 /*set up cursor shape*/
eng_crtc_cursor_define(uint8 * andMask,uint8 * xorMask)737 status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask)
738 {
739 int x, y;
740 uint8 b;
741 uint16 *cursor;
742 uint16 pixel;
743
744 /* get a pointer to the cursor */
745 cursor = (uint16*) si->framebuffer;
746
747 /* draw the cursor */
748 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */
749 for (y = 0; y < 16; y++)
750 {
751 b = 0x80;
752 for (x = 0; x < 8; x++)
753 {
754 /* preset transparant */
755 pixel = 0x0000;
756 /* set white if requested */
757 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
758 /* set black if requested */
759 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000;
760 /* set invert if requested */
761 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff;
762 /* place the pixel in the bitmap */
763 cursor[x + (y * 32)] = pixel;
764 b >>= 1;
765 }
766 xorMask++;
767 andMask++;
768 b = 0x80;
769 for (; x < 16; x++)
770 {
771 /* preset transparant */
772 pixel = 0x0000;
773 /* set white if requested */
774 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
775 /* set black if requested */
776 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000;
777 /* set invert if requested */
778 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff;
779 /* place the pixel in the bitmap */
780 cursor[x + (y * 32)] = pixel;
781 b >>= 1;
782 }
783 xorMask++;
784 andMask++;
785 }
786
787 return B_OK;
788 }
789
790 /* position the cursor */
eng_crtc_cursor_position(uint16 x,uint16 y)791 status_t eng_crtc_cursor_position(uint16 x, uint16 y)
792 {
793 uint16 yhigh;
794
795 /* make sure we are beyond the first line of the cursorbitmap being drawn during
796 * updating the position to prevent distortions: no double buffering feature */
797 /* Note:
798 * we need to return as quick as possible or some apps will exhibit lagging.. */
799
800 /* read the old cursor Y position */
801 yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16);
802 /* make sure we will wait until we are below both the old and new Y position:
803 * visible cursorbitmap drawing needs to be done at least... */
804 if (y > yhigh) yhigh = y;
805
806 if (yhigh < (si->dm.timing.v_display - 16))
807 {
808 /* we have vertical lines below old and new cursorposition to spare. So we
809 * update the cursor postion 'mid-screen', but below that area. */
810 while (((uint16)(ENG_RG32(RG32_RASTER) & 0x000007ff)) < (yhigh + 16))
811 {
812 snooze(10);
813 }
814 }
815 else
816 {
817 /* no room to spare, just wait for retrace (is relatively slow) */
818 while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display)
819 {
820 /* don't snooze much longer or retrace might get missed! */
821 snooze(10);
822 }
823 }
824
825 /* update cursorposition */
826 DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16)));
827
828 return B_OK;
829 }
830