1 /* CTRC functionality */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-5/2004 4 */ 5 6 #define MODULE_BIT 0x00040000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (si->ps.card_type > NV04) 33 { 34 if (*hd_e > 2048) *hd_e = 2048; 35 } 36 else 37 { 38 if (*hd_e > 1920) *hd_e = 1920; 39 } 40 41 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 42 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 43 44 /* make sure sync pulse is not during display */ 45 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 46 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 47 48 /* correct sync pulse if it is too long: 49 * there are only 5 bits available to save this in the card registers! */ 50 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 51 52 /*vertical*/ 53 /* confine to required number of bits, taking logic into account */ 54 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 55 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 56 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 57 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 58 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 59 60 /* confine to a reasonable height */ 61 if (*vd_e < 480) *vd_e = 480; 62 if (si->ps.card_type > NV04) 63 { 64 if (*vd_e > 1536) *vd_e = 1536; 65 } 66 else 67 { 68 if (*vd_e > 1440) *vd_e = 1440; 69 } 70 71 /*if vertical total does not leave room for a sync pulse, increase it!*/ 72 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 73 74 /* make sure sync pulse is not during display */ 75 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 76 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 77 78 /* correct sync pulse if it is too long: 79 * there are only 4 bits available to save this in the card registers! */ 80 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 81 82 return B_OK; 83 } 84 85 /*set a mode line - inputs are in pixels*/ 86 status_t nv_crtc_set_timing(display_mode target) 87 { 88 uint8 temp; 89 90 uint32 htotal; /*total horizontal total VCLKs*/ 91 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 92 uint32 hsync_s; /*begin of horizontal sync pulse*/ 93 uint32 hsync_e; /*end of horizontal sync pulse*/ 94 uint32 hblnk_s; /*begin horizontal blanking*/ 95 uint32 hblnk_e; /*end horizontal blanking*/ 96 97 uint32 vtotal; /*total vertical total scanlines*/ 98 uint32 vdisp_e; /*end of vertical display*/ 99 uint32 vsync_s; /*begin of vertical sync pulse*/ 100 uint32 vsync_e; /*end of vertical sync pulse*/ 101 uint32 vblnk_s; /*begin vertical blanking*/ 102 uint32 vblnk_e; /*end vertical blanking*/ 103 104 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 105 106 LOG(4,("CRTC: setting timing\n")); 107 108 /* setup tuned internal modeline for flatpanel if connected and active */ 109 if (si->ps.tmds1_active) 110 { 111 LOG(2,("CRTC: DFP active: tuning modeline\n")); 112 113 /* horizontal timing */ 114 //testing (640x480): total = 135% is too much, 120% to small... 115 //total = display + 160 equals panel modeline: but must be smaller...? 116 // target.timing.h_total = target.timing.h_display + 152;//160;//128 117 // target.timing.h_sync_start = target.timing.h_total - 136;//144;//112 118 // target.timing.h_sync_end = target.timing.h_total - 40;//48;//16 119 //adaptive to panel: fixme: test on 4:3 and 16:10 panels! 120 target.timing.h_sync_start = 121 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) * 122 target.timing.h_display)) & 0xfff8; 123 124 target.timing.h_sync_end = 125 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) * 126 target.timing.h_display)) & 0xfff8; 127 128 target.timing.h_total = 129 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) * 130 target.timing.h_display)) & 0xfff8) - 8; 131 132 if (target.timing.h_sync_start == target.timing.h_display) 133 target.timing.h_sync_start += 8; 134 if (target.timing.h_sync_end == target.timing.h_total) 135 target.timing.h_sync_end -= 8; 136 137 /* vertical timing */ 138 // target.timing.v_total = target.timing.v_display + 6; 139 // target.timing.v_sync_start = target.timing.v_total - 3; 140 // target.timing.v_sync_end = target.timing.v_total - 2; 141 target.timing.v_sync_start = 142 ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) * 143 target.timing.v_display)); 144 145 target.timing.v_sync_end = 146 ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) * 147 target.timing.v_display)); 148 149 target.timing.v_total = 150 ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) * 151 target.timing.v_display)) - 1; 152 153 if (target.timing.v_sync_start == target.timing.v_display) 154 target.timing.v_sync_start += 1; 155 if (target.timing.v_sync_end == target.timing.v_total) 156 target.timing.v_sync_end -= 1; 157 158 /* disable GPU scaling testmode so automatic scaling will be done */ 159 DACW(FP_DEBUG1, 0); 160 } 161 162 /* Modify parameters as required by standard VGA */ 163 htotal = ((target.timing.h_total >> 3) - 5); 164 hdisp_e = ((target.timing.h_display >> 3) - 1); 165 hblnk_s = hdisp_e; 166 hblnk_e = (htotal + 4);//0; 167 hsync_s = (target.timing.h_sync_start >> 3); 168 hsync_e = (target.timing.h_sync_end >> 3); 169 170 vtotal = target.timing.v_total - 2; 171 vdisp_e = target.timing.v_display - 1; 172 vblnk_s = vdisp_e; 173 vblnk_e = (vtotal + 1); 174 vsync_s = target.timing.v_sync_start;//-1; 175 vsync_e = target.timing.v_sync_end;//-1; 176 177 /* prevent memory adress counter from being reset (linecomp may not occur) */ 178 linecomp = target.timing.v_display; 179 180 /* enable access to primary head */ 181 set_crtc_owner(0); 182 183 /* Note for laptop and DVI flatpanels: 184 * CRTC timing has a seperate set of registers from flatpanel timing. 185 * The flatpanel timing registers have scaling registers that are used to match 186 * these two modelines. */ 187 { 188 LOG(4,("CRTC: Setting full timing...\n")); 189 190 /* log the mode that will be set */ 191 LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 192 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 193 194 /* actually program the card! */ 195 /* unlock CRTC registers at index 0-7 */ 196 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); 197 /* horizontal standard VGA regs */ 198 CRTCW(HTOTAL, (htotal & 0xff)); 199 CRTCW(HDISPE, (hdisp_e & 0xff)); 200 CRTCW(HBLANKS, (hblnk_s & 0xff)); 201 /* also unlock vertical retrace registers in advance */ 202 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 203 CRTCW(HSYNCS, (hsync_s & 0xff)); 204 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 205 206 /* vertical standard VGA regs */ 207 CRTCW(VTOTAL, (vtotal & 0xff)); 208 CRTCW(OVERFLOW, 209 ( 210 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 211 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 212 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 213 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 214 )); 215 CRTCW(PRROWSCN, 0x00); /* not used */ 216 CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 217 CRTCW(VSYNCS, (vsync_s & 0xff)); 218 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 219 CRTCW(VDISPE, (vdisp_e & 0xff)); 220 CRTCW(VBLANKS, (vblnk_s & 0xff)); 221 CRTCW(VBLANKE, (vblnk_e & 0xff)); 222 CRTCW(LINECOMP, (linecomp & 0xff)); 223 224 /* horizontal extended regs */ 225 //fixme: we reset bit4. is this correct?? 226 CRTCW(HEB, (CRTCR(HEB) & 0xe0) | 227 ( 228 ((htotal & 0x100) >> (8 - 0)) | 229 ((hdisp_e & 0x100) >> (8 - 1)) | 230 ((hblnk_s & 0x100) >> (8 - 2)) | 231 ((hsync_s & 0x100) >> (8 - 3)) 232 )); 233 234 /* (mostly) vertical extended regs */ 235 CRTCW(LSR, 236 ( 237 ((vtotal & 0x400) >> (10 - 0)) | 238 ((vdisp_e & 0x400) >> (10 - 1)) | 239 ((vsync_s & 0x400) >> (10 - 2)) | 240 ((vblnk_s & 0x400) >> (10 - 3)) | 241 ((hblnk_e & 0x040) >> (6 - 4)) 242 //fixme: we still miss one linecomp bit!?! is this it?? 243 //| ((linecomp & 0x400) >> 3) 244 )); 245 246 /* more vertical extended regs (on GeForce cards only) */ 247 if (si->ps.card_arch >= NV10A) 248 { 249 CRTCW(EXTRA, 250 ( 251 ((vtotal & 0x800) >> (11 - 0)) | 252 ((vdisp_e & 0x800) >> (11 - 2)) | 253 ((vsync_s & 0x800) >> (11 - 4)) | 254 ((vblnk_s & 0x800) >> (11 - 6)) 255 //fixme: do we miss another linecomp bit!?! 256 )); 257 } 258 259 /* setup 'large screen' mode */ 260 if (target.timing.h_display >= 1280) 261 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); 262 else 263 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); 264 265 /* setup HSYNC & VSYNC polarity */ 266 LOG(2,("CRTC: sync polarity: ")); 267 temp = NV_REG8(NV8_MISCR); 268 if (target.timing.flags & B_POSITIVE_HSYNC) 269 { 270 LOG(2,("H:pos ")); 271 temp &= ~0x40; 272 } 273 else 274 { 275 LOG(2,("H:neg ")); 276 temp |= 0x40; 277 } 278 if (target.timing.flags & B_POSITIVE_VSYNC) 279 { 280 LOG(2,("V:pos ")); 281 temp &= ~0x80; 282 } 283 else 284 { 285 LOG(2,("V:neg ")); 286 temp |= 0x80; 287 } 288 NV_REG8(NV8_MISCW) = temp; 289 290 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 291 } 292 293 /* always disable interlaced operation */ 294 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 295 CRTCW(INTERLACE, 0xff); 296 297 /* setup flatpanel if connected and active */ 298 if (si->ps.tmds1_active) 299 { 300 uint32 iscale_x, iscale_y; 301 302 /* calculate inverse scaling factors used by hardware in 20.12 format */ 303 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display); 304 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display); 305 306 /* unblock flatpanel timing programming (or something like that..) */ 307 CRTCW(FP_HTIMING, 0); 308 CRTCW(FP_VTIMING, 0); 309 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); 310 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); 311 312 /* enable full width visibility on flatpanel */ 313 DACW(FP_HVALID_S, 0); 314 DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1)); 315 /* enable full height visibility on flatpanel */ 316 DACW(FP_VVALID_S, 0); 317 DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1)); 318 319 /* nVidia cards support upscaling except on ??? */ 320 /* NV11 cards can upscale after all! */ 321 if (0)//si->ps.card_type == NV11) 322 { 323 /* disable last fetched line limiting */ 324 DACW(FP_DEBUG2, 0x00000000); 325 /* inform panel to scale if needed */ 326 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 327 { 328 LOG(2,("CRTC: DFP needs to do scaling\n")); 329 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 330 } 331 else 332 { 333 LOG(2,("CRTC: no scaling for DFP needed\n")); 334 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 335 } 336 } 337 else 338 { 339 float dm_aspect; 340 341 LOG(2,("CRTC: GPU scales for DFP if needed\n")); 342 343 /* calculate display mode aspect */ 344 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 345 346 /* limit last fetched line if vertical scaling is done */ 347 if (iscale_y != (1 << 12)) 348 DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 349 else 350 DACW(FP_DEBUG2, 0x00000000); 351 352 /* inform panel not to scale */ 353 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 354 355 /* GPU scaling is automatically setup by hardware, so only modify this 356 * scalingfactor for non 4:3 (1.33) aspect panels; 357 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 358 359 /* correct for widescreen panels relative to mode... 360 * (so if panel is more widescreen than mode being set) */ 361 /* BTW: known widescreen panels: 362 * 1280 x 800 (1.60), 363 * 1440 x 900 (1.60), 364 * 1680 x 1050 (1.60), 365 * 1920 x 1200 (1.60). */ 366 /* known 4:3 aspect non-standard resolution panels: 367 * 1400 x 1050 (1.33). */ 368 /* NOTE: 369 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 370 if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10))) 371 { 372 uint16 diff; 373 374 LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n")); 375 376 /* X-scaling should be the same as Y-scaling */ 377 iscale_x = iscale_y; 378 /* enable testmode (b12) and program modified X-scaling factor */ 379 DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 380 /* center/cut-off left and right side of screen */ 381 diff = ((si->ps.p1_timing.h_display - 382 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 383 / 2); 384 DACW(FP_HVALID_S, diff); 385 DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1)); 386 } 387 /* correct for portrait panels... */ 388 /* NOTE: 389 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 390 if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10))) 391 { 392 LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n")); 393 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 394 } 395 } 396 397 /* do some logging.. */ 398 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 399 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 400 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 401 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 402 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 403 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 404 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2))); 405 LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3))); 406 LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL))); 407 } 408 409 return B_OK; 410 } 411 412 status_t nv_crtc_depth(int mode) 413 { 414 uint8 viddelay = 0; 415 uint32 genctrl = 0; 416 417 /* set VCLK scaling */ 418 switch(mode) 419 { 420 case BPP8: 421 viddelay = 0x01; 422 /* genctrl b4 & b5 reset: 'direct mode' */ 423 genctrl = 0x00101100; 424 break; 425 case BPP15: 426 viddelay = 0x02; 427 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 428 genctrl = 0x00100130; 429 break; 430 case BPP16: 431 viddelay = 0x02; 432 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 433 genctrl = 0x00101130; 434 break; 435 case BPP24: 436 viddelay = 0x03; 437 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 438 genctrl = 0x00100130; 439 break; 440 case BPP32: 441 viddelay = 0x03; 442 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 443 genctrl = 0x00101130; 444 break; 445 } 446 /* enable access to primary head */ 447 set_crtc_owner(0); 448 449 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); 450 DACW(GENCTRL, genctrl); 451 452 return B_OK; 453 } 454 455 status_t nv_crtc_dpms(bool display, bool h, bool v) 456 { 457 uint8 temp; 458 459 LOG(4,("CRTC: setting DPMS: ")); 460 461 /* enable access to primary head */ 462 set_crtc_owner(0); 463 464 /* start synchronous reset: required before turning screen off! */ 465 SEQW(RESET, 0x01); 466 467 /* turn screen off */ 468 temp = SEQR(CLKMODE); 469 if (display) 470 { 471 SEQW(CLKMODE, (temp & ~0x20)); 472 473 /* end synchronous reset if display should be enabled */ 474 SEQW(RESET, 0x03); 475 476 //'safe mode' test! feedback needed with this 'setting'! 477 if (0)//si->ps.tmds1_active) 478 { 479 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 480 * internal transmitters... */ 481 /* note: 482 * the powerbits in this register are hardwired to the DVI connectors, 483 * instead of to the DACs! (confirmed NV34) */ 484 //fixme... 485 DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff)); 486 /* ... and powerup external TMDS transmitter if it exists */ 487 /* (confirmed OK on NV28 and NV34) */ 488 CRTCW(0x59, (CRTCR(0x59) | 0x01)); 489 } 490 491 LOG(4,("display on, ")); 492 } 493 else 494 { 495 SEQW(CLKMODE, (temp | 0x20)); 496 497 //'safe mode' test! feedback needed with this 'setting'! 498 if (0)//si->ps.tmds1_active) 499 { 500 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 501 * internal transmitters... */ 502 /* note: 503 * the powerbits in this register are hardwired to the DVI connectors, 504 * instead of to the DACs! (confirmed NV34) */ 505 //fixme... 506 DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000)); 507 /* ... and powerdown external TMDS transmitter if it exists */ 508 /* (confirmed OK on NV28 and NV34) */ 509 CRTCW(0x59, (CRTCR(0x59) & 0xfe)); 510 } 511 512 LOG(4,("display off, ")); 513 } 514 515 if (h) 516 { 517 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); 518 LOG(4,("hsync enabled, ")); 519 } 520 else 521 { 522 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80)); 523 LOG(4,("hsync disabled, ")); 524 } 525 if (v) 526 { 527 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); 528 LOG(4,("vsync enabled\n")); 529 } 530 else 531 { 532 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40)); 533 LOG(4,("vsync disabled\n")); 534 } 535 536 return B_OK; 537 } 538 539 status_t nv_crtc_dpms_fetch(bool *display, bool *h, bool *v) 540 { 541 /* enable access to primary head */ 542 set_crtc_owner(0); 543 544 *display = !(SEQR(CLKMODE) & 0x20); 545 *h = !(CRTCR(REPAINT1) & 0x80); 546 *v = !(CRTCR(REPAINT1) & 0x40); 547 548 LOG(4,("CTRC: fetched DPMS state:")); 549 if (display) LOG(4,("display on, ")); 550 else LOG(4,("display off, ")); 551 if (h) LOG(4,("hsync enabled, ")); 552 else LOG(4,("hsync disabled, ")); 553 if (v) LOG(4,("vsync enabled\n")); 554 else LOG(4,("vsync disabled\n")); 555 556 return B_OK; 557 } 558 559 status_t nv_crtc_set_display_pitch() 560 { 561 uint32 offset; 562 563 LOG(4,("CRTC: setting card pitch (offset between lines)\n")); 564 565 /* figure out offset value hardware needs */ 566 offset = si->fbc.bytes_per_row / 8; 567 568 LOG(2,("CRTC: offset register set to: $%04x\n", offset)); 569 570 /* enable access to primary head */ 571 set_crtc_owner(0); 572 573 /* program the card */ 574 CRTCW(PITCHL, (offset & 0x00ff)); 575 CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 576 577 return B_OK; 578 } 579 580 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) 581 { 582 uint8 temp; 583 uint32 timeout = 0; 584 585 LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp)); 586 587 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 588 LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer)); 589 LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer)); 590 591 /* we might have no retraces during setmode! */ 592 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 593 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 594 (timeout < (25000/10))) 595 { 596 /* don't snooze much longer or retrace might get missed! */ 597 snooze(10); 598 timeout++; 599 } 600 601 /* enable access to primary head */ 602 set_crtc_owner(0); 603 604 if (si->ps.card_arch == NV04A) 605 { 606 /* upto 32Mb RAM adressing: must be used this way on pre-NV10! */ 607 608 /* set standard registers */ 609 /* (NVidia: startadress in 32bit words (b2 - b17) */ 610 CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2)); 611 CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10)); 612 613 /* set extended registers */ 614 /* NV4 extended bits: (b18-22) */ 615 temp = (CRTCR(REPAINT0) & 0xe0); 616 CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18))); 617 /* NV4 extended bits: (b23-24) */ 618 temp = (CRTCR(HEB) & 0x9f); 619 CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18))); 620 } 621 else 622 { 623 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 624 /* NOTE: 625 * While this register also exists on pre-NV10 cards, it will 626 * wrap-around at 16Mb boundaries!! */ 627 628 /* 30bit adress in 32bit words */ 629 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 630 } 631 632 /* set NV4/NV10 byte adress: (b0 - 1) */ 633 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1)); 634 635 return B_OK; 636 } 637 638 status_t nv_crtc_cursor_init() 639 { 640 int i; 641 uint32 * fb; 642 /* cursor bitmap will be stored at the start of the framebuffer */ 643 const uint32 curadd = 0; 644 645 /* enable access to primary head */ 646 set_crtc_owner(0); 647 648 /* set cursor bitmap adress ... */ 649 if ((si->ps.card_arch == NV04A) || (si->ps.laptop)) 650 { 651 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 652 653 /* cursorbitmap must start on 2Kbyte boundary: */ 654 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 655 CRTCW(CURCTL0, ((curadd & 0x0001f800) >> 9)); 656 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 657 CRTCW(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 658 /* set adress bit24-31 */ 659 CRTCW(CURCTL2, ((curadd & 0xff000000) >> 24)); 660 } 661 else 662 { 663 /* upto 4Gb RAM adressing: 664 * can be used on NV10 and later (except for 'Go' cards)! */ 665 /* NOTE: 666 * This register does not exist on pre-NV10 and 'Go' cards. */ 667 668 /* cursorbitmap must still start on 2Kbyte boundary: */ 669 NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); 670 } 671 672 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 673 674 /*clear cursor*/ 675 fb = (uint32 *) si->framebuffer + curadd; 676 for (i=0;i<(2048/4);i++) 677 { 678 fb[i]=0; 679 } 680 681 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 682 NV_REG32(NV32_CURCONF) = 0x02000100; 683 684 /* activate hardware cursor */ 685 nv_crtc_cursor_show(); 686 687 return B_OK; 688 } 689 690 status_t nv_crtc_cursor_show() 691 { 692 LOG(4,("CRTC: enabling cursor\n")); 693 694 /* enable access to CRTC1 on dualhead cards */ 695 set_crtc_owner(0); 696 697 /* b0 = 1 enables cursor */ 698 CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01)); 699 700 return B_OK; 701 } 702 703 status_t nv_crtc_cursor_hide() 704 { 705 LOG(4,("CRTC: disabling cursor\n")); 706 707 /* enable access to primary head */ 708 set_crtc_owner(0); 709 710 /* b0 = 0 disables cursor */ 711 CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe)); 712 713 return B_OK; 714 } 715 716 /*set up cursor shape*/ 717 status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask) 718 { 719 int x, y; 720 uint8 b; 721 uint16 *cursor; 722 uint16 pixel; 723 724 /* get a pointer to the cursor */ 725 cursor = (uint16*) si->framebuffer; 726 727 /* draw the cursor */ 728 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 729 for (y = 0; y < 16; y++) 730 { 731 b = 0x80; 732 for (x = 0; x < 8; x++) 733 { 734 /* preset transparant */ 735 pixel = 0x0000; 736 /* set white if requested */ 737 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 738 /* set black if requested */ 739 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 740 /* set invert if requested */ 741 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 742 /* place the pixel in the bitmap */ 743 cursor[x + (y * 32)] = pixel; 744 b >>= 1; 745 } 746 xorMask++; 747 andMask++; 748 b = 0x80; 749 for (; x < 16; x++) 750 { 751 /* preset transparant */ 752 pixel = 0x0000; 753 /* set white if requested */ 754 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 755 /* set black if requested */ 756 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 757 /* set invert if requested */ 758 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 759 /* place the pixel in the bitmap */ 760 cursor[x + (y * 32)] = pixel; 761 b >>= 1; 762 } 763 xorMask++; 764 andMask++; 765 } 766 767 return B_OK; 768 } 769 770 /* position the cursor */ 771 status_t nv_crtc_cursor_position(uint16 x, uint16 y) 772 { 773 uint16 yhigh; 774 775 /* make sure we are beyond the first line of the cursorbitmap being drawn during 776 * updating the position to prevent distortions: no double buffering feature */ 777 /* Note: 778 * we need to return as quick as possible or some apps will exhibit lagging.. */ 779 780 /* read the old cursor Y position */ 781 yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16); 782 /* make sure we will wait until we are below both the old and new Y position: 783 * visible cursorbitmap drawing needs to be done at least... */ 784 if (y > yhigh) yhigh = y; 785 786 if (yhigh < (si->dm.timing.v_display - 16)) 787 { 788 /* we have vertical lines below old and new cursorposition to spare. So we 789 * update the cursor postion 'mid-screen', but below that area. */ 790 while (((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) 791 { 792 snooze(10); 793 } 794 } 795 else 796 { 797 /* no room to spare, just wait for retrace (is relatively slow) */ 798 while ((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) 799 { 800 /* don't snooze much longer or retrace might get missed! */ 801 snooze(10); 802 } 803 } 804 805 /* update cursorposition */ 806 DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 807 808 return B_OK; 809 } 810