Searched refs:fRegBase (Results 1 – 6 of 6) sorted by relevance
15 fRegBase[PXA_ICMR] |= 1 << irq; in EnableInterrupt()19 fRegBase[PXA_ICMR2] |= 1 << (irq - 32); in EnableInterrupt()27 fRegBase[PXA_ICMR] &= ~(1 << irq); in DisableInterrupt()31 fRegBase[PXA_ICMR2] &= ~(1 << (irq - 32)); in DisableInterrupt()39 if (fRegBase[PXA_ICIP] & (1 << i)) in HandleInterrupt()47 fRegArea = vm_map_physical_memory(B_SYSTEM_TEAM, "intc-pxa", (void**)&fRegBase, in PXAInterruptController()53 fRegBase[PXA_ICMR] = 0; in PXAInterruptController()54 fRegBase[PXA_ICMR2] = 0; in PXAInterruptController()96 fRegBase[PXA_OIER] |= (1 << 4); in SetTimeout()97 fRegBase[PXA_OMCR4] = res; in SetTimeout()[all …]
33 fRegBase[INTCPS_MIR_CLEARn + (8 * bank)] = 1 << bit; in EnableInterrupt()41 fRegBase[INTCPS_MIR_SETn + (8 * bank)] = 1 << bit; in DisableInterrupt()53 irqnr = fRegBase[INTCPS_PENDING_IRQn + (8 * i)]; in HandleInterrupt()61 irqnr = fRegBase[INTCPS_SIR_IRQ]; in HandleInterrupt()73 fRegBase[INTCPS_CONTROL] = 1; in HandleInterrupt()80 uint32 tmp = fRegBase[INTCPS_REVISION] & 0xff; in SoftReset()83 fRegBase, tmp >> 4, tmp & 0xf); in SoftReset()85 tmp = fRegBase[INTCPS_SYSCONFIG]; in SoftReset()87 fRegBase[INTCPS_SYSCONFIG] = tmp; in SoftReset()89 while (!(fRegBase[INTCPS_SYSSTATUS] & 0x1)) in SoftReset()[all …]
23 fRegBase[SUN4I_INTC_MASK_REG0] |= 1 << irq; in EnableInterrupt()28 fRegBase[SUN4I_INTC_MASK_REG1] |= 1 << (irq - 32); in EnableInterrupt()32 fRegBase[SUN4I_INTC_MASK_REG2] |= 1 << (irq - 64); in EnableInterrupt()40 fRegBase[SUN4I_INTC_MASK_REG0] &= ~(1 << irq); in DisableInterrupt()45 fRegBase[SUN4I_INTC_MASK_REG1] &= ~(1 << (irq - 32)); in DisableInterrupt()49 fRegBase[SUN4I_INTC_MASK_REG1] &= ~(1 << (irq - 64)); in DisableInterrupt()58 if (fRegBase[SUN4I_INTC_PEND_REG0] & (1 << i)) in HandleInterrupt()63 if (fRegBase[SUN4I_INTC_PEND_REG1] & (1 << i)) in HandleInterrupt()68 if (fRegBase[SUN4I_INTC_PEND_REG2] & (1 << i)) in HandleInterrupt()76 fRegArea = vm_map_physical_memory(B_SYSTEM_TEAM, "intc-sun4i", (void**)&fRegBase, in Sun4iInterruptController()[all …]
20 uint32 *fRegBase; variable40 uint32 *fRegBase; variable
22 uint32 *fRegBase; variable52 uint32 *fRegBase; variable
22 uint32 *fRegBase; variable