33 	fRegBase[INTCPS_MIR_CLEARn + (8 * bank)] = 1 << bit;  in EnableInterrupt()
41 	fRegBase[INTCPS_MIR_SETn + (8 * bank)] = 1 << bit;  in DisableInterrupt()
53 			irqnr = fRegBase[INTCPS_PENDING_IRQn + (8 * i)];  in HandleInterrupt()
61 		irqnr = fRegBase[INTCPS_SIR_IRQ];  in HandleInterrupt()
73 		fRegBase[INTCPS_CONTROL] = 1;  in HandleInterrupt()
80 	uint32 tmp = fRegBase[INTCPS_REVISION] & 0xff;  in SoftReset()
83 		fRegBase, tmp >> 4, tmp & 0xf);  in SoftReset()
85 	tmp = fRegBase[INTCPS_SYSCONFIG];  in SoftReset()
87 	fRegBase[INTCPS_SYSCONFIG] = tmp;  in SoftReset()
89         while (!(fRegBase[INTCPS_SYSSTATUS] & 0x1))  in SoftReset()
93         fRegBase[INTCPS_SYSCONFIG] = 1;  in SoftReset()
100 	fRegArea = vm_map_physical_memory(B_SYSTEM_TEAM, "intc-omap3", (void**)&fRegBase,  in OMAP3InterruptController()
109 	fRegBase[INTCPS_PROTECTION] |= 1;  in OMAP3InterruptController()
146 	uint32 ints = fRegBase[TISR] & 7;  in HandleInterrupt()
159 	fRegBase[TISR] = ints;  in HandleInterrupt()
168 	fRegBase[TMAR] = fRegBase[TCRR] + timeout / 1000ULL;  in SetTimeout()
169 	fRegBase[TIER] |= 1; // Enable match interrupt  in SetTimeout()
176 	return fSystemTime + fRegBase[TCRR];  in Time()
183 	fRegBase[TIER] &= ~1; // Disable match interrupt  in Clear()
190 	fRegArea = vm_map_physical_memory(B_SYSTEM_TEAM, "timer-omap3", (void**)&fRegBase,  in OMAP3Timer()
200 	uint32 rev = fRegBase[TIDR];  in OMAP3Timer()
202 		fRegBase, fInterrupt, (rev >> 4) & 0xf, rev & 0xf);  in OMAP3Timer()
205 	fRegBase[TCLR] |= 1;  in OMAP3Timer()
206 	fRegBase[TIER] = 2; // Enable overflow interrupt  in OMAP3Timer()