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Searched refs:CRTCR (Results 1 – 14 of 14) sorted by relevance

/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dcrtc.c212 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); in eng_crtc_set_timing()
234 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); in eng_crtc_set_timing()
242 CRTCW(HEB, (CRTCR(HEB) & 0xe0) | in eng_crtc_set_timing()
277 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); in eng_crtc_set_timing()
279 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); in eng_crtc_set_timing()
315 if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); in eng_crtc_set_timing()
329 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); in eng_crtc_set_timing()
330 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); in eng_crtc_set_timing()
469 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); in eng_crtc_depth()
508 CRTCW(0x59, (CRTCR(0x59) | 0x01)); in eng_crtc_dpms()
[all …]
H A Dinfo.c250 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card()
262 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card()
328 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card_516_up()
340 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card_516_up()
2101 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in detect_panels()
2106 LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL))); in detect_panels()
2114 LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD))); in detect_panels()
2117 LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59))); in detect_panels()
2120 LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f))); in detect_panels()
2123 slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); in detect_panels()
[all …]
H A Dgeneral.c449 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in eng_general_bios_to_powergraphics()
/haiku/src/add-ons/accelerants/via/engine/
H A Dcrtc.c200 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); in eng_crtc_set_timing()
222 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); in eng_crtc_set_timing()
229 CRTCW(HTIMEXT1, (CRTCR(HTIMEXT1) & 0xc8) | in eng_crtc_set_timing()
235 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) & 0xf7) | ((htotal & 0x100) >> (8 - 3))); in eng_crtc_set_timing()
238 CRTCW(VTIMEXT_PIT, (CRTCR(VTIMEXT_PIT) & 0xe0) | in eng_crtc_set_timing()
318 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); in eng_crtc_set_timing()
319 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); in eng_crtc_set_timing()
505 CRTCW(0x59, (CRTCR(0x59) | 0x01)); in eng_crtc_dpms()
526 CRTCW(0x59, (CRTCR(0x59) & 0xfe)); in eng_crtc_dpms()
534 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) & 0xef)); in eng_crtc_dpms()
[all …]
H A Dinfo.c163 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in detect_panels()
168 LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL))); in detect_panels()
176 LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD))); in detect_panels()
179 LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59))); in detect_panels()
182 LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f))); in detect_panels()
185 slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); in detect_panels()
189 tvout1 = !(CRTCR(LCD) & 0x01); in detect_panels()
H A Dgeneral.c456 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in eng_general_bios_to_powergraphics()
H A Dbes.c49 switch (((CRTCR(MEMCLK)) & 0x70) >> 4) in eng_bes_chk_bandwidth()
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_crtc.c338 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); in nv_crtc_set_timing()
360 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); in nv_crtc_set_timing()
368 CRTCW(HEB, (CRTCR(HEB) & 0xe0) | in nv_crtc_set_timing()
403 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); in nv_crtc_set_timing()
405 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); in nv_crtc_set_timing()
441 if (!(si->ps.monitors & CRTC1_TMDS)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); in nv_crtc_set_timing()
455 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); in nv_crtc_set_timing()
456 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); in nv_crtc_set_timing()
595 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); in nv_crtc_depth()
712 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); in nv_crtc_dpms()
[all …]
H A Dnv_i2c.c79 data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01; in OutSCL()
86 data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01; in OutSCL()
93 data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01; in OutSCL()
136 data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01; in OutSDA()
143 data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01; in OutSDA()
150 data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01; in OutSDA()
178 if ((CRTCR(RD_I2CBUS_0) & 0x04)) return true; in InSCL()
181 if ((CRTCR(RD_I2CBUS_1) & 0x04)) return true; in InSCL()
184 if ((CRTCR(RD_I2CBUS_2) & 0x04)) return true; in InSCL()
210 if ((CRTCR(RD_I2CBUS_0) & 0x08)) return true; in InSDA()
[all …]
H A Dnv_info.c262 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card()
274 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card()
340 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card_516_up()
352 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in coldstart_card_516_up()
2239 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in detect_panels()
2244 LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL))); in detect_panels()
2252 LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD))); in detect_panels()
2255 LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59))); in detect_panels()
2258 LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f))); in detect_panels()
2261 slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); in detect_panels()
[all …]
H A Dnv_general.c1739 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in unlock_card()
1746 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); in unlock_card()
/haiku/headers/private/graphics/skeleton/
H A Dmacros.h769 #define CRTCR(A) (ENG_REG8(RG8_CRTCIND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTCDAT)) macro
/haiku/headers/private/graphics/via/
H A Dmacros.h838 #define CRTCR(A) (ENG_REG8(RG8_CRTCIND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTCDAT)) macro
/haiku/headers/private/graphics/nvidia/
H A Dnv_macros.h916 #define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) macro