/haiku/src/system/boot/platform/efi/arch/riscv64/ |
H A D | arch_traps.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | arch_mmu.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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/haiku/src/system/boot/platform/riscv/ |
H A D | traps.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | cpu.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | mmu.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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/haiku/headers/private/kernel/arch/riscv64/ |
H A D | arch_int.h | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | arch_cpu.h | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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/haiku/src/system/kernel/arch/riscv64/ |
H A D | arch_vm_translation_map.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | arch_cpu.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | arch_thread.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | RISCV64VMTranslationMap.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | arch_vm.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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H A D | arch_int.cpp | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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/haiku/headers/private/system/arch/riscv64/ |
H A D | arch_cpu_defs.h | fa557843f23498980832cb32871183f247dbb807 Sun Nov 27 15:27:35 UTC 2022 X512 <danger_mail@list.ru> riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.
Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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