riscv: use atomic CSR bit set/clear operations, refactor

Fix race conditions that cause broken timer interrupts.

Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f
Reviewed-on: https://review.hai

riscv: use atomic CSR bit set/clear operations, refactor

Fix race conditions that cause broken timer interrupts.

Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883
Reviewed-by: X512 <danger_mail@list.ru>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>

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Merge branch 'master' into dev/netservices

Change-Id: I1eb6c2ea2fd0d794ad6378eab8bbb80ce46dfbb8

haiku_loader.riscv: update

* Moved machine mode code from kernel.
* Added MMU page table generation.
* Added QEMU ramfb video driver.

Change-Id: Icd67cd2e8dbf2b568d81ab8dd0d6127ca3cd97a8
Reviewed-o

haiku_loader.riscv: update

* Moved machine mode code from kernel.
* Added MMU page table generation.
* Added QEMU ramfb video driver.

Change-Id: Icd67cd2e8dbf2b568d81ab8dd0d6127ca3cd97a8
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4302
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>

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