1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/types.h> 31 #include <SupportDefs.h> 32 #include <arch/x86/npx.h> 33 #include <posix/fenv.h> 34 35 const fenv_t __fe_dfl_env = { 36 __INITIAL_NPXCW__, 37 0x0000, 38 0x0000, 39 0x1f80, 40 0xffffffff, 41 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 42 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff } 43 }; 44 45 enum __sse_support __has_sse = 46 #ifdef __SSE__ 47 __SSE_YES; 48 #else 49 __SSE_UNK; 50 #endif 51 52 #define getfl(x) __asm __volatile("pushfl\n\tpopl %0" : "=mr" (*(x))) 53 #define setfl(x) __asm __volatile("pushl %0\n\tpopfl" : : "g" (x)) 54 #define cpuid_dx(x) __asm __volatile("pushl %%ebx\n\tmovl $1, %%eax\n\t" \ 55 "cpuid\n\tpopl %%ebx" \ 56 : "=d" (*(x)) : : "eax", "ecx") 57 58 /* 59 * Test for SSE support on this processor. We need to do this because 60 * we need to use ldmxcsr/stmxcsr to get correct results if any part 61 * of the program was compiled to use SSE floating-point, but we can't 62 * use SSE on older processors. 63 */ 64 int 65 __test_sse(void) 66 { 67 int flag, nflag; 68 int dx_features; 69 70 /* Am I a 486? */ 71 getfl(&flag); 72 nflag = flag ^ 0x200000; 73 setfl(nflag); 74 getfl(&nflag); 75 if (flag != nflag) { 76 /* Not a 486, so CPUID should work. */ 77 cpuid_dx(&dx_features); 78 if (dx_features & 0x2000000) { 79 __has_sse = __SSE_YES; 80 return (1); 81 } 82 } 83 __has_sse = __SSE_NO; 84 return (0); 85 } 86 87 int 88 fesetexceptflag(const fexcept_t *flagp, int excepts) 89 { 90 fenv_t env; 91 int mxcsr; 92 93 __fnstenv(&env); 94 env.__status &= ~excepts; 95 env.__status |= *flagp & excepts; 96 __fldenv(env); 97 98 if (__HAS_SSE()) { 99 __stmxcsr(&mxcsr); 100 mxcsr &= ~excepts; 101 mxcsr |= *flagp & excepts; 102 __ldmxcsr(mxcsr); 103 } 104 105 return (0); 106 } 107 108 int 109 feraiseexcept(int excepts) 110 { 111 fexcept_t ex = excepts; 112 113 fesetexceptflag(&ex, excepts); 114 __fwait(); 115 return (0); 116 } 117 118 int 119 fegetenv(fenv_t *envp) 120 { 121 int mxcsr; 122 123 __fnstenv(envp); 124 /* 125 * fnstenv masks all exceptions, so we need to restore 126 * the old control word to avoid this side effect. 127 */ 128 __fldcw(envp->__control); 129 if (__HAS_SSE()) { 130 __stmxcsr(&mxcsr); 131 __set_mxcsr(*envp, mxcsr); 132 } 133 return (0); 134 } 135 136 int 137 feholdexcept(fenv_t *envp) 138 { 139 int mxcsr; 140 141 __fnstenv(envp); 142 __fnclex(); 143 if (__HAS_SSE()) { 144 __stmxcsr(&mxcsr); 145 __set_mxcsr(*envp, mxcsr); 146 mxcsr &= ~FE_ALL_EXCEPT; 147 mxcsr |= FE_ALL_EXCEPT << _SSE_EMASK_SHIFT; 148 __ldmxcsr(mxcsr); 149 } 150 return (0); 151 } 152 153 int 154 feupdateenv(const fenv_t *envp) 155 { 156 int mxcsr, status; 157 158 __fnstsw(&status); 159 if (__HAS_SSE()) 160 __stmxcsr(&mxcsr); 161 else 162 mxcsr = 0; 163 fesetenv(envp); 164 feraiseexcept((mxcsr | status) & FE_ALL_EXCEPT); 165 return (0); 166 } 167 168 int 169 __feenableexcept(int mask) 170 { 171 int mxcsr, control, omask; 172 173 mask &= FE_ALL_EXCEPT; 174 __fnstcw(&control); 175 if (__HAS_SSE()) 176 __stmxcsr(&mxcsr); 177 else 178 mxcsr = 0; 179 omask = (control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT; 180 control &= ~mask; 181 __fldcw(control); 182 if (__HAS_SSE()) { 183 mxcsr &= ~(mask << _SSE_EMASK_SHIFT); 184 __ldmxcsr(mxcsr); 185 } 186 return (~omask); 187 } 188 189 int 190 __fedisableexcept(int mask) 191 { 192 int mxcsr, control, omask; 193 194 mask &= FE_ALL_EXCEPT; 195 __fnstcw(&control); 196 if (__HAS_SSE()) 197 __stmxcsr(&mxcsr); 198 else 199 mxcsr = 0; 200 omask = (control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT; 201 control |= mask; 202 __fldcw(control); 203 if (__HAS_SSE()) { 204 mxcsr |= mask << _SSE_EMASK_SHIFT; 205 __ldmxcsr(mxcsr); 206 } 207 return (~omask); 208 } 209 210 __weak_reference(__feenableexcept, feenableexcept); 211 __weak_reference(__fedisableexcept, fedisableexcept); 212