1950b24e3SAlex Smith /* 2950b24e3SAlex Smith * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 3950b24e3SAlex Smith * Distributed under the terms of the MIT License. 4950b24e3SAlex Smith */ 5*e276cc04SAlex Smith #ifndef KERNEL_ARCH_X86_PAGING_64BIT_PAGING_H 6*e276cc04SAlex Smith #define KERNEL_ARCH_X86_PAGING_64BIT_PAGING_H 7950b24e3SAlex Smith 8950b24e3SAlex Smith 9950b24e3SAlex Smith #include <OS.h> 10950b24e3SAlex Smith 11950b24e3SAlex Smith 12*e276cc04SAlex Smith // PML4 entry bits. 13*e276cc04SAlex Smith #define X86_64_PML4E_PRESENT (1LL << 0) 14*e276cc04SAlex Smith #define X86_64_PML4E_WRITABLE (1LL << 1) 15*e276cc04SAlex Smith #define X86_64_PML4E_USER (1LL << 2) 16*e276cc04SAlex Smith #define X86_64_PML4E_WRITE_THROUGH (1LL << 3) 17*e276cc04SAlex Smith #define X86_64_PML4E_CACHING_DISABLED (1LL << 4) 18*e276cc04SAlex Smith #define X86_64_PML4E_ACCESSED (1LL << 5) 19*e276cc04SAlex Smith #define X86_64_PML4E_NOT_EXECUTABLE (1LL << 63) 20*e276cc04SAlex Smith #define X86_64_PML4E_ADDRESS_MASK 0x000ffffffffff000L 21*e276cc04SAlex Smith 22*e276cc04SAlex Smith // PDPT entry bits. 23*e276cc04SAlex Smith #define X86_64_PDPTE_PRESENT (1LL << 0) 24*e276cc04SAlex Smith #define X86_64_PDPTE_WRITABLE (1LL << 1) 25*e276cc04SAlex Smith #define X86_64_PDPTE_USER (1LL << 2) 26*e276cc04SAlex Smith #define X86_64_PDPTE_WRITE_THROUGH (1LL << 3) 27*e276cc04SAlex Smith #define X86_64_PDPTE_CACHING_DISABLED (1LL << 4) 28*e276cc04SAlex Smith #define X86_64_PDPTE_ACCESSED (1LL << 5) 29*e276cc04SAlex Smith #define X86_64_PDPTE_DIRTY (1LL << 6) 30*e276cc04SAlex Smith #define X86_64_PDPTE_LARGE_PAGE (1LL << 7) 31*e276cc04SAlex Smith #define X86_64_PDPTE_GLOBAL (1LL << 8) 32*e276cc04SAlex Smith #define X86_64_PDPTE_PAT (1LL << 12) 33*e276cc04SAlex Smith #define X86_64_PDPTE_NOT_EXECUTABLE (1LL << 63) 34*e276cc04SAlex Smith #define X86_64_PDPTE_ADDRESS_MASK 0x000ffffffffff000L 35*e276cc04SAlex Smith 36*e276cc04SAlex Smith // Page directory entry bits. 37*e276cc04SAlex Smith #define X86_64_PDE_PRESENT (1LL << 0) 38*e276cc04SAlex Smith #define X86_64_PDE_WRITABLE (1LL << 1) 39*e276cc04SAlex Smith #define X86_64_PDE_USER (1LL << 2) 40*e276cc04SAlex Smith #define X86_64_PDE_WRITE_THROUGH (1LL << 3) 41*e276cc04SAlex Smith #define X86_64_PDE_CACHING_DISABLED (1LL << 4) 42*e276cc04SAlex Smith #define X86_64_PDE_ACCESSED (1LL << 5) 43*e276cc04SAlex Smith #define X86_64_PDE_DIRTY (1LL << 6) 44*e276cc04SAlex Smith #define X86_64_PDE_LARGE_PAGE (1LL << 7) 45*e276cc04SAlex Smith #define X86_64_PDE_GLOBAL (1LL << 8) 46*e276cc04SAlex Smith #define X86_64_PDE_PAT (1LL << 12) 47*e276cc04SAlex Smith #define X86_64_PDE_NOT_EXECUTABLE (1LL << 63) 48*e276cc04SAlex Smith #define X86_64_PDE_ADDRESS_MASK 0x000ffffffffff000L 49*e276cc04SAlex Smith 50*e276cc04SAlex Smith // Page table entry bits. 51*e276cc04SAlex Smith #define X86_64_PTE_PRESENT (1LL << 0) 52*e276cc04SAlex Smith #define X86_64_PTE_WRITABLE (1LL << 1) 53*e276cc04SAlex Smith #define X86_64_PTE_USER (1LL << 2) 54*e276cc04SAlex Smith #define X86_64_PTE_WRITE_THROUGH (1LL << 3) 55*e276cc04SAlex Smith #define X86_64_PTE_CACHING_DISABLED (1LL << 4) 56*e276cc04SAlex Smith #define X86_64_PTE_ACCESSED (1LL << 5) 57*e276cc04SAlex Smith #define X86_64_PTE_DIRTY (1LL << 6) 58*e276cc04SAlex Smith #define X86_64_PTE_PAT (1LL << 7) 59*e276cc04SAlex Smith #define X86_64_PTE_GLOBAL (1LL << 8) 60*e276cc04SAlex Smith #define X86_64_PTE_NOT_EXECUTABLE (1LL << 63) 61*e276cc04SAlex Smith #define X86_64_PTE_ADDRESS_MASK 0x000ffffffffff000L 62*e276cc04SAlex Smith #define X86_64_PTE_PROTECTION_MASK (X86_64_PTE_WRITABLE | X86_64_PTE_USER) 63*e276cc04SAlex Smith #define X86_64_PTE_MEMORY_TYPE_MASK (X86_64_PTE_WRITE_THROUGH \ 64*e276cc04SAlex Smith | X86_64_PTE_CACHING_DISABLED) 65*e276cc04SAlex Smith 66*e276cc04SAlex Smith 67*e276cc04SAlex Smith static const size_t k64BitPageTableRange = 0x200000L; 68*e276cc04SAlex Smith static const size_t k64BitPageDirectoryRange = 0x40000000L; 69*e276cc04SAlex Smith static const size_t k64BitPDPTRange = 0x8000000000L; 70*e276cc04SAlex Smith 71*e276cc04SAlex Smith static const size_t k64BitTableEntryCount = 512; 72*e276cc04SAlex Smith 73*e276cc04SAlex Smith 74*e276cc04SAlex Smith #define VADDR_TO_PML4E(va) (((va) & 0x0000fffffffff000L) / k64BitPDPTRange) 75*e276cc04SAlex Smith #define VADDR_TO_PDPTE(va) (((va) % k64BitPDPTRange) / k64BitPageDirectoryRange) 76*e276cc04SAlex Smith #define VADDR_TO_PDE(va) (((va) % k64BitPageDirectoryRange) / k64BitPageTableRange) 77*e276cc04SAlex Smith #define VADDR_TO_PTE(va) (((va) % k64BitPageTableRange) / B_PAGE_SIZE) 78*e276cc04SAlex Smith 79*e276cc04SAlex Smith 80*e276cc04SAlex Smith #endif // KERNEL_ARCH_X86_PAGING_64BIT_PAGING_H 81