1 /* 2 * Copyright 2018, Jérôme Duval, jerome.duval@gmail.com. 3 * Copyright 2002-2010, Axel Dörfler, axeld@pinc-software.de. 4 * Copyright 2013, Paweł Dziepak, pdziepak@quarnos.org. 5 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 6 * Distributed under the terms of the MIT License. 7 * 8 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 9 * Distributed under the terms of the NewOS License. 10 */ 11 12 13 #include <cpu.h> 14 15 #include <string.h> 16 #include <stdlib.h> 17 #include <stdio.h> 18 19 #include <algorithm> 20 21 #include <ACPI.h> 22 23 #include <boot_device.h> 24 #include <commpage.h> 25 #include <debug.h> 26 #include <elf.h> 27 #include <safemode.h> 28 #include <smp.h> 29 #include <util/BitUtils.h> 30 #include <vm/vm.h> 31 #include <vm/vm_types.h> 32 #include <vm/VMAddressSpace.h> 33 34 #include <arch_system_info.h> 35 #include <arch/x86/apic.h> 36 #include <boot/kernel_args.h> 37 38 #include "paging/X86PagingStructures.h" 39 #include "paging/X86VMTranslationMap.h" 40 41 42 #define DUMP_FEATURE_STRING 1 43 #define DUMP_CPU_TOPOLOGY 1 44 #define DUMP_CPU_PATCHLEVEL 1 45 46 47 /* cpu vendor info */ 48 struct cpu_vendor_info { 49 const char *vendor; 50 const char *ident_string[2]; 51 }; 52 53 static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = { 54 { "Intel", { "GenuineIntel" } }, 55 { "AMD", { "AuthenticAMD" } }, 56 { "Cyrix", { "CyrixInstead" } }, 57 { "UMC", { "UMC UMC UMC" } }, 58 { "NexGen", { "NexGenDriven" } }, 59 { "Centaur", { "CentaurHauls" } }, 60 { "Rise", { "RiseRiseRise" } }, 61 { "Transmeta", { "GenuineTMx86", "TransmetaCPU" } }, 62 { "NSC", { "Geode by NSC" } }, 63 { "Hygon", { "HygonGenuine" } }, 64 }; 65 66 #define K8_SMIONCMPHALT (1ULL << 27) 67 #define K8_C1EONCMPHALT (1ULL << 28) 68 69 #define K8_CMPHALT (K8_SMIONCMPHALT | K8_C1EONCMPHALT) 70 71 struct set_mtrr_parameter { 72 int32 index; 73 uint64 base; 74 uint64 length; 75 uint8 type; 76 }; 77 78 struct set_mtrrs_parameter { 79 const x86_mtrr_info* infos; 80 uint32 count; 81 uint8 defaultType; 82 }; 83 84 85 #ifdef __x86_64__ 86 extern addr_t _stac; 87 extern addr_t _clac; 88 extern addr_t _xsave; 89 extern addr_t _xsavec; 90 extern addr_t _xrstor; 91 uint64 gXsaveMask; 92 uint64 gFPUSaveLength = 512; 93 bool gHasXsave = false; 94 bool gHasXsavec = false; 95 #endif 96 97 extern "C" void x86_reboot(void); 98 // from arch.S 99 100 void (*gCpuIdleFunc)(void); 101 #ifndef __x86_64__ 102 void (*gX86SwapFPUFunc)(void* oldState, const void* newState) = x86_noop_swap; 103 bool gHasSSE = false; 104 #endif 105 106 static uint32 sCpuRendezvous; 107 static uint32 sCpuRendezvous2; 108 static uint32 sCpuRendezvous3; 109 static vint32 sTSCSyncRendezvous; 110 111 /* Some specials for the double fault handler */ 112 static uint8* sDoubleFaultStacks; 113 static const size_t kDoubleFaultStackSize = 4096; // size per CPU 114 115 static x86_cpu_module_info* sCpuModule; 116 117 118 /* CPU topology information */ 119 static uint32 (*sGetCPUTopologyID)(int currentCPU); 120 static uint32 sHierarchyMask[CPU_TOPOLOGY_LEVELS]; 121 static uint32 sHierarchyShift[CPU_TOPOLOGY_LEVELS]; 122 123 /* Cache topology information */ 124 static uint32 sCacheSharingMask[CPU_MAX_CACHE_LEVEL]; 125 126 static void* sUcodeData = NULL; 127 static size_t sUcodeDataSize = 0; 128 static struct intel_microcode_header* sLoadedUcodeUpdate; 129 static spinlock sUcodeUpdateLock = B_SPINLOCK_INITIALIZER; 130 131 132 static status_t 133 acpi_shutdown(bool rebootSystem) 134 { 135 if (debug_debugger_running() || !are_interrupts_enabled()) 136 return B_ERROR; 137 138 acpi_module_info* acpi; 139 if (get_module(B_ACPI_MODULE_NAME, (module_info**)&acpi) != B_OK) 140 return B_NOT_SUPPORTED; 141 142 status_t status; 143 if (rebootSystem) { 144 status = acpi->reboot(); 145 } else { 146 status = acpi->prepare_sleep_state(ACPI_POWER_STATE_OFF, NULL, 0); 147 if (status == B_OK) { 148 //cpu_status state = disable_interrupts(); 149 status = acpi->enter_sleep_state(ACPI_POWER_STATE_OFF); 150 //restore_interrupts(state); 151 } 152 } 153 154 put_module(B_ACPI_MODULE_NAME); 155 return status; 156 } 157 158 159 /*! Disable CPU caches, and invalidate them. */ 160 static void 161 disable_caches() 162 { 163 x86_write_cr0((x86_read_cr0() | CR0_CACHE_DISABLE) 164 & ~CR0_NOT_WRITE_THROUGH); 165 wbinvd(); 166 arch_cpu_global_TLB_invalidate(); 167 } 168 169 170 /*! Invalidate CPU caches, and enable them. */ 171 static void 172 enable_caches() 173 { 174 wbinvd(); 175 arch_cpu_global_TLB_invalidate(); 176 x86_write_cr0(x86_read_cr0() 177 & ~(CR0_CACHE_DISABLE | CR0_NOT_WRITE_THROUGH)); 178 } 179 180 181 static void 182 set_mtrr(void* _parameter, int cpu) 183 { 184 struct set_mtrr_parameter* parameter 185 = (struct set_mtrr_parameter*)_parameter; 186 187 // wait until all CPUs have arrived here 188 smp_cpu_rendezvous(&sCpuRendezvous); 189 190 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 191 // that initiated the call_all_cpus() from doing that again and clearing 192 // sCpuRendezvous2 before the last CPU has actually left the loop in 193 // smp_cpu_rendezvous(); 194 if (cpu == 0) 195 atomic_set((int32*)&sCpuRendezvous3, 0); 196 197 disable_caches(); 198 199 sCpuModule->set_mtrr(parameter->index, parameter->base, parameter->length, 200 parameter->type); 201 202 enable_caches(); 203 204 // wait until all CPUs have arrived here 205 smp_cpu_rendezvous(&sCpuRendezvous2); 206 smp_cpu_rendezvous(&sCpuRendezvous3); 207 } 208 209 210 static void 211 set_mtrrs(void* _parameter, int cpu) 212 { 213 set_mtrrs_parameter* parameter = (set_mtrrs_parameter*)_parameter; 214 215 // wait until all CPUs have arrived here 216 smp_cpu_rendezvous(&sCpuRendezvous); 217 218 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 219 // that initiated the call_all_cpus() from doing that again and clearing 220 // sCpuRendezvous2 before the last CPU has actually left the loop in 221 // smp_cpu_rendezvous(); 222 if (cpu == 0) 223 atomic_set((int32*)&sCpuRendezvous3, 0); 224 225 disable_caches(); 226 227 sCpuModule->set_mtrrs(parameter->defaultType, parameter->infos, 228 parameter->count); 229 230 enable_caches(); 231 232 // wait until all CPUs have arrived here 233 smp_cpu_rendezvous(&sCpuRendezvous2); 234 smp_cpu_rendezvous(&sCpuRendezvous3); 235 } 236 237 238 static void 239 init_mtrrs(void* _unused, int cpu) 240 { 241 // wait until all CPUs have arrived here 242 smp_cpu_rendezvous(&sCpuRendezvous); 243 244 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 245 // that initiated the call_all_cpus() from doing that again and clearing 246 // sCpuRendezvous2 before the last CPU has actually left the loop in 247 // smp_cpu_rendezvous(); 248 if (cpu == 0) 249 atomic_set((int32*)&sCpuRendezvous3, 0); 250 251 disable_caches(); 252 253 sCpuModule->init_mtrrs(); 254 255 enable_caches(); 256 257 // wait until all CPUs have arrived here 258 smp_cpu_rendezvous(&sCpuRendezvous2); 259 smp_cpu_rendezvous(&sCpuRendezvous3); 260 } 261 262 263 uint32 264 x86_count_mtrrs(void) 265 { 266 if (sCpuModule == NULL) 267 return 0; 268 269 return sCpuModule->count_mtrrs(); 270 } 271 272 273 void 274 x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type) 275 { 276 struct set_mtrr_parameter parameter; 277 parameter.index = index; 278 parameter.base = base; 279 parameter.length = length; 280 parameter.type = type; 281 282 sCpuRendezvous = sCpuRendezvous2 = 0; 283 call_all_cpus(&set_mtrr, ¶meter); 284 } 285 286 287 status_t 288 x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, uint8* _type) 289 { 290 // the MTRRs are identical on all CPUs, so it doesn't matter 291 // on which CPU this runs 292 return sCpuModule->get_mtrr(index, _base, _length, _type); 293 } 294 295 296 void 297 x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, uint32 count) 298 { 299 if (sCpuModule == NULL) 300 return; 301 302 struct set_mtrrs_parameter parameter; 303 parameter.defaultType = defaultType; 304 parameter.infos = infos; 305 parameter.count = count; 306 307 sCpuRendezvous = sCpuRendezvous2 = 0; 308 call_all_cpus(&set_mtrrs, ¶meter); 309 } 310 311 312 void 313 x86_init_fpu(void) 314 { 315 // All x86_64 CPUs support SSE, don't need to bother checking for it. 316 #ifndef __x86_64__ 317 if (!x86_check_feature(IA32_FEATURE_FPU, FEATURE_COMMON)) { 318 // No FPU... time to install one in your 386? 319 dprintf("%s: Warning: CPU has no reported FPU.\n", __func__); 320 gX86SwapFPUFunc = x86_noop_swap; 321 return; 322 } 323 324 if (!x86_check_feature(IA32_FEATURE_SSE, FEATURE_COMMON) 325 || !x86_check_feature(IA32_FEATURE_FXSR, FEATURE_COMMON)) { 326 dprintf("%s: CPU has no SSE... just enabling FPU.\n", __func__); 327 // we don't have proper SSE support, just enable FPU 328 x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU)); 329 gX86SwapFPUFunc = x86_fnsave_swap; 330 return; 331 } 332 #endif 333 334 dprintf("%s: CPU has SSE... enabling FXSR and XMM.\n", __func__); 335 #ifndef __x86_64__ 336 // enable OS support for SSE 337 x86_write_cr4(x86_read_cr4() | CR4_OS_FXSR | CR4_OS_XMM_EXCEPTION); 338 x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU)); 339 340 gX86SwapFPUFunc = x86_fxsave_swap; 341 gHasSSE = true; 342 #endif 343 } 344 345 346 #if DUMP_FEATURE_STRING 347 static void 348 dump_feature_string(int currentCPU, cpu_ent* cpu) 349 { 350 char features[512]; 351 features[0] = 0; 352 353 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FPU) 354 strlcat(features, "fpu ", sizeof(features)); 355 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_VME) 356 strlcat(features, "vme ", sizeof(features)); 357 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DE) 358 strlcat(features, "de ", sizeof(features)); 359 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE) 360 strlcat(features, "pse ", sizeof(features)); 361 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TSC) 362 strlcat(features, "tsc ", sizeof(features)); 363 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MSR) 364 strlcat(features, "msr ", sizeof(features)); 365 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAE) 366 strlcat(features, "pae ", sizeof(features)); 367 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCE) 368 strlcat(features, "mce ", sizeof(features)); 369 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CX8) 370 strlcat(features, "cx8 ", sizeof(features)); 371 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_APIC) 372 strlcat(features, "apic ", sizeof(features)); 373 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SEP) 374 strlcat(features, "sep ", sizeof(features)); 375 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MTRR) 376 strlcat(features, "mtrr ", sizeof(features)); 377 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PGE) 378 strlcat(features, "pge ", sizeof(features)); 379 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCA) 380 strlcat(features, "mca ", sizeof(features)); 381 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CMOV) 382 strlcat(features, "cmov ", sizeof(features)); 383 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAT) 384 strlcat(features, "pat ", sizeof(features)); 385 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE36) 386 strlcat(features, "pse36 ", sizeof(features)); 387 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSN) 388 strlcat(features, "psn ", sizeof(features)); 389 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CLFSH) 390 strlcat(features, "clfsh ", sizeof(features)); 391 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DS) 392 strlcat(features, "ds ", sizeof(features)); 393 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_ACPI) 394 strlcat(features, "acpi ", sizeof(features)); 395 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MMX) 396 strlcat(features, "mmx ", sizeof(features)); 397 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FXSR) 398 strlcat(features, "fxsr ", sizeof(features)); 399 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE) 400 strlcat(features, "sse ", sizeof(features)); 401 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE2) 402 strlcat(features, "sse2 ", sizeof(features)); 403 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SS) 404 strlcat(features, "ss ", sizeof(features)); 405 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_HTT) 406 strlcat(features, "htt ", sizeof(features)); 407 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TM) 408 strlcat(features, "tm ", sizeof(features)); 409 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PBE) 410 strlcat(features, "pbe ", sizeof(features)); 411 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE3) 412 strlcat(features, "sse3 ", sizeof(features)); 413 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCLMULQDQ) 414 strlcat(features, "pclmulqdq ", sizeof(features)); 415 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DTES64) 416 strlcat(features, "dtes64 ", sizeof(features)); 417 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MONITOR) 418 strlcat(features, "monitor ", sizeof(features)); 419 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DSCPL) 420 strlcat(features, "dscpl ", sizeof(features)); 421 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_VMX) 422 strlcat(features, "vmx ", sizeof(features)); 423 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SMX) 424 strlcat(features, "smx ", sizeof(features)); 425 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_EST) 426 strlcat(features, "est ", sizeof(features)); 427 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TM2) 428 strlcat(features, "tm2 ", sizeof(features)); 429 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSSE3) 430 strlcat(features, "ssse3 ", sizeof(features)); 431 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CNXTID) 432 strlcat(features, "cnxtid ", sizeof(features)); 433 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_FMA) 434 strlcat(features, "fma ", sizeof(features)); 435 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CX16) 436 strlcat(features, "cx16 ", sizeof(features)); 437 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XTPR) 438 strlcat(features, "xtpr ", sizeof(features)); 439 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PDCM) 440 strlcat(features, "pdcm ", sizeof(features)); 441 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCID) 442 strlcat(features, "pcid ", sizeof(features)); 443 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DCA) 444 strlcat(features, "dca ", sizeof(features)); 445 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_1) 446 strlcat(features, "sse4_1 ", sizeof(features)); 447 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_2) 448 strlcat(features, "sse4_2 ", sizeof(features)); 449 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_X2APIC) 450 strlcat(features, "x2apic ", sizeof(features)); 451 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MOVBE) 452 strlcat(features, "movbe ", sizeof(features)); 453 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_POPCNT) 454 strlcat(features, "popcnt ", sizeof(features)); 455 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TSCDEADLINE) 456 strlcat(features, "tscdeadline ", sizeof(features)); 457 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AES) 458 strlcat(features, "aes ", sizeof(features)); 459 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XSAVE) 460 strlcat(features, "xsave ", sizeof(features)); 461 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_OSXSAVE) 462 strlcat(features, "osxsave ", sizeof(features)); 463 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AVX) 464 strlcat(features, "avx ", sizeof(features)); 465 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_F16C) 466 strlcat(features, "f16c ", sizeof(features)); 467 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_RDRND) 468 strlcat(features, "rdrnd ", sizeof(features)); 469 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) 470 strlcat(features, "hypervisor ", sizeof(features)); 471 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_SYSCALL) 472 strlcat(features, "syscall ", sizeof(features)); 473 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_NX) 474 strlcat(features, "nx ", sizeof(features)); 475 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_MMXEXT) 476 strlcat(features, "mmxext ", sizeof(features)); 477 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_FFXSR) 478 strlcat(features, "ffxsr ", sizeof(features)); 479 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_PDPE1GB) 480 strlcat(features, "pdpe1gb ", sizeof(features)); 481 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_LONG) 482 strlcat(features, "long ", sizeof(features)); 483 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOWEXT) 484 strlcat(features, "3dnowext ", sizeof(features)); 485 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOW) 486 strlcat(features, "3dnow ", sizeof(features)); 487 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_DTS) 488 strlcat(features, "dts ", sizeof(features)); 489 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ITB) 490 strlcat(features, "itb ", sizeof(features)); 491 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ARAT) 492 strlcat(features, "arat ", sizeof(features)); 493 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PLN) 494 strlcat(features, "pln ", sizeof(features)); 495 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ECMD) 496 strlcat(features, "ecmd ", sizeof(features)); 497 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PTM) 498 strlcat(features, "ptm ", sizeof(features)); 499 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP) 500 strlcat(features, "hwp ", sizeof(features)); 501 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_NOTIFY) 502 strlcat(features, "hwp_notify ", sizeof(features)); 503 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_ACTWIN) 504 strlcat(features, "hwp_actwin ", sizeof(features)); 505 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_EPP) 506 strlcat(features, "hwp_epp ", sizeof(features)); 507 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PLR) 508 strlcat(features, "hwp_plr ", sizeof(features)); 509 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HDC) 510 strlcat(features, "hdc ", sizeof(features)); 511 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_TBMT3) 512 strlcat(features, "tbmt3 ", sizeof(features)); 513 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_CAP) 514 strlcat(features, "hwp_cap ", sizeof(features)); 515 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PECI) 516 strlcat(features, "hwp_peci ", sizeof(features)); 517 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FLEX) 518 strlcat(features, "hwp_flex ", sizeof(features)); 519 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FAST) 520 strlcat(features, "hwp_fast ", sizeof(features)); 521 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HW_FEEDBACK) 522 strlcat(features, "hw_feedback ", sizeof(features)); 523 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_IGNIDL) 524 strlcat(features, "hwp_ignidl ", sizeof(features)); 525 if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_APERFMPERF) 526 strlcat(features, "aperfmperf ", sizeof(features)); 527 if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_EPB) 528 strlcat(features, "epb ", sizeof(features)); 529 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_TSC_ADJUST) 530 strlcat(features, "tsc_adjust ", sizeof(features)); 531 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SGX) 532 strlcat(features, "sgx ", sizeof(features)); 533 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI1) 534 strlcat(features, "bmi1 ", sizeof(features)); 535 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_HLE) 536 strlcat(features, "hle ", sizeof(features)); 537 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX2) 538 strlcat(features, "avx2 ", sizeof(features)); 539 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMEP) 540 strlcat(features, "smep ", sizeof(features)); 541 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI2) 542 strlcat(features, "bmi2 ", sizeof(features)); 543 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ERMS) 544 strlcat(features, "erms ", sizeof(features)); 545 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INVPCID) 546 strlcat(features, "invpcid ", sizeof(features)); 547 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RTM) 548 strlcat(features, "rtm ", sizeof(features)); 549 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CQM) 550 strlcat(features, "cqm ", sizeof(features)); 551 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_MPX) 552 strlcat(features, "mpx ", sizeof(features)); 553 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDT_A) 554 strlcat(features, "rdt_a ", sizeof(features)); 555 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512F) 556 strlcat(features, "avx512f ", sizeof(features)); 557 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512DQ) 558 strlcat(features, "avx512dq ", sizeof(features)); 559 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDSEED) 560 strlcat(features, "rdseed ", sizeof(features)); 561 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ADX) 562 strlcat(features, "adx ", sizeof(features)); 563 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMAP) 564 strlcat(features, "smap ", sizeof(features)); 565 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512IFMA) 566 strlcat(features, "avx512ifma ", sizeof(features)); 567 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_PCOMMIT) 568 strlcat(features, "pcommit ", sizeof(features)); 569 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLFLUSHOPT) 570 strlcat(features, "cflushopt ", sizeof(features)); 571 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLWB) 572 strlcat(features, "clwb ", sizeof(features)); 573 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INTEL_PT) 574 strlcat(features, "intel_pt ", sizeof(features)); 575 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512PF) 576 strlcat(features, "avx512pf ", sizeof(features)); 577 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512ER) 578 strlcat(features, "avx512er ", sizeof(features)); 579 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512CD) 580 strlcat(features, "avx512cd ", sizeof(features)); 581 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SHA_NI) 582 strlcat(features, "sha_ni ", sizeof(features)); 583 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512BW) 584 strlcat(features, "avx512bw ", sizeof(features)); 585 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512VI) 586 strlcat(features, "avx512vi ", sizeof(features)); 587 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI) 588 strlcat(features, "avx512vmbi ", sizeof(features)); 589 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_UMIP) 590 strlcat(features, "umip ", sizeof(features)); 591 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_PKU) 592 strlcat(features, "pku ", sizeof(features)); 593 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_OSPKE) 594 strlcat(features, "ospke ", sizeof(features)); 595 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI2) 596 strlcat(features, "avx512vmbi2 ", sizeof(features)); 597 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_GFNI) 598 strlcat(features, "gfni ", sizeof(features)); 599 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VAES) 600 strlcat(features, "vaes ", sizeof(features)); 601 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VPCLMULQDQ) 602 strlcat(features, "vpclmulqdq ", sizeof(features)); 603 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VNNI) 604 strlcat(features, "avx512vnni ", sizeof(features)); 605 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_BITALG) 606 strlcat(features, "avx512bitalg ", sizeof(features)); 607 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VPOPCNTDQ) 608 strlcat(features, "avx512vpopcntdq ", sizeof(features)); 609 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_LA57) 610 strlcat(features, "la57 ", sizeof(features)); 611 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_RDPID) 612 strlcat(features, "rdpid ", sizeof(features)); 613 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_SGX_LC) 614 strlcat(features, "sgx_lc ", sizeof(features)); 615 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_IBRS) 616 strlcat(features, "ibrs ", sizeof(features)); 617 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_STIBP) 618 strlcat(features, "stibp ", sizeof(features)); 619 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_L1D_FLUSH) 620 strlcat(features, "l1d_flush ", sizeof(features)); 621 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_ARCH_CAPABILITIES) 622 strlcat(features, "msr_arch ", sizeof(features)); 623 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_SSBD) 624 strlcat(features, "ssbd ", sizeof(features)); 625 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEOPT) 626 strlcat(features, "xsaveopt ", sizeof(features)); 627 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEC) 628 strlcat(features, "xsavec ", sizeof(features)); 629 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XGETBV1) 630 strlcat(features, "xgetbv1 ", sizeof(features)); 631 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVES) 632 strlcat(features, "xsaves ", sizeof(features)); 633 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_CLZERO) 634 strlcat(features, "clzero ", sizeof(features)); 635 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_IBPB) 636 strlcat(features, "ibpb ", sizeof(features)); 637 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSBD) 638 strlcat(features, "amd_ssbd ", sizeof(features)); 639 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_VIRT_SSBD) 640 strlcat(features, "virt_ssbd ", sizeof(features)); 641 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSB_NO) 642 strlcat(features, "amd_ssb_no ", sizeof(features)); 643 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_CPPC) 644 strlcat(features, "cppc ", sizeof(features)); 645 dprintf("CPU %d: features: %s\n", currentCPU, features); 646 } 647 #endif // DUMP_FEATURE_STRING 648 649 650 static void 651 compute_cpu_hierarchy_masks(int maxLogicalID, int maxCoreID) 652 { 653 ASSERT(maxLogicalID >= maxCoreID); 654 const int kMaxSMTID = maxLogicalID / maxCoreID; 655 656 sHierarchyMask[CPU_TOPOLOGY_SMT] = kMaxSMTID - 1; 657 sHierarchyShift[CPU_TOPOLOGY_SMT] = 0; 658 659 sHierarchyMask[CPU_TOPOLOGY_CORE] = (maxCoreID - 1) * kMaxSMTID; 660 sHierarchyShift[CPU_TOPOLOGY_CORE] 661 = count_set_bits(sHierarchyMask[CPU_TOPOLOGY_SMT]); 662 663 const uint32 kSinglePackageMask = sHierarchyMask[CPU_TOPOLOGY_SMT] 664 | sHierarchyMask[CPU_TOPOLOGY_CORE]; 665 sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~kSinglePackageMask; 666 sHierarchyShift[CPU_TOPOLOGY_PACKAGE] = count_set_bits(kSinglePackageMask); 667 } 668 669 670 static uint32 671 get_cpu_legacy_initial_apic_id(int /* currentCPU */) 672 { 673 cpuid_info cpuid; 674 get_current_cpuid(&cpuid, 1, 0); 675 return cpuid.regs.ebx >> 24; 676 } 677 678 679 static inline status_t 680 detect_amd_cpu_topology(uint32 maxBasicLeaf, uint32 maxExtendedLeaf) 681 { 682 sGetCPUTopologyID = get_cpu_legacy_initial_apic_id; 683 684 cpuid_info cpuid; 685 get_current_cpuid(&cpuid, 1, 0); 686 int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff); 687 688 int maxCoreID = 1; 689 if (maxExtendedLeaf >= 0x80000008) { 690 get_current_cpuid(&cpuid, 0x80000008, 0); 691 maxCoreID = (cpuid.regs.ecx >> 12) & 0xf; 692 if (maxCoreID != 0) 693 maxCoreID = 1 << maxCoreID; 694 else 695 maxCoreID = next_power_of_2((cpuid.regs.edx & 0xf) + 1); 696 } 697 698 if (maxExtendedLeaf >= 0x80000001) { 699 get_current_cpuid(&cpuid, 0x80000001, 0); 700 if (x86_check_feature(IA32_FEATURE_AMD_EXT_CMPLEGACY, 701 FEATURE_EXT_AMD_ECX)) 702 maxCoreID = maxLogicalID; 703 } 704 705 compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID); 706 707 return B_OK; 708 } 709 710 711 static void 712 detect_amd_cache_topology(uint32 maxExtendedLeaf) 713 { 714 if (!x86_check_feature(IA32_FEATURE_AMD_EXT_TOPOLOGY, FEATURE_EXT_AMD_ECX)) 715 return; 716 717 if (maxExtendedLeaf < 0x8000001d) 718 return; 719 720 uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL]; 721 int maxCacheLevel = 0; 722 723 int currentLevel = 0; 724 int cacheType; 725 do { 726 cpuid_info cpuid; 727 get_current_cpuid(&cpuid, 0x8000001d, currentLevel); 728 729 cacheType = cpuid.regs.eax & 0x1f; 730 if (cacheType == 0) 731 break; 732 733 int cacheLevel = (cpuid.regs.eax >> 5) & 0x7; 734 int coresCount = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1); 735 hierarchyLevels[cacheLevel - 1] 736 = coresCount * (sHierarchyMask[CPU_TOPOLOGY_SMT] + 1); 737 maxCacheLevel = std::max(maxCacheLevel, cacheLevel); 738 739 currentLevel++; 740 } while (true); 741 742 for (int i = 0; i < maxCacheLevel; i++) 743 sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1); 744 gCPUCacheLevelCount = maxCacheLevel; 745 } 746 747 748 static uint32 749 get_intel_cpu_initial_x2apic_id(int /* currentCPU */) 750 { 751 cpuid_info cpuid; 752 get_current_cpuid(&cpuid, 11, 0); 753 return cpuid.regs.edx; 754 } 755 756 757 static inline status_t 758 detect_intel_cpu_topology_x2apic(uint32 maxBasicLeaf) 759 { 760 761 uint32 leaf = 0; 762 cpuid_info cpuid; 763 if (maxBasicLeaf >= 0x1f) { 764 get_current_cpuid(&cpuid, 0x1f, 0); 765 if (cpuid.regs.ebx != 0) 766 leaf = 0x1f; 767 } 768 if (maxBasicLeaf >= 0xb && leaf == 0) { 769 get_current_cpuid(&cpuid, 0xb, 0); 770 if (cpuid.regs.ebx != 0) 771 leaf = 0xb; 772 } 773 if (leaf == 0) 774 return B_UNSUPPORTED; 775 776 uint8 hierarchyLevels[CPU_TOPOLOGY_LEVELS] = { 0 }; 777 778 int currentLevel = 0; 779 unsigned int levelsSet = 0; 780 do { 781 cpuid_info cpuid; 782 get_current_cpuid(&cpuid, leaf, currentLevel++); 783 int levelType = (cpuid.regs.ecx >> 8) & 0xff; 784 int levelValue = cpuid.regs.eax & 0x1f; 785 786 if (levelType == 0) 787 break; 788 789 switch (levelType) { 790 case 1: // SMT 791 hierarchyLevels[CPU_TOPOLOGY_SMT] = levelValue; 792 levelsSet |= 1; 793 break; 794 case 2: // core 795 hierarchyLevels[CPU_TOPOLOGY_CORE] = levelValue; 796 levelsSet |= 2; 797 break; 798 } 799 800 } while (levelsSet != 3); 801 802 sGetCPUTopologyID = get_intel_cpu_initial_x2apic_id; 803 804 for (int i = 1; i < CPU_TOPOLOGY_LEVELS; i++) { 805 if ((levelsSet & (1u << i)) != 0) 806 continue; 807 hierarchyLevels[i] = hierarchyLevels[i - 1]; 808 } 809 810 for (int i = 0; i < CPU_TOPOLOGY_LEVELS; i++) { 811 uint32 mask = ~uint32(0); 812 if (i < CPU_TOPOLOGY_LEVELS - 1) 813 mask = (1u << hierarchyLevels[i]) - 1; 814 if (i > 0) 815 mask &= ~sHierarchyMask[i - 1]; 816 sHierarchyMask[i] = mask; 817 sHierarchyShift[i] = i > 0 ? hierarchyLevels[i - 1] : 0; 818 } 819 820 return B_OK; 821 } 822 823 824 static inline status_t 825 detect_intel_cpu_topology_legacy(uint32 maxBasicLeaf) 826 { 827 sGetCPUTopologyID = get_cpu_legacy_initial_apic_id; 828 829 cpuid_info cpuid; 830 831 get_current_cpuid(&cpuid, 1, 0); 832 int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff); 833 834 int maxCoreID = 1; 835 if (maxBasicLeaf >= 4) { 836 get_current_cpuid(&cpuid, 4, 0); 837 maxCoreID = next_power_of_2((cpuid.regs.eax >> 26) + 1); 838 } 839 840 compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID); 841 842 return B_OK; 843 } 844 845 846 static void 847 detect_intel_cache_topology(uint32 maxBasicLeaf) 848 { 849 if (maxBasicLeaf < 4) 850 return; 851 852 uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL]; 853 int maxCacheLevel = 0; 854 855 int currentLevel = 0; 856 int cacheType; 857 do { 858 cpuid_info cpuid; 859 get_current_cpuid(&cpuid, 4, currentLevel); 860 861 cacheType = cpuid.regs.eax & 0x1f; 862 if (cacheType == 0) 863 break; 864 865 int cacheLevel = (cpuid.regs.eax >> 5) & 0x7; 866 hierarchyLevels[cacheLevel - 1] 867 = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1); 868 maxCacheLevel = std::max(maxCacheLevel, cacheLevel); 869 870 currentLevel++; 871 } while (true); 872 873 for (int i = 0; i < maxCacheLevel; i++) 874 sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1); 875 876 gCPUCacheLevelCount = maxCacheLevel; 877 } 878 879 880 static uint32 881 get_simple_cpu_topology_id(int currentCPU) 882 { 883 return currentCPU; 884 } 885 886 887 static inline int 888 get_topology_level_id(uint32 id, cpu_topology_level level) 889 { 890 ASSERT(level < CPU_TOPOLOGY_LEVELS); 891 return (id & sHierarchyMask[level]) >> sHierarchyShift[level]; 892 } 893 894 895 static void 896 detect_cpu_topology(int currentCPU, cpu_ent* cpu, uint32 maxBasicLeaf, 897 uint32 maxExtendedLeaf) 898 { 899 if (currentCPU == 0) { 900 memset(sCacheSharingMask, 0xff, sizeof(sCacheSharingMask)); 901 902 status_t result = B_UNSUPPORTED; 903 if (x86_check_feature(IA32_FEATURE_HTT, FEATURE_COMMON)) { 904 if (cpu->arch.vendor == VENDOR_AMD 905 || cpu->arch.vendor == VENDOR_HYGON) { 906 result = detect_amd_cpu_topology(maxBasicLeaf, maxExtendedLeaf); 907 908 if (result == B_OK) 909 detect_amd_cache_topology(maxExtendedLeaf); 910 } 911 912 if (cpu->arch.vendor == VENDOR_INTEL) { 913 result = detect_intel_cpu_topology_x2apic(maxBasicLeaf); 914 if (result != B_OK) 915 result = detect_intel_cpu_topology_legacy(maxBasicLeaf); 916 917 if (result == B_OK) 918 detect_intel_cache_topology(maxBasicLeaf); 919 } 920 } 921 922 if (result != B_OK) { 923 dprintf("No CPU topology information available.\n"); 924 925 sGetCPUTopologyID = get_simple_cpu_topology_id; 926 927 sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~uint32(0); 928 } 929 } 930 931 ASSERT(sGetCPUTopologyID != NULL); 932 int topologyID = sGetCPUTopologyID(currentCPU); 933 cpu->topology_id[CPU_TOPOLOGY_SMT] 934 = get_topology_level_id(topologyID, CPU_TOPOLOGY_SMT); 935 cpu->topology_id[CPU_TOPOLOGY_CORE] 936 = get_topology_level_id(topologyID, CPU_TOPOLOGY_CORE); 937 cpu->topology_id[CPU_TOPOLOGY_PACKAGE] 938 = get_topology_level_id(topologyID, CPU_TOPOLOGY_PACKAGE); 939 940 unsigned int i; 941 for (i = 0; i < gCPUCacheLevelCount; i++) 942 cpu->cache_id[i] = topologyID & sCacheSharingMask[i]; 943 for (; i < CPU_MAX_CACHE_LEVEL; i++) 944 cpu->cache_id[i] = -1; 945 946 #if DUMP_CPU_TOPOLOGY 947 dprintf("CPU %d: apic id %d, package %d, core %d, smt %d\n", currentCPU, 948 topologyID, cpu->topology_id[CPU_TOPOLOGY_PACKAGE], 949 cpu->topology_id[CPU_TOPOLOGY_CORE], 950 cpu->topology_id[CPU_TOPOLOGY_SMT]); 951 952 if (gCPUCacheLevelCount > 0) { 953 char cacheLevels[256]; 954 unsigned int offset = 0; 955 for (i = 0; i < gCPUCacheLevelCount; i++) { 956 offset += snprintf(cacheLevels + offset, 957 sizeof(cacheLevels) - offset, 958 " L%d id %d%s", i + 1, cpu->cache_id[i], 959 i < gCPUCacheLevelCount - 1 ? "," : ""); 960 961 if (offset >= sizeof(cacheLevels)) 962 break; 963 } 964 965 dprintf("CPU %d: cache sharing:%s\n", currentCPU, cacheLevels); 966 } 967 #endif 968 } 969 970 971 static void 972 detect_intel_patch_level(cpu_ent* cpu) 973 { 974 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) { 975 cpu->arch.patch_level = 0; 976 return; 977 } 978 979 x86_write_msr(IA32_MSR_UCODE_REV, 0); 980 cpuid_info cpuid; 981 get_current_cpuid(&cpuid, 1, 0); 982 983 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV); 984 cpu->arch.patch_level = value >> 32; 985 } 986 987 988 static void 989 detect_amd_patch_level(cpu_ent* cpu) 990 { 991 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) { 992 cpu->arch.patch_level = 0; 993 return; 994 } 995 996 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV); 997 cpu->arch.patch_level = value >> 32; 998 } 999 1000 1001 static struct intel_microcode_header* 1002 find_microcode_intel(addr_t data, size_t size, uint32 patchLevel) 1003 { 1004 // 9.11.3 Processor Identification 1005 cpuid_info cpuid; 1006 get_current_cpuid(&cpuid, 1, 0); 1007 uint32 signature = cpuid.regs.eax; 1008 // 9.11.4 Platform Identification 1009 uint64 platformBits = (x86_read_msr(IA32_MSR_PLATFORM_ID) >> 50) & 0x7; 1010 uint64 mask = 1 << platformBits; 1011 1012 while (size > 0) { 1013 if (size < sizeof(struct intel_microcode_header)) { 1014 dprintf("find_microcode_intel update is too small for header\n"); 1015 break; 1016 } 1017 struct intel_microcode_header* header = 1018 (struct intel_microcode_header*)data; 1019 1020 uint32 totalSize = header->total_size; 1021 uint32 dataSize = header->data_size; 1022 if (dataSize == 0) { 1023 dataSize = 2000; 1024 totalSize = sizeof(struct intel_microcode_header) 1025 + dataSize; 1026 } 1027 if (totalSize > size) { 1028 dprintf("find_microcode_intel update is too small for data\n"); 1029 break; 1030 } 1031 1032 uint32* dwords = (uint32*)data; 1033 // prepare the next update 1034 size -= totalSize; 1035 data += totalSize; 1036 1037 if (header->loader_revision != 1) { 1038 dprintf("find_microcode_intel incorrect loader version\n"); 1039 continue; 1040 } 1041 // 9.11.6 The microcode update data requires a 16-byte boundary 1042 // alignment. 1043 if (((addr_t)header % 16) != 0) { 1044 dprintf("find_microcode_intel incorrect alignment\n"); 1045 continue; 1046 } 1047 uint32 sum = 0; 1048 for (uint32 i = 0; i < totalSize / 4; i++) { 1049 sum += dwords[i]; 1050 } 1051 if (sum != 0) { 1052 dprintf("find_microcode_intel incorrect checksum\n"); 1053 continue; 1054 } 1055 if (patchLevel > header->update_revision) { 1056 dprintf("find_microcode_intel update_revision is lower\n"); 1057 continue; 1058 } 1059 if (signature == header->processor_signature 1060 && (mask & header->processor_flags) != 0) { 1061 return header; 1062 } 1063 if (totalSize <= (sizeof(struct intel_microcode_header) + dataSize 1064 + sizeof(struct intel_microcode_extended_signature_header))) { 1065 continue; 1066 } 1067 struct intel_microcode_extended_signature_header* extSigHeader = 1068 (struct intel_microcode_extended_signature_header*)((addr_t)header 1069 + sizeof(struct intel_microcode_header) + dataSize); 1070 struct intel_microcode_extended_signature* extended_signature = 1071 (struct intel_microcode_extended_signature*)((addr_t)extSigHeader 1072 + sizeof(struct intel_microcode_extended_signature_header)); 1073 for (uint32 i = 0; i < extSigHeader->extended_signature_count; i++) { 1074 if (signature == extended_signature[i].processor_signature 1075 && (mask & extended_signature[i].processor_flags) != 0) 1076 return header; 1077 } 1078 } 1079 return NULL; 1080 } 1081 1082 1083 static void 1084 load_microcode_intel(int currentCPU, cpu_ent* cpu) 1085 { 1086 // serialize for HT cores 1087 if (currentCPU != 0) 1088 acquire_spinlock(&sUcodeUpdateLock); 1089 detect_intel_patch_level(cpu); 1090 uint32 revision = cpu->arch.patch_level; 1091 struct intel_microcode_header* update = sLoadedUcodeUpdate; 1092 if (update == NULL) { 1093 update = find_microcode_intel((addr_t)sUcodeData, sUcodeDataSize, 1094 revision); 1095 } 1096 if (update != NULL) { 1097 addr_t data = (addr_t)update + sizeof(struct intel_microcode_header); 1098 wbinvd(); 1099 x86_write_msr(IA32_MSR_UCODE_WRITE, data); 1100 detect_intel_patch_level(cpu); 1101 if (revision == cpu->arch.patch_level) { 1102 dprintf("CPU %d: update failed\n", currentCPU); 1103 } else { 1104 if (sLoadedUcodeUpdate == NULL) 1105 sLoadedUcodeUpdate = update; 1106 dprintf("CPU %d: updated from revision %" B_PRIu32 " to %" B_PRIu32 1107 "\n", currentCPU, revision, cpu->arch.patch_level); 1108 } 1109 } else { 1110 dprintf("CPU %d: no update found\n", currentCPU); 1111 } 1112 if (currentCPU != 0) 1113 release_spinlock(&sUcodeUpdateLock); 1114 } 1115 1116 1117 static void 1118 load_microcode_amd(int currentCPU, cpu_ent* cpu) 1119 { 1120 dprintf("CPU %d: no update found\n", currentCPU); 1121 } 1122 1123 1124 static void 1125 load_microcode(int currentCPU) 1126 { 1127 if (sUcodeData == NULL) 1128 return; 1129 cpu_ent* cpu = get_cpu_struct(); 1130 if ((cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) != 0) 1131 return; 1132 if (cpu->arch.vendor == VENDOR_INTEL) 1133 load_microcode_intel(currentCPU, cpu); 1134 else if (cpu->arch.vendor == VENDOR_AMD) 1135 load_microcode_amd(currentCPU, cpu); 1136 } 1137 1138 1139 static void 1140 detect_cpu(int currentCPU) 1141 { 1142 cpu_ent* cpu = get_cpu_struct(); 1143 char vendorString[17]; 1144 cpuid_info cpuid; 1145 1146 // clear out the cpu info data 1147 cpu->arch.vendor = VENDOR_UNKNOWN; 1148 cpu->arch.vendor_name = "UNKNOWN VENDOR"; 1149 cpu->arch.feature[FEATURE_COMMON] = 0; 1150 cpu->arch.feature[FEATURE_EXT] = 0; 1151 cpu->arch.feature[FEATURE_EXT_AMD] = 0; 1152 cpu->arch.feature[FEATURE_7_EBX] = 0; 1153 cpu->arch.feature[FEATURE_7_ECX] = 0; 1154 cpu->arch.feature[FEATURE_7_EDX] = 0; 1155 cpu->arch.feature[FEATURE_D_1_EAX] = 0; 1156 cpu->arch.model_name[0] = 0; 1157 1158 // print some fun data 1159 get_current_cpuid(&cpuid, 0, 0); 1160 uint32 maxBasicLeaf = cpuid.eax_0.max_eax; 1161 1162 // build the vendor string 1163 memset(vendorString, 0, sizeof(vendorString)); 1164 memcpy(vendorString, cpuid.eax_0.vendor_id, sizeof(cpuid.eax_0.vendor_id)); 1165 1166 // get the family, model, stepping 1167 get_current_cpuid(&cpuid, 1, 0); 1168 cpu->arch.type = cpuid.eax_1.type; 1169 cpu->arch.family = cpuid.eax_1.family; 1170 cpu->arch.extended_family = cpuid.eax_1.extended_family; 1171 cpu->arch.model = cpuid.eax_1.model; 1172 cpu->arch.extended_model = cpuid.eax_1.extended_model; 1173 cpu->arch.stepping = cpuid.eax_1.stepping; 1174 dprintf("CPU %d: type %d family %d extended_family %d model %d " 1175 "extended_model %d stepping %d, string '%s'\n", 1176 currentCPU, cpu->arch.type, cpu->arch.family, 1177 cpu->arch.extended_family, cpu->arch.model, 1178 cpu->arch.extended_model, cpu->arch.stepping, vendorString); 1179 1180 // figure out what vendor we have here 1181 1182 for (int32 i = 0; i < VENDOR_NUM; i++) { 1183 if (vendor_info[i].ident_string[0] 1184 && !strcmp(vendorString, vendor_info[i].ident_string[0])) { 1185 cpu->arch.vendor = (x86_vendors)i; 1186 cpu->arch.vendor_name = vendor_info[i].vendor; 1187 break; 1188 } 1189 if (vendor_info[i].ident_string[1] 1190 && !strcmp(vendorString, vendor_info[i].ident_string[1])) { 1191 cpu->arch.vendor = (x86_vendors)i; 1192 cpu->arch.vendor_name = vendor_info[i].vendor; 1193 break; 1194 } 1195 } 1196 1197 // see if we can get the model name 1198 get_current_cpuid(&cpuid, 0x80000000, 0); 1199 uint32 maxExtendedLeaf = cpuid.eax_0.max_eax; 1200 if (maxExtendedLeaf >= 0x80000004) { 1201 // build the model string (need to swap ecx/edx data before copying) 1202 unsigned int temp; 1203 memset(cpu->arch.model_name, 0, sizeof(cpu->arch.model_name)); 1204 1205 get_current_cpuid(&cpuid, 0x80000002, 0); 1206 temp = cpuid.regs.edx; 1207 cpuid.regs.edx = cpuid.regs.ecx; 1208 cpuid.regs.ecx = temp; 1209 memcpy(cpu->arch.model_name, cpuid.as_chars, sizeof(cpuid.as_chars)); 1210 1211 get_current_cpuid(&cpuid, 0x80000003, 0); 1212 temp = cpuid.regs.edx; 1213 cpuid.regs.edx = cpuid.regs.ecx; 1214 cpuid.regs.ecx = temp; 1215 memcpy(cpu->arch.model_name + 16, cpuid.as_chars, 1216 sizeof(cpuid.as_chars)); 1217 1218 get_current_cpuid(&cpuid, 0x80000004, 0); 1219 temp = cpuid.regs.edx; 1220 cpuid.regs.edx = cpuid.regs.ecx; 1221 cpuid.regs.ecx = temp; 1222 memcpy(cpu->arch.model_name + 32, cpuid.as_chars, 1223 sizeof(cpuid.as_chars)); 1224 1225 // some cpus return a right-justified string 1226 int32 i = 0; 1227 while (cpu->arch.model_name[i] == ' ') 1228 i++; 1229 if (i > 0) { 1230 memmove(cpu->arch.model_name, &cpu->arch.model_name[i], 1231 strlen(&cpu->arch.model_name[i]) + 1); 1232 } 1233 1234 dprintf("CPU %d: vendor '%s' model name '%s'\n", 1235 currentCPU, cpu->arch.vendor_name, cpu->arch.model_name); 1236 } else { 1237 strlcpy(cpu->arch.model_name, "unknown", sizeof(cpu->arch.model_name)); 1238 } 1239 1240 // load feature bits 1241 get_current_cpuid(&cpuid, 1, 0); 1242 cpu->arch.feature[FEATURE_COMMON] = cpuid.eax_1.features; // edx 1243 cpu->arch.feature[FEATURE_EXT] = cpuid.eax_1.extended_features; // ecx 1244 1245 if (maxExtendedLeaf >= 0x80000001) { 1246 get_current_cpuid(&cpuid, 0x80000001, 0); 1247 if (cpu->arch.vendor == VENDOR_AMD) 1248 cpu->arch.feature[FEATURE_EXT_AMD_ECX] = cpuid.regs.ecx; // ecx 1249 cpu->arch.feature[FEATURE_EXT_AMD] = cpuid.regs.edx; // edx 1250 if (cpu->arch.vendor != VENDOR_AMD) 1251 cpu->arch.feature[FEATURE_EXT_AMD] &= IA32_FEATURES_INTEL_EXT; 1252 } 1253 1254 if (maxBasicLeaf >= 5) { 1255 get_current_cpuid(&cpuid, 5, 0); 1256 cpu->arch.feature[FEATURE_5_ECX] = cpuid.regs.ecx; 1257 } 1258 1259 if (maxBasicLeaf >= 6) { 1260 get_current_cpuid(&cpuid, 6, 0); 1261 cpu->arch.feature[FEATURE_6_EAX] = cpuid.regs.eax; 1262 cpu->arch.feature[FEATURE_6_ECX] = cpuid.regs.ecx; 1263 } 1264 1265 if (maxBasicLeaf >= 7) { 1266 get_current_cpuid(&cpuid, 7, 0); 1267 cpu->arch.feature[FEATURE_7_EBX] = cpuid.regs.ebx; 1268 cpu->arch.feature[FEATURE_7_ECX] = cpuid.regs.ecx; 1269 cpu->arch.feature[FEATURE_7_EDX] = cpuid.regs.edx; 1270 } 1271 1272 if (maxBasicLeaf >= 0xd) { 1273 get_current_cpuid(&cpuid, 0xd, 1); 1274 cpu->arch.feature[FEATURE_D_1_EAX] = cpuid.regs.eax; 1275 } 1276 1277 if (maxExtendedLeaf >= 0x80000007) { 1278 get_current_cpuid(&cpuid, 0x80000007, 0); 1279 cpu->arch.feature[FEATURE_EXT_7_EDX] = cpuid.regs.edx; 1280 } 1281 1282 if (maxExtendedLeaf >= 0x80000008) { 1283 get_current_cpuid(&cpuid, 0x80000008, 0); 1284 cpu->arch.feature[FEATURE_EXT_8_EBX] = cpuid.regs.ebx; 1285 } 1286 1287 detect_cpu_topology(currentCPU, cpu, maxBasicLeaf, maxExtendedLeaf); 1288 1289 if (cpu->arch.vendor == VENDOR_INTEL) 1290 detect_intel_patch_level(cpu); 1291 else if (cpu->arch.vendor == VENDOR_AMD) 1292 detect_amd_patch_level(cpu); 1293 1294 #if DUMP_FEATURE_STRING 1295 dump_feature_string(currentCPU, cpu); 1296 #endif 1297 #if DUMP_CPU_PATCHLEVEL 1298 dprintf("CPU %d: patch_level %" B_PRIu32 "\n", currentCPU, 1299 cpu->arch.patch_level); 1300 #endif 1301 } 1302 1303 1304 bool 1305 x86_check_feature(uint32 feature, enum x86_feature_type type) 1306 { 1307 cpu_ent* cpu = get_cpu_struct(); 1308 1309 #if 0 1310 int i; 1311 dprintf("x86_check_feature: feature 0x%x, type %d\n", feature, type); 1312 for (i = 0; i < FEATURE_NUM; i++) { 1313 dprintf("features %d: 0x%x\n", i, cpu->arch.feature[i]); 1314 } 1315 #endif 1316 1317 return (cpu->arch.feature[type] & feature) != 0; 1318 } 1319 1320 1321 void* 1322 x86_get_double_fault_stack(int32 cpu, size_t* _size) 1323 { 1324 *_size = kDoubleFaultStackSize; 1325 return sDoubleFaultStacks + kDoubleFaultStackSize * cpu; 1326 } 1327 1328 1329 /*! Returns the index of the current CPU. Can only be called from the double 1330 fault handler. 1331 */ 1332 int32 1333 x86_double_fault_get_cpu(void) 1334 { 1335 addr_t stack = x86_get_stack_frame(); 1336 return (stack - (addr_t)sDoubleFaultStacks) / kDoubleFaultStackSize; 1337 } 1338 1339 1340 // #pragma mark - 1341 1342 1343 status_t 1344 arch_cpu_preboot_init_percpu(kernel_args* args, int cpu) 1345 { 1346 // On SMP system we want to synchronize the CPUs' TSCs, so system_time() 1347 // will return consistent values. 1348 if (smp_get_num_cpus() > 1) { 1349 // let the first CPU prepare the rendezvous point 1350 if (cpu == 0) 1351 sTSCSyncRendezvous = smp_get_num_cpus() - 1; 1352 1353 // One CPU after the other will drop out of this loop and be caught by 1354 // the loop below, until the last CPU (0) gets there. Save for +/- a few 1355 // cycles the CPUs should pass the second loop at the same time. 1356 while (sTSCSyncRendezvous != cpu) { 1357 } 1358 1359 sTSCSyncRendezvous = cpu - 1; 1360 1361 while (sTSCSyncRendezvous != -1) { 1362 } 1363 1364 // reset TSC to 0 1365 x86_write_msr(IA32_MSR_TSC, 0); 1366 } 1367 1368 x86_descriptors_preboot_init_percpu(args, cpu); 1369 1370 return B_OK; 1371 } 1372 1373 1374 static void 1375 halt_idle(void) 1376 { 1377 asm("hlt"); 1378 } 1379 1380 1381 static void 1382 amdc1e_noarat_idle(void) 1383 { 1384 uint64 msr = x86_read_msr(K8_MSR_IPM); 1385 if (msr & K8_CMPHALT) 1386 x86_write_msr(K8_MSR_IPM, msr & ~K8_CMPHALT); 1387 halt_idle(); 1388 } 1389 1390 1391 static bool 1392 detect_amdc1e_noarat() 1393 { 1394 cpu_ent* cpu = get_cpu_struct(); 1395 1396 if (cpu->arch.vendor != VENDOR_AMD) 1397 return false; 1398 1399 // Family 0x12 and higher processors support ARAT 1400 // Family lower than 0xf processors doesn't support C1E 1401 // Family 0xf with model <= 0x40 procssors doesn't support C1E 1402 uint32 family = cpu->arch.family + cpu->arch.extended_family; 1403 uint32 model = (cpu->arch.extended_model << 4) | cpu->arch.model; 1404 return (family < 0x12 && family > 0xf) || (family == 0xf && model > 0x40); 1405 } 1406 1407 1408 static void 1409 init_tsc_with_cpuid(kernel_args* args, uint32* conversionFactor) 1410 { 1411 cpu_ent* cpu = get_cpu_struct(); 1412 if (cpu->arch.vendor != VENDOR_INTEL) 1413 return; 1414 uint32 model = (cpu->arch.extended_model << 4) | cpu->arch.model; 1415 cpuid_info cpuid; 1416 get_current_cpuid(&cpuid, 0, 0); 1417 uint32 maxBasicLeaf = cpuid.eax_0.max_eax; 1418 if (maxBasicLeaf < 0x15) 1419 return; 1420 1421 get_current_cpuid(&cpuid, 0x15, 0); 1422 if (cpuid.regs.eax == 0 || cpuid.regs.ebx == 0) 1423 return; 1424 uint32 khz = cpuid.regs.ecx / 1000; 1425 uint32 denominator = cpuid.regs.eax; 1426 uint32 numerator = cpuid.regs.ebx; 1427 if (khz == 0 && model == 0x5f) { 1428 // CPUID 0x16 isn't supported, hardcoding 1429 khz = 25000; 1430 } 1431 1432 if (khz == 0 && maxBasicLeaf >= 0x16) { 1433 // for these CPUs the base frequency is also the tsc frequency 1434 get_current_cpuid(&cpuid, 0x16, 0); 1435 khz = cpuid.regs.eax * 1000 * denominator / numerator; 1436 } 1437 if (khz == 0) 1438 return; 1439 dprintf("CPU: using TSC frequency from CPUID\n"); 1440 // compute for microseconds as follows (1000000 << 32) / (tsc freq in Hz), 1441 // or (1000 << 32) / (tsc freq in kHz) 1442 *conversionFactor = (1000ULL << 32) / (khz * numerator / denominator); 1443 // overwrite the bootloader value 1444 args->arch_args.system_time_cv_factor = *conversionFactor; 1445 } 1446 1447 1448 static void 1449 init_tsc_with_msr(kernel_args* args, uint32* conversionFactor) 1450 { 1451 cpu_ent* cpuEnt = get_cpu_struct(); 1452 if (cpuEnt->arch.vendor != VENDOR_AMD) 1453 return; 1454 uint32 family = cpuEnt->arch.family + cpuEnt->arch.extended_family; 1455 if (family < 0x10) 1456 return; 1457 uint64 value = x86_read_msr(MSR_F10H_HWCR); 1458 if ((value & HWCR_TSCFREQSEL) == 0) 1459 return; 1460 1461 value = x86_read_msr(MSR_F10H_PSTATEDEF(0)); 1462 if ((value & PSTATEDEF_EN) == 0) 1463 return; 1464 if (family != 0x17 && family != 0x19) 1465 return; 1466 1467 uint64 khz = 200 * 1000; 1468 uint32 denominator = (value >> 8) & 0x3f; 1469 if (denominator < 0x8 || denominator > 0x2c) 1470 return; 1471 if (denominator > 0x1a && (denominator % 2) == 1) 1472 return; 1473 uint32 numerator = value & 0xff; 1474 if (numerator < 0x10) 1475 return; 1476 1477 dprintf("CPU: using TSC frequency from MSR %" B_PRIu64 "\n", khz * numerator / denominator); 1478 // compute for microseconds as follows (1000000 << 32) / (tsc freq in Hz), 1479 // or (1000 << 32) / (tsc freq in kHz) 1480 *conversionFactor = (1000ULL << 32) / (khz * numerator / denominator); 1481 // overwrite the bootloader value 1482 args->arch_args.system_time_cv_factor = *conversionFactor; 1483 } 1484 1485 1486 static void 1487 init_tsc(kernel_args* args) 1488 { 1489 // init the TSC -> system_time() conversion factors 1490 1491 // try to find the TSC frequency with CPUID 1492 uint32 conversionFactor = args->arch_args.system_time_cv_factor; 1493 init_tsc_with_cpuid(args, &conversionFactor); 1494 init_tsc_with_msr(args, &conversionFactor); 1495 uint64 conversionFactorNsecs = (uint64)conversionFactor * 1000; 1496 1497 1498 #ifdef __x86_64__ 1499 // The x86_64 system_time() implementation uses 64-bit multiplication and 1500 // therefore shifting is not necessary for low frequencies (it's also not 1501 // too likely that there'll be any x86_64 CPUs clocked under 1GHz). 1502 __x86_setup_system_time((uint64)conversionFactor << 32, 1503 conversionFactorNsecs); 1504 #else 1505 if (conversionFactorNsecs >> 32 != 0) { 1506 // the TSC frequency is < 1 GHz, which forces us to shift the factor 1507 __x86_setup_system_time(conversionFactor, conversionFactorNsecs >> 16, 1508 true); 1509 } else { 1510 // the TSC frequency is >= 1 GHz 1511 __x86_setup_system_time(conversionFactor, conversionFactorNsecs, false); 1512 } 1513 #endif 1514 } 1515 1516 1517 status_t 1518 arch_cpu_init_percpu(kernel_args* args, int cpu) 1519 { 1520 load_microcode(cpu); 1521 detect_cpu(cpu); 1522 1523 if (cpu == 0) 1524 init_tsc(args); 1525 1526 if (!gCpuIdleFunc) { 1527 if (detect_amdc1e_noarat()) 1528 gCpuIdleFunc = amdc1e_noarat_idle; 1529 else 1530 gCpuIdleFunc = halt_idle; 1531 } 1532 1533 if (x86_check_feature(IA32_FEATURE_MCE, FEATURE_COMMON)) 1534 x86_write_cr4(x86_read_cr4() | IA32_CR4_MCE); 1535 1536 #ifdef __x86_64__ 1537 // if RDTSCP is available write cpu number in TSC_AUX 1538 if (x86_check_feature(IA32_FEATURE_AMD_EXT_RDTSCP, FEATURE_EXT_AMD)) 1539 x86_write_msr(IA32_MSR_TSC_AUX, cpu); 1540 1541 // make LFENCE a dispatch serializing instruction on AMD 64bit 1542 cpu_ent* cpuEnt = get_cpu_struct(); 1543 if (cpuEnt->arch.vendor == VENDOR_AMD) { 1544 uint32 family = cpuEnt->arch.family + cpuEnt->arch.extended_family; 1545 if (family >= 0x10 && family != 0x11) { 1546 uint64 value = x86_read_msr(MSR_F10H_DE_CFG); 1547 if ((value & DE_CFG_SERIALIZE_LFENCE) == 0) 1548 x86_write_msr(MSR_F10H_DE_CFG, value | DE_CFG_SERIALIZE_LFENCE); 1549 } 1550 } 1551 #endif 1552 1553 if (x86_check_feature(IA32_FEATURE_APERFMPERF, FEATURE_6_ECX)) { 1554 gCPU[cpu].arch.mperf_prev = x86_read_msr(IA32_MSR_MPERF); 1555 gCPU[cpu].arch.aperf_prev = x86_read_msr(IA32_MSR_APERF); 1556 gCPU[cpu].arch.frequency = 0; 1557 gCPU[cpu].arch.perf_timestamp = 0; 1558 } 1559 return __x86_patch_errata_percpu(cpu); 1560 } 1561 1562 1563 status_t 1564 arch_cpu_init(kernel_args* args) 1565 { 1566 if (args->ucode_data != NULL 1567 && args->ucode_data_size > 0) { 1568 sUcodeData = args->ucode_data; 1569 sUcodeDataSize = args->ucode_data_size; 1570 } else { 1571 dprintf("CPU: no microcode provided\n"); 1572 } 1573 1574 // Initialize descriptor tables. 1575 x86_descriptors_init(args); 1576 1577 return B_OK; 1578 } 1579 1580 1581 #ifdef __x86_64__ 1582 static void 1583 enable_smap(void* dummy, int cpu) 1584 { 1585 x86_write_cr4(x86_read_cr4() | IA32_CR4_SMAP); 1586 } 1587 1588 1589 static void 1590 enable_smep(void* dummy, int cpu) 1591 { 1592 x86_write_cr4(x86_read_cr4() | IA32_CR4_SMEP); 1593 } 1594 1595 1596 static void 1597 enable_osxsave(void* dummy, int cpu) 1598 { 1599 x86_write_cr4(x86_read_cr4() | IA32_CR4_OSXSAVE); 1600 } 1601 1602 1603 static void 1604 enable_xsavemask(void* dummy, int cpu) 1605 { 1606 xsetbv(0, gXsaveMask); 1607 } 1608 #endif 1609 1610 1611 status_t 1612 arch_cpu_init_post_vm(kernel_args* args) 1613 { 1614 uint32 i; 1615 1616 // allocate an area for the double fault stacks 1617 virtual_address_restrictions virtualRestrictions = {}; 1618 virtualRestrictions.address_specification = B_ANY_KERNEL_ADDRESS; 1619 physical_address_restrictions physicalRestrictions = {}; 1620 create_area_etc(B_SYSTEM_TEAM, "double fault stacks", 1621 kDoubleFaultStackSize * smp_get_num_cpus(), B_FULL_LOCK, 1622 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, CREATE_AREA_DONT_WAIT, 0, 1623 &virtualRestrictions, &physicalRestrictions, 1624 (void**)&sDoubleFaultStacks); 1625 1626 X86PagingStructures* kernelPagingStructures 1627 = static_cast<X86VMTranslationMap*>( 1628 VMAddressSpace::Kernel()->TranslationMap())->PagingStructures(); 1629 1630 // Set active translation map on each CPU. 1631 for (i = 0; i < args->num_cpus; i++) { 1632 gCPU[i].arch.active_paging_structures = kernelPagingStructures; 1633 kernelPagingStructures->AddReference(); 1634 } 1635 1636 if (!apic_available()) 1637 x86_init_fpu(); 1638 // else fpu gets set up in smp code 1639 1640 #ifdef __x86_64__ 1641 // if available enable SMEP (Supervisor Memory Execution Protection) 1642 if (x86_check_feature(IA32_FEATURE_SMEP, FEATURE_7_EBX)) { 1643 if (!get_safemode_boolean(B_SAFEMODE_DISABLE_SMEP_SMAP, false)) { 1644 dprintf("enable SMEP\n"); 1645 call_all_cpus_sync(&enable_smep, NULL); 1646 } else 1647 dprintf("SMEP disabled per safemode setting\n"); 1648 } 1649 1650 // if available enable SMAP (Supervisor Memory Access Protection) 1651 if (x86_check_feature(IA32_FEATURE_SMAP, FEATURE_7_EBX)) { 1652 if (!get_safemode_boolean(B_SAFEMODE_DISABLE_SMEP_SMAP, false)) { 1653 dprintf("enable SMAP\n"); 1654 call_all_cpus_sync(&enable_smap, NULL); 1655 1656 arch_altcodepatch_replace(ALTCODEPATCH_TAG_STAC, &_stac, 3); 1657 arch_altcodepatch_replace(ALTCODEPATCH_TAG_CLAC, &_clac, 3); 1658 } else 1659 dprintf("SMAP disabled per safemode setting\n"); 1660 } 1661 1662 // if available enable XSAVE (XSAVE and extended states) 1663 gHasXsave = x86_check_feature(IA32_FEATURE_EXT_XSAVE, FEATURE_EXT); 1664 if (gHasXsave) { 1665 gHasXsavec = x86_check_feature(IA32_FEATURE_XSAVEC, 1666 FEATURE_D_1_EAX); 1667 1668 call_all_cpus_sync(&enable_osxsave, NULL); 1669 gXsaveMask = IA32_XCR0_X87 | IA32_XCR0_SSE; 1670 cpuid_info cpuid; 1671 get_current_cpuid(&cpuid, 0xd, 0); 1672 gXsaveMask |= (cpuid.regs.eax & IA32_XCR0_AVX); 1673 call_all_cpus_sync(&enable_xsavemask, NULL); 1674 get_current_cpuid(&cpuid, 0xd, 0); 1675 gFPUSaveLength = cpuid.regs.ebx; 1676 if (gFPUSaveLength > sizeof(((struct arch_thread *)0)->fpu_state)) 1677 gFPUSaveLength = 832; 1678 1679 arch_altcodepatch_replace(ALTCODEPATCH_TAG_XSAVE, 1680 gHasXsavec ? &_xsavec : &_xsave, 4); 1681 arch_altcodepatch_replace(ALTCODEPATCH_TAG_XRSTOR, 1682 &_xrstor, 4); 1683 1684 dprintf("enable %s 0x%" B_PRIx64 " %" B_PRId64 "\n", 1685 gHasXsavec ? "XSAVEC" : "XSAVE", gXsaveMask, gFPUSaveLength); 1686 } 1687 1688 #endif 1689 1690 return B_OK; 1691 } 1692 1693 1694 status_t 1695 arch_cpu_init_post_modules(kernel_args* args) 1696 { 1697 // initialize CPU module 1698 1699 void* cookie = open_module_list("cpu"); 1700 1701 while (true) { 1702 char name[B_FILE_NAME_LENGTH]; 1703 size_t nameLength = sizeof(name); 1704 1705 if (read_next_module_name(cookie, name, &nameLength) != B_OK 1706 || get_module(name, (module_info**)&sCpuModule) == B_OK) 1707 break; 1708 } 1709 1710 close_module_list(cookie); 1711 1712 // initialize MTRRs if available 1713 if (x86_count_mtrrs() > 0) { 1714 sCpuRendezvous = sCpuRendezvous2 = 0; 1715 call_all_cpus(&init_mtrrs, NULL); 1716 } 1717 1718 size_t threadExitLen = (addr_t)x86_end_userspace_thread_exit 1719 - (addr_t)x86_userspace_thread_exit; 1720 addr_t threadExitPosition = fill_commpage_entry( 1721 COMMPAGE_ENTRY_X86_THREAD_EXIT, (const void*)x86_userspace_thread_exit, 1722 threadExitLen); 1723 1724 // add the functions to the commpage image 1725 image_id image = get_commpage_image(); 1726 1727 elf_add_memory_image_symbol(image, "commpage_thread_exit", 1728 threadExitPosition, threadExitLen, B_SYMBOL_TYPE_TEXT); 1729 1730 return B_OK; 1731 } 1732 1733 1734 void 1735 arch_cpu_user_TLB_invalidate(void) 1736 { 1737 x86_write_cr3(x86_read_cr3()); 1738 } 1739 1740 1741 void 1742 arch_cpu_global_TLB_invalidate(void) 1743 { 1744 uint32 flags = x86_read_cr4(); 1745 1746 if (flags & IA32_CR4_GLOBAL_PAGES) { 1747 // disable and reenable the global pages to flush all TLBs regardless 1748 // of the global page bit 1749 x86_write_cr4(flags & ~IA32_CR4_GLOBAL_PAGES); 1750 x86_write_cr4(flags | IA32_CR4_GLOBAL_PAGES); 1751 } else { 1752 cpu_status state = disable_interrupts(); 1753 arch_cpu_user_TLB_invalidate(); 1754 restore_interrupts(state); 1755 } 1756 } 1757 1758 1759 void 1760 arch_cpu_invalidate_TLB_range(addr_t start, addr_t end) 1761 { 1762 int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE; 1763 while (num_pages-- >= 0) { 1764 invalidate_TLB(start); 1765 start += B_PAGE_SIZE; 1766 } 1767 } 1768 1769 1770 void 1771 arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages) 1772 { 1773 int i; 1774 for (i = 0; i < num_pages; i++) { 1775 invalidate_TLB(pages[i]); 1776 } 1777 } 1778 1779 1780 status_t 1781 arch_cpu_shutdown(bool rebootSystem) 1782 { 1783 if (acpi_shutdown(rebootSystem) == B_OK) 1784 return B_OK; 1785 1786 if (!rebootSystem) { 1787 #ifndef __x86_64__ 1788 return apm_shutdown(); 1789 #else 1790 return B_NOT_SUPPORTED; 1791 #endif 1792 } 1793 1794 cpu_status state = disable_interrupts(); 1795 1796 // try to reset the system using the keyboard controller 1797 out8(0xfe, 0x64); 1798 1799 // Give some time to the controller to do its job (0.5s) 1800 snooze(500000); 1801 1802 // if that didn't help, try it this way 1803 x86_reboot(); 1804 1805 restore_interrupts(state); 1806 return B_ERROR; 1807 } 1808 1809 1810 void 1811 arch_cpu_sync_icache(void* address, size_t length) 1812 { 1813 // instruction cache is always consistent on x86 1814 } 1815 1816