1 /* 2 * Copyright 2018, Jérôme Duval, jerome.duval@gmail.com. 3 * Copyright 2002-2010, Axel Dörfler, axeld@pinc-software.de. 4 * Copyright 2013, Paweł Dziepak, pdziepak@quarnos.org. 5 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 6 * Distributed under the terms of the MIT License. 7 * 8 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 9 * Distributed under the terms of the NewOS License. 10 */ 11 12 13 #include <cpu.h> 14 15 #include <string.h> 16 #include <stdlib.h> 17 #include <stdio.h> 18 19 #include <algorithm> 20 21 #include <ACPI.h> 22 23 #include <boot_device.h> 24 #include <commpage.h> 25 #include <debug.h> 26 #include <elf.h> 27 #include <safemode.h> 28 #include <smp.h> 29 #include <util/BitUtils.h> 30 #include <vm/vm.h> 31 #include <vm/vm_types.h> 32 #include <vm/VMAddressSpace.h> 33 34 #include <arch_system_info.h> 35 #include <arch/x86/apic.h> 36 #include <boot/kernel_args.h> 37 38 #include "paging/X86PagingStructures.h" 39 #include "paging/X86VMTranslationMap.h" 40 41 42 #define DUMP_FEATURE_STRING 1 43 #define DUMP_CPU_TOPOLOGY 1 44 #define DUMP_CPU_PATCHLEVEL 1 45 46 47 /* cpu vendor info */ 48 struct cpu_vendor_info { 49 const char *vendor; 50 const char *ident_string[2]; 51 }; 52 53 static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = { 54 { "Intel", { "GenuineIntel" } }, 55 { "AMD", { "AuthenticAMD" } }, 56 { "Cyrix", { "CyrixInstead" } }, 57 { "UMC", { "UMC UMC UMC" } }, 58 { "NexGen", { "NexGenDriven" } }, 59 { "Centaur", { "CentaurHauls" } }, 60 { "Rise", { "RiseRiseRise" } }, 61 { "Transmeta", { "GenuineTMx86", "TransmetaCPU" } }, 62 { "NSC", { "Geode by NSC" } }, 63 { "Hygon", { "HygonGenuine" } }, 64 }; 65 66 #define K8_SMIONCMPHALT (1ULL << 27) 67 #define K8_C1EONCMPHALT (1ULL << 28) 68 69 #define K8_CMPHALT (K8_SMIONCMPHALT | K8_C1EONCMPHALT) 70 71 struct set_mtrr_parameter { 72 int32 index; 73 uint64 base; 74 uint64 length; 75 uint8 type; 76 }; 77 78 struct set_mtrrs_parameter { 79 const x86_mtrr_info* infos; 80 uint32 count; 81 uint8 defaultType; 82 }; 83 84 85 #ifdef __x86_64__ 86 extern addr_t _stac; 87 extern addr_t _clac; 88 extern addr_t _xsave; 89 extern addr_t _xsavec; 90 extern addr_t _xrstor; 91 uint64 gXsaveMask; 92 uint64 gFPUSaveLength = 512; 93 bool gHasXsave = false; 94 bool gHasXsavec = false; 95 #endif 96 97 extern "C" void x86_reboot(void); 98 // from arch.S 99 100 void (*gCpuIdleFunc)(void); 101 #ifndef __x86_64__ 102 void (*gX86SwapFPUFunc)(void* oldState, const void* newState) = x86_noop_swap; 103 bool gHasSSE = false; 104 #endif 105 106 static uint32 sCpuRendezvous; 107 static uint32 sCpuRendezvous2; 108 static uint32 sCpuRendezvous3; 109 static vint32 sTSCSyncRendezvous; 110 111 /* Some specials for the double fault handler */ 112 static uint8* sDoubleFaultStacks; 113 static const size_t kDoubleFaultStackSize = 4096; // size per CPU 114 115 static x86_cpu_module_info* sCpuModule; 116 117 118 /* CPU topology information */ 119 static uint32 (*sGetCPUTopologyID)(int currentCPU); 120 static uint32 sHierarchyMask[CPU_TOPOLOGY_LEVELS]; 121 static uint32 sHierarchyShift[CPU_TOPOLOGY_LEVELS]; 122 123 /* Cache topology information */ 124 static uint32 sCacheSharingMask[CPU_MAX_CACHE_LEVEL]; 125 126 static void* sUcodeData = NULL; 127 static size_t sUcodeDataSize = 0; 128 static struct intel_microcode_header* sLoadedUcodeUpdate; 129 static spinlock sUcodeUpdateLock = B_SPINLOCK_INITIALIZER; 130 131 132 static status_t 133 acpi_shutdown(bool rebootSystem) 134 { 135 if (debug_debugger_running() || !are_interrupts_enabled()) 136 return B_ERROR; 137 138 acpi_module_info* acpi; 139 if (get_module(B_ACPI_MODULE_NAME, (module_info**)&acpi) != B_OK) 140 return B_NOT_SUPPORTED; 141 142 status_t status; 143 if (rebootSystem) { 144 status = acpi->reboot(); 145 } else { 146 status = acpi->prepare_sleep_state(ACPI_POWER_STATE_OFF, NULL, 0); 147 if (status == B_OK) { 148 //cpu_status state = disable_interrupts(); 149 status = acpi->enter_sleep_state(ACPI_POWER_STATE_OFF); 150 //restore_interrupts(state); 151 } 152 } 153 154 put_module(B_ACPI_MODULE_NAME); 155 return status; 156 } 157 158 159 /*! Disable CPU caches, and invalidate them. */ 160 static void 161 disable_caches() 162 { 163 x86_write_cr0((x86_read_cr0() | CR0_CACHE_DISABLE) 164 & ~CR0_NOT_WRITE_THROUGH); 165 wbinvd(); 166 arch_cpu_global_TLB_invalidate(); 167 } 168 169 170 /*! Invalidate CPU caches, and enable them. */ 171 static void 172 enable_caches() 173 { 174 wbinvd(); 175 arch_cpu_global_TLB_invalidate(); 176 x86_write_cr0(x86_read_cr0() 177 & ~(CR0_CACHE_DISABLE | CR0_NOT_WRITE_THROUGH)); 178 } 179 180 181 static void 182 set_mtrr(void* _parameter, int cpu) 183 { 184 struct set_mtrr_parameter* parameter 185 = (struct set_mtrr_parameter*)_parameter; 186 187 // wait until all CPUs have arrived here 188 smp_cpu_rendezvous(&sCpuRendezvous); 189 190 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 191 // that initiated the call_all_cpus() from doing that again and clearing 192 // sCpuRendezvous2 before the last CPU has actually left the loop in 193 // smp_cpu_rendezvous(); 194 if (cpu == 0) 195 atomic_set((int32*)&sCpuRendezvous3, 0); 196 197 disable_caches(); 198 199 sCpuModule->set_mtrr(parameter->index, parameter->base, parameter->length, 200 parameter->type); 201 202 enable_caches(); 203 204 // wait until all CPUs have arrived here 205 smp_cpu_rendezvous(&sCpuRendezvous2); 206 smp_cpu_rendezvous(&sCpuRendezvous3); 207 } 208 209 210 static void 211 set_mtrrs(void* _parameter, int cpu) 212 { 213 set_mtrrs_parameter* parameter = (set_mtrrs_parameter*)_parameter; 214 215 // wait until all CPUs have arrived here 216 smp_cpu_rendezvous(&sCpuRendezvous); 217 218 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 219 // that initiated the call_all_cpus() from doing that again and clearing 220 // sCpuRendezvous2 before the last CPU has actually left the loop in 221 // smp_cpu_rendezvous(); 222 if (cpu == 0) 223 atomic_set((int32*)&sCpuRendezvous3, 0); 224 225 disable_caches(); 226 227 sCpuModule->set_mtrrs(parameter->defaultType, parameter->infos, 228 parameter->count); 229 230 enable_caches(); 231 232 // wait until all CPUs have arrived here 233 smp_cpu_rendezvous(&sCpuRendezvous2); 234 smp_cpu_rendezvous(&sCpuRendezvous3); 235 } 236 237 238 static void 239 init_mtrrs(void* _unused, int cpu) 240 { 241 // wait until all CPUs have arrived here 242 smp_cpu_rendezvous(&sCpuRendezvous); 243 244 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 245 // that initiated the call_all_cpus() from doing that again and clearing 246 // sCpuRendezvous2 before the last CPU has actually left the loop in 247 // smp_cpu_rendezvous(); 248 if (cpu == 0) 249 atomic_set((int32*)&sCpuRendezvous3, 0); 250 251 disable_caches(); 252 253 sCpuModule->init_mtrrs(); 254 255 enable_caches(); 256 257 // wait until all CPUs have arrived here 258 smp_cpu_rendezvous(&sCpuRendezvous2); 259 smp_cpu_rendezvous(&sCpuRendezvous3); 260 } 261 262 263 uint32 264 x86_count_mtrrs(void) 265 { 266 if (sCpuModule == NULL) 267 return 0; 268 269 return sCpuModule->count_mtrrs(); 270 } 271 272 273 void 274 x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type) 275 { 276 struct set_mtrr_parameter parameter; 277 parameter.index = index; 278 parameter.base = base; 279 parameter.length = length; 280 parameter.type = type; 281 282 sCpuRendezvous = sCpuRendezvous2 = 0; 283 call_all_cpus(&set_mtrr, ¶meter); 284 } 285 286 287 status_t 288 x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, uint8* _type) 289 { 290 // the MTRRs are identical on all CPUs, so it doesn't matter 291 // on which CPU this runs 292 return sCpuModule->get_mtrr(index, _base, _length, _type); 293 } 294 295 296 void 297 x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, uint32 count) 298 { 299 if (sCpuModule == NULL) 300 return; 301 302 struct set_mtrrs_parameter parameter; 303 parameter.defaultType = defaultType; 304 parameter.infos = infos; 305 parameter.count = count; 306 307 sCpuRendezvous = sCpuRendezvous2 = 0; 308 call_all_cpus(&set_mtrrs, ¶meter); 309 } 310 311 312 void 313 x86_init_fpu(void) 314 { 315 // All x86_64 CPUs support SSE, don't need to bother checking for it. 316 #ifndef __x86_64__ 317 if (!x86_check_feature(IA32_FEATURE_FPU, FEATURE_COMMON)) { 318 // No FPU... time to install one in your 386? 319 dprintf("%s: Warning: CPU has no reported FPU.\n", __func__); 320 gX86SwapFPUFunc = x86_noop_swap; 321 return; 322 } 323 324 if (!x86_check_feature(IA32_FEATURE_SSE, FEATURE_COMMON) 325 || !x86_check_feature(IA32_FEATURE_FXSR, FEATURE_COMMON)) { 326 dprintf("%s: CPU has no SSE... just enabling FPU.\n", __func__); 327 // we don't have proper SSE support, just enable FPU 328 x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU)); 329 gX86SwapFPUFunc = x86_fnsave_swap; 330 return; 331 } 332 #endif 333 334 dprintf("%s: CPU has SSE... enabling FXSR and XMM.\n", __func__); 335 #ifndef __x86_64__ 336 // enable OS support for SSE 337 x86_write_cr4(x86_read_cr4() | CR4_OS_FXSR | CR4_OS_XMM_EXCEPTION); 338 x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU)); 339 340 gX86SwapFPUFunc = x86_fxsave_swap; 341 gHasSSE = true; 342 #endif 343 } 344 345 346 #if DUMP_FEATURE_STRING 347 static void 348 dump_feature_string(int currentCPU, cpu_ent* cpu) 349 { 350 char features[512]; 351 features[0] = 0; 352 353 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FPU) 354 strlcat(features, "fpu ", sizeof(features)); 355 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_VME) 356 strlcat(features, "vme ", sizeof(features)); 357 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DE) 358 strlcat(features, "de ", sizeof(features)); 359 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE) 360 strlcat(features, "pse ", sizeof(features)); 361 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TSC) 362 strlcat(features, "tsc ", sizeof(features)); 363 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MSR) 364 strlcat(features, "msr ", sizeof(features)); 365 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAE) 366 strlcat(features, "pae ", sizeof(features)); 367 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCE) 368 strlcat(features, "mce ", sizeof(features)); 369 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CX8) 370 strlcat(features, "cx8 ", sizeof(features)); 371 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_APIC) 372 strlcat(features, "apic ", sizeof(features)); 373 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SEP) 374 strlcat(features, "sep ", sizeof(features)); 375 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MTRR) 376 strlcat(features, "mtrr ", sizeof(features)); 377 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PGE) 378 strlcat(features, "pge ", sizeof(features)); 379 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCA) 380 strlcat(features, "mca ", sizeof(features)); 381 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CMOV) 382 strlcat(features, "cmov ", sizeof(features)); 383 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAT) 384 strlcat(features, "pat ", sizeof(features)); 385 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE36) 386 strlcat(features, "pse36 ", sizeof(features)); 387 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSN) 388 strlcat(features, "psn ", sizeof(features)); 389 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CLFSH) 390 strlcat(features, "clfsh ", sizeof(features)); 391 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DS) 392 strlcat(features, "ds ", sizeof(features)); 393 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_ACPI) 394 strlcat(features, "acpi ", sizeof(features)); 395 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MMX) 396 strlcat(features, "mmx ", sizeof(features)); 397 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FXSR) 398 strlcat(features, "fxsr ", sizeof(features)); 399 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE) 400 strlcat(features, "sse ", sizeof(features)); 401 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE2) 402 strlcat(features, "sse2 ", sizeof(features)); 403 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SS) 404 strlcat(features, "ss ", sizeof(features)); 405 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_HTT) 406 strlcat(features, "htt ", sizeof(features)); 407 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TM) 408 strlcat(features, "tm ", sizeof(features)); 409 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PBE) 410 strlcat(features, "pbe ", sizeof(features)); 411 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE3) 412 strlcat(features, "sse3 ", sizeof(features)); 413 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCLMULQDQ) 414 strlcat(features, "pclmulqdq ", sizeof(features)); 415 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DTES64) 416 strlcat(features, "dtes64 ", sizeof(features)); 417 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MONITOR) 418 strlcat(features, "monitor ", sizeof(features)); 419 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DSCPL) 420 strlcat(features, "dscpl ", sizeof(features)); 421 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_VMX) 422 strlcat(features, "vmx ", sizeof(features)); 423 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SMX) 424 strlcat(features, "smx ", sizeof(features)); 425 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_EST) 426 strlcat(features, "est ", sizeof(features)); 427 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TM2) 428 strlcat(features, "tm2 ", sizeof(features)); 429 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSSE3) 430 strlcat(features, "ssse3 ", sizeof(features)); 431 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CNXTID) 432 strlcat(features, "cnxtid ", sizeof(features)); 433 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_FMA) 434 strlcat(features, "fma ", sizeof(features)); 435 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CX16) 436 strlcat(features, "cx16 ", sizeof(features)); 437 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XTPR) 438 strlcat(features, "xtpr ", sizeof(features)); 439 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PDCM) 440 strlcat(features, "pdcm ", sizeof(features)); 441 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCID) 442 strlcat(features, "pcid ", sizeof(features)); 443 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DCA) 444 strlcat(features, "dca ", sizeof(features)); 445 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_1) 446 strlcat(features, "sse4_1 ", sizeof(features)); 447 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_2) 448 strlcat(features, "sse4_2 ", sizeof(features)); 449 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_X2APIC) 450 strlcat(features, "x2apic ", sizeof(features)); 451 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MOVBE) 452 strlcat(features, "movbe ", sizeof(features)); 453 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_POPCNT) 454 strlcat(features, "popcnt ", sizeof(features)); 455 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TSCDEADLINE) 456 strlcat(features, "tscdeadline ", sizeof(features)); 457 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AES) 458 strlcat(features, "aes ", sizeof(features)); 459 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XSAVE) 460 strlcat(features, "xsave ", sizeof(features)); 461 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_OSXSAVE) 462 strlcat(features, "osxsave ", sizeof(features)); 463 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AVX) 464 strlcat(features, "avx ", sizeof(features)); 465 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_F16C) 466 strlcat(features, "f16c ", sizeof(features)); 467 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_RDRND) 468 strlcat(features, "rdrnd ", sizeof(features)); 469 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) 470 strlcat(features, "hypervisor ", sizeof(features)); 471 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_SYSCALL) 472 strlcat(features, "syscall ", sizeof(features)); 473 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_NX) 474 strlcat(features, "nx ", sizeof(features)); 475 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_MMXEXT) 476 strlcat(features, "mmxext ", sizeof(features)); 477 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_FFXSR) 478 strlcat(features, "ffxsr ", sizeof(features)); 479 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_PDPE1GB) 480 strlcat(features, "pdpe1gb ", sizeof(features)); 481 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_LONG) 482 strlcat(features, "long ", sizeof(features)); 483 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOWEXT) 484 strlcat(features, "3dnowext ", sizeof(features)); 485 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOW) 486 strlcat(features, "3dnow ", sizeof(features)); 487 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_DTS) 488 strlcat(features, "dts ", sizeof(features)); 489 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ITB) 490 strlcat(features, "itb ", sizeof(features)); 491 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ARAT) 492 strlcat(features, "arat ", sizeof(features)); 493 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PLN) 494 strlcat(features, "pln ", sizeof(features)); 495 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ECMD) 496 strlcat(features, "ecmd ", sizeof(features)); 497 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PTM) 498 strlcat(features, "ptm ", sizeof(features)); 499 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP) 500 strlcat(features, "hwp ", sizeof(features)); 501 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_NOTIFY) 502 strlcat(features, "hwp_notify ", sizeof(features)); 503 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_ACTWIN) 504 strlcat(features, "hwp_actwin ", sizeof(features)); 505 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_EPP) 506 strlcat(features, "hwp_epp ", sizeof(features)); 507 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PLR) 508 strlcat(features, "hwp_plr ", sizeof(features)); 509 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HDC) 510 strlcat(features, "hdc ", sizeof(features)); 511 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_TBMT3) 512 strlcat(features, "tbmt3 ", sizeof(features)); 513 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_CAP) 514 strlcat(features, "hwp_cap ", sizeof(features)); 515 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PECI) 516 strlcat(features, "hwp_peci ", sizeof(features)); 517 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FLEX) 518 strlcat(features, "hwp_flex ", sizeof(features)); 519 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FAST) 520 strlcat(features, "hwp_fast ", sizeof(features)); 521 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HW_FEEDBACK) 522 strlcat(features, "hw_feedback ", sizeof(features)); 523 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_IGNIDL) 524 strlcat(features, "hwp_ignidl ", sizeof(features)); 525 if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_APERFMPERF) 526 strlcat(features, "aperfmperf ", sizeof(features)); 527 if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_EPB) 528 strlcat(features, "epb ", sizeof(features)); 529 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_TSC_ADJUST) 530 strlcat(features, "tsc_adjust ", sizeof(features)); 531 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SGX) 532 strlcat(features, "sgx ", sizeof(features)); 533 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI1) 534 strlcat(features, "bmi1 ", sizeof(features)); 535 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_HLE) 536 strlcat(features, "hle ", sizeof(features)); 537 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX2) 538 strlcat(features, "avx2 ", sizeof(features)); 539 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMEP) 540 strlcat(features, "smep ", sizeof(features)); 541 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI2) 542 strlcat(features, "bmi2 ", sizeof(features)); 543 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ERMS) 544 strlcat(features, "erms ", sizeof(features)); 545 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INVPCID) 546 strlcat(features, "invpcid ", sizeof(features)); 547 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RTM) 548 strlcat(features, "rtm ", sizeof(features)); 549 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CQM) 550 strlcat(features, "cqm ", sizeof(features)); 551 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_MPX) 552 strlcat(features, "mpx ", sizeof(features)); 553 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDT_A) 554 strlcat(features, "rdt_a ", sizeof(features)); 555 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512F) 556 strlcat(features, "avx512f ", sizeof(features)); 557 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512DQ) 558 strlcat(features, "avx512dq ", sizeof(features)); 559 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDSEED) 560 strlcat(features, "rdseed ", sizeof(features)); 561 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ADX) 562 strlcat(features, "adx ", sizeof(features)); 563 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMAP) 564 strlcat(features, "smap ", sizeof(features)); 565 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512IFMA) 566 strlcat(features, "avx512ifma ", sizeof(features)); 567 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_PCOMMIT) 568 strlcat(features, "pcommit ", sizeof(features)); 569 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLFLUSHOPT) 570 strlcat(features, "cflushopt ", sizeof(features)); 571 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLWB) 572 strlcat(features, "clwb ", sizeof(features)); 573 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INTEL_PT) 574 strlcat(features, "intel_pt ", sizeof(features)); 575 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512PF) 576 strlcat(features, "avx512pf ", sizeof(features)); 577 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512ER) 578 strlcat(features, "avx512er ", sizeof(features)); 579 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512CD) 580 strlcat(features, "avx512cd ", sizeof(features)); 581 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SHA_NI) 582 strlcat(features, "sha_ni ", sizeof(features)); 583 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512BW) 584 strlcat(features, "avx512bw ", sizeof(features)); 585 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512VI) 586 strlcat(features, "avx512vi ", sizeof(features)); 587 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI) 588 strlcat(features, "avx512vmbi ", sizeof(features)); 589 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_UMIP) 590 strlcat(features, "umip ", sizeof(features)); 591 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_PKU) 592 strlcat(features, "pku ", sizeof(features)); 593 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_OSPKE) 594 strlcat(features, "ospke ", sizeof(features)); 595 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI2) 596 strlcat(features, "avx512vmbi2 ", sizeof(features)); 597 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_GFNI) 598 strlcat(features, "gfni ", sizeof(features)); 599 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VAES) 600 strlcat(features, "vaes ", sizeof(features)); 601 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VPCLMULQDQ) 602 strlcat(features, "vpclmulqdq ", sizeof(features)); 603 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VNNI) 604 strlcat(features, "avx512vnni ", sizeof(features)); 605 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_BITALG) 606 strlcat(features, "avx512bitalg ", sizeof(features)); 607 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VPOPCNTDQ) 608 strlcat(features, "avx512vpopcntdq ", sizeof(features)); 609 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_LA57) 610 strlcat(features, "la57 ", sizeof(features)); 611 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_RDPID) 612 strlcat(features, "rdpid ", sizeof(features)); 613 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_SGX_LC) 614 strlcat(features, "sgx_lc ", sizeof(features)); 615 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_IBRS) 616 strlcat(features, "ibrs ", sizeof(features)); 617 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_STIBP) 618 strlcat(features, "stibp ", sizeof(features)); 619 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_L1D_FLUSH) 620 strlcat(features, "l1d_flush ", sizeof(features)); 621 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_ARCH_CAPABILITIES) 622 strlcat(features, "msr_arch ", sizeof(features)); 623 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_SSBD) 624 strlcat(features, "ssbd ", sizeof(features)); 625 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEOPT) 626 strlcat(features, "xsaveopt ", sizeof(features)); 627 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEC) 628 strlcat(features, "xsavec ", sizeof(features)); 629 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XGETBV1) 630 strlcat(features, "xgetbv1 ", sizeof(features)); 631 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVES) 632 strlcat(features, "xsaves ", sizeof(features)); 633 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_CLZERO) 634 strlcat(features, "clzero ", sizeof(features)); 635 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_IBPB) 636 strlcat(features, "ibpb ", sizeof(features)); 637 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSBD) 638 strlcat(features, "amd_ssbd ", sizeof(features)); 639 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_VIRT_SSBD) 640 strlcat(features, "virt_ssbd ", sizeof(features)); 641 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSB_NO) 642 strlcat(features, "amd_ssb_no ", sizeof(features)); 643 dprintf("CPU %d: features: %s\n", currentCPU, features); 644 } 645 #endif // DUMP_FEATURE_STRING 646 647 648 static void 649 compute_cpu_hierarchy_masks(int maxLogicalID, int maxCoreID) 650 { 651 ASSERT(maxLogicalID >= maxCoreID); 652 const int kMaxSMTID = maxLogicalID / maxCoreID; 653 654 sHierarchyMask[CPU_TOPOLOGY_SMT] = kMaxSMTID - 1; 655 sHierarchyShift[CPU_TOPOLOGY_SMT] = 0; 656 657 sHierarchyMask[CPU_TOPOLOGY_CORE] = (maxCoreID - 1) * kMaxSMTID; 658 sHierarchyShift[CPU_TOPOLOGY_CORE] 659 = count_set_bits(sHierarchyMask[CPU_TOPOLOGY_SMT]); 660 661 const uint32 kSinglePackageMask = sHierarchyMask[CPU_TOPOLOGY_SMT] 662 | sHierarchyMask[CPU_TOPOLOGY_CORE]; 663 sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~kSinglePackageMask; 664 sHierarchyShift[CPU_TOPOLOGY_PACKAGE] = count_set_bits(kSinglePackageMask); 665 } 666 667 668 static uint32 669 get_cpu_legacy_initial_apic_id(int /* currentCPU */) 670 { 671 cpuid_info cpuid; 672 get_current_cpuid(&cpuid, 1, 0); 673 return cpuid.regs.ebx >> 24; 674 } 675 676 677 static inline status_t 678 detect_amd_cpu_topology(uint32 maxBasicLeaf, uint32 maxExtendedLeaf) 679 { 680 sGetCPUTopologyID = get_cpu_legacy_initial_apic_id; 681 682 cpuid_info cpuid; 683 get_current_cpuid(&cpuid, 1, 0); 684 int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff); 685 686 int maxCoreID = 1; 687 if (maxExtendedLeaf >= 0x80000008) { 688 get_current_cpuid(&cpuid, 0x80000008, 0); 689 maxCoreID = (cpuid.regs.ecx >> 12) & 0xf; 690 if (maxCoreID != 0) 691 maxCoreID = 1 << maxCoreID; 692 else 693 maxCoreID = next_power_of_2((cpuid.regs.edx & 0xf) + 1); 694 } 695 696 if (maxExtendedLeaf >= 0x80000001) { 697 get_current_cpuid(&cpuid, 0x80000001, 0); 698 if (x86_check_feature(IA32_FEATURE_AMD_EXT_CMPLEGACY, 699 FEATURE_EXT_AMD_ECX)) 700 maxCoreID = maxLogicalID; 701 } 702 703 compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID); 704 705 return B_OK; 706 } 707 708 709 static void 710 detect_amd_cache_topology(uint32 maxExtendedLeaf) 711 { 712 if (!x86_check_feature(IA32_FEATURE_AMD_EXT_TOPOLOGY, FEATURE_EXT_AMD_ECX)) 713 return; 714 715 if (maxExtendedLeaf < 0x8000001d) 716 return; 717 718 uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL]; 719 int maxCacheLevel = 0; 720 721 int currentLevel = 0; 722 int cacheType; 723 do { 724 cpuid_info cpuid; 725 get_current_cpuid(&cpuid, 0x8000001d, currentLevel); 726 727 cacheType = cpuid.regs.eax & 0x1f; 728 if (cacheType == 0) 729 break; 730 731 int cacheLevel = (cpuid.regs.eax >> 5) & 0x7; 732 int coresCount = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1); 733 hierarchyLevels[cacheLevel - 1] 734 = coresCount * (sHierarchyMask[CPU_TOPOLOGY_SMT] + 1); 735 maxCacheLevel = std::max(maxCacheLevel, cacheLevel); 736 737 currentLevel++; 738 } while (true); 739 740 for (int i = 0; i < maxCacheLevel; i++) 741 sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1); 742 gCPUCacheLevelCount = maxCacheLevel; 743 } 744 745 746 static uint32 747 get_intel_cpu_initial_x2apic_id(int /* currentCPU */) 748 { 749 cpuid_info cpuid; 750 get_current_cpuid(&cpuid, 11, 0); 751 return cpuid.regs.edx; 752 } 753 754 755 static inline status_t 756 detect_intel_cpu_topology_x2apic(uint32 maxBasicLeaf) 757 { 758 if (maxBasicLeaf < 11) 759 return B_UNSUPPORTED; 760 761 uint8 hierarchyLevels[CPU_TOPOLOGY_LEVELS] = { 0 }; 762 763 int currentLevel = 0; 764 int levelType; 765 unsigned int levelsSet = 0; 766 767 do { 768 cpuid_info cpuid; 769 get_current_cpuid(&cpuid, 11, currentLevel); 770 if (currentLevel == 0 && cpuid.regs.ebx == 0) 771 return B_UNSUPPORTED; 772 773 levelType = (cpuid.regs.ecx >> 8) & 0xff; 774 int levelValue = cpuid.regs.eax & 0x1f; 775 776 switch (levelType) { 777 case 1: // SMT 778 hierarchyLevels[CPU_TOPOLOGY_SMT] = levelValue; 779 levelsSet |= 1; 780 break; 781 case 2: // core 782 hierarchyLevels[CPU_TOPOLOGY_CORE] = levelValue; 783 levelsSet |= 2; 784 break; 785 } 786 787 currentLevel++; 788 } while (levelType != 0 && levelsSet != 3); 789 790 sGetCPUTopologyID = get_intel_cpu_initial_x2apic_id; 791 792 for (int i = 1; i < CPU_TOPOLOGY_LEVELS; i++) { 793 if ((levelsSet & (1u << i)) != 0) 794 continue; 795 hierarchyLevels[i] = hierarchyLevels[i - 1]; 796 } 797 798 for (int i = 0; i < CPU_TOPOLOGY_LEVELS; i++) { 799 uint32 mask = ~uint32(0); 800 if (i < CPU_TOPOLOGY_LEVELS - 1) 801 mask = (1u << hierarchyLevels[i]) - 1; 802 if (i > 0) 803 mask &= ~sHierarchyMask[i - 1]; 804 sHierarchyMask[i] = mask; 805 sHierarchyShift[i] = i > 0 ? hierarchyLevels[i - 1] : 0; 806 } 807 808 return B_OK; 809 } 810 811 812 static inline status_t 813 detect_intel_cpu_topology_legacy(uint32 maxBasicLeaf) 814 { 815 sGetCPUTopologyID = get_cpu_legacy_initial_apic_id; 816 817 cpuid_info cpuid; 818 819 get_current_cpuid(&cpuid, 1, 0); 820 int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff); 821 822 int maxCoreID = 1; 823 if (maxBasicLeaf >= 4) { 824 get_current_cpuid(&cpuid, 4, 0); 825 maxCoreID = next_power_of_2((cpuid.regs.eax >> 26) + 1); 826 } 827 828 compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID); 829 830 return B_OK; 831 } 832 833 834 static void 835 detect_intel_cache_topology(uint32 maxBasicLeaf) 836 { 837 if (maxBasicLeaf < 4) 838 return; 839 840 uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL]; 841 int maxCacheLevel = 0; 842 843 int currentLevel = 0; 844 int cacheType; 845 do { 846 cpuid_info cpuid; 847 get_current_cpuid(&cpuid, 4, currentLevel); 848 849 cacheType = cpuid.regs.eax & 0x1f; 850 if (cacheType == 0) 851 break; 852 853 int cacheLevel = (cpuid.regs.eax >> 5) & 0x7; 854 hierarchyLevels[cacheLevel - 1] 855 = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1); 856 maxCacheLevel = std::max(maxCacheLevel, cacheLevel); 857 858 currentLevel++; 859 } while (true); 860 861 for (int i = 0; i < maxCacheLevel; i++) 862 sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1); 863 864 gCPUCacheLevelCount = maxCacheLevel; 865 } 866 867 868 static uint32 869 get_simple_cpu_topology_id(int currentCPU) 870 { 871 return currentCPU; 872 } 873 874 875 static inline int 876 get_topology_level_id(uint32 id, cpu_topology_level level) 877 { 878 ASSERT(level < CPU_TOPOLOGY_LEVELS); 879 return (id & sHierarchyMask[level]) >> sHierarchyShift[level]; 880 } 881 882 883 static void 884 detect_cpu_topology(int currentCPU, cpu_ent* cpu, uint32 maxBasicLeaf, 885 uint32 maxExtendedLeaf) 886 { 887 if (currentCPU == 0) { 888 memset(sCacheSharingMask, 0xff, sizeof(sCacheSharingMask)); 889 890 status_t result = B_UNSUPPORTED; 891 if (x86_check_feature(IA32_FEATURE_HTT, FEATURE_COMMON)) { 892 if (cpu->arch.vendor == VENDOR_AMD 893 || cpu->arch.vendor == VENDOR_HYGON) { 894 result = detect_amd_cpu_topology(maxBasicLeaf, maxExtendedLeaf); 895 896 if (result == B_OK) 897 detect_amd_cache_topology(maxExtendedLeaf); 898 } 899 900 if (cpu->arch.vendor == VENDOR_INTEL) { 901 result = detect_intel_cpu_topology_x2apic(maxBasicLeaf); 902 if (result != B_OK) 903 result = detect_intel_cpu_topology_legacy(maxBasicLeaf); 904 905 if (result == B_OK) 906 detect_intel_cache_topology(maxBasicLeaf); 907 } 908 } 909 910 if (result != B_OK) { 911 dprintf("No CPU topology information available.\n"); 912 913 sGetCPUTopologyID = get_simple_cpu_topology_id; 914 915 sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~uint32(0); 916 } 917 } 918 919 ASSERT(sGetCPUTopologyID != NULL); 920 int topologyID = sGetCPUTopologyID(currentCPU); 921 cpu->topology_id[CPU_TOPOLOGY_SMT] 922 = get_topology_level_id(topologyID, CPU_TOPOLOGY_SMT); 923 cpu->topology_id[CPU_TOPOLOGY_CORE] 924 = get_topology_level_id(topologyID, CPU_TOPOLOGY_CORE); 925 cpu->topology_id[CPU_TOPOLOGY_PACKAGE] 926 = get_topology_level_id(topologyID, CPU_TOPOLOGY_PACKAGE); 927 928 unsigned int i; 929 for (i = 0; i < gCPUCacheLevelCount; i++) 930 cpu->cache_id[i] = topologyID & sCacheSharingMask[i]; 931 for (; i < CPU_MAX_CACHE_LEVEL; i++) 932 cpu->cache_id[i] = -1; 933 934 #if DUMP_CPU_TOPOLOGY 935 dprintf("CPU %d: apic id %d, package %d, core %d, smt %d\n", currentCPU, 936 topologyID, cpu->topology_id[CPU_TOPOLOGY_PACKAGE], 937 cpu->topology_id[CPU_TOPOLOGY_CORE], 938 cpu->topology_id[CPU_TOPOLOGY_SMT]); 939 940 if (gCPUCacheLevelCount > 0) { 941 char cacheLevels[256]; 942 unsigned int offset = 0; 943 for (i = 0; i < gCPUCacheLevelCount; i++) { 944 offset += snprintf(cacheLevels + offset, 945 sizeof(cacheLevels) - offset, 946 " L%d id %d%s", i + 1, cpu->cache_id[i], 947 i < gCPUCacheLevelCount - 1 ? "," : ""); 948 949 if (offset >= sizeof(cacheLevels)) 950 break; 951 } 952 953 dprintf("CPU %d: cache sharing:%s\n", currentCPU, cacheLevels); 954 } 955 #endif 956 } 957 958 959 static void 960 detect_intel_patch_level(cpu_ent* cpu) 961 { 962 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) { 963 cpu->arch.patch_level = 0; 964 return; 965 } 966 967 x86_write_msr(IA32_MSR_UCODE_REV, 0); 968 cpuid_info cpuid; 969 get_current_cpuid(&cpuid, 1, 0); 970 971 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV); 972 cpu->arch.patch_level = value >> 32; 973 } 974 975 976 static void 977 detect_amd_patch_level(cpu_ent* cpu) 978 { 979 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) { 980 cpu->arch.patch_level = 0; 981 return; 982 } 983 984 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV); 985 cpu->arch.patch_level = value >> 32; 986 } 987 988 989 static struct intel_microcode_header* 990 find_microcode_intel(addr_t data, size_t size, uint32 patchLevel) 991 { 992 // 9.11.3 Processor Identification 993 cpuid_info cpuid; 994 get_current_cpuid(&cpuid, 1, 0); 995 uint32 signature = cpuid.regs.eax; 996 // 9.11.4 Platform Identification 997 uint64 platformBits = (x86_read_msr(IA32_MSR_PLATFORM_ID) >> 50) & 0x7; 998 uint64 mask = 1 << platformBits; 999 1000 while (size > 0) { 1001 if (size < sizeof(struct intel_microcode_header)) { 1002 dprintf("find_microcode_intel update is too small for header\n"); 1003 break; 1004 } 1005 struct intel_microcode_header* header = 1006 (struct intel_microcode_header*)data; 1007 1008 uint32 totalSize = header->total_size; 1009 uint32 dataSize = header->data_size; 1010 if (dataSize == 0) { 1011 dataSize = 2000; 1012 totalSize = sizeof(struct intel_microcode_header) 1013 + dataSize; 1014 } 1015 if (totalSize > size) { 1016 dprintf("find_microcode_intel update is too small for data\n"); 1017 break; 1018 } 1019 1020 uint32* dwords = (uint32*)data; 1021 // prepare the next update 1022 size -= totalSize; 1023 data += totalSize; 1024 1025 if (header->loader_revision != 1) { 1026 dprintf("find_microcode_intel incorrect loader version\n"); 1027 continue; 1028 } 1029 // 9.11.6 The microcode update data requires a 16-byte boundary 1030 // alignment. 1031 if (((addr_t)header % 16) != 0) { 1032 dprintf("find_microcode_intel incorrect alignment\n"); 1033 continue; 1034 } 1035 uint32 sum = 0; 1036 for (uint32 i = 0; i < totalSize / 4; i++) { 1037 sum += dwords[i]; 1038 } 1039 if (sum != 0) { 1040 dprintf("find_microcode_intel incorrect checksum\n"); 1041 continue; 1042 } 1043 if (patchLevel > header->update_revision) { 1044 dprintf("find_microcode_intel update_revision is lower\n"); 1045 continue; 1046 } 1047 if (signature == header->processor_signature 1048 && (mask & header->processor_flags) != 0) { 1049 return header; 1050 } 1051 if (totalSize <= (sizeof(struct intel_microcode_header) + dataSize 1052 + sizeof(struct intel_microcode_extended_signature_header))) { 1053 continue; 1054 } 1055 struct intel_microcode_extended_signature_header* extSigHeader = 1056 (struct intel_microcode_extended_signature_header*)((addr_t)header 1057 + sizeof(struct intel_microcode_header) + dataSize); 1058 struct intel_microcode_extended_signature* extended_signature = 1059 (struct intel_microcode_extended_signature*)((addr_t)extSigHeader 1060 + sizeof(struct intel_microcode_extended_signature_header)); 1061 for (uint32 i = 0; i < extSigHeader->extended_signature_count; i++) { 1062 if (signature == extended_signature[i].processor_signature 1063 && (mask & extended_signature[i].processor_flags) != 0) 1064 return header; 1065 } 1066 } 1067 return NULL; 1068 } 1069 1070 1071 static void 1072 load_microcode_intel(int currentCPU, cpu_ent* cpu) 1073 { 1074 // serialize for HT cores 1075 if (currentCPU != 0) 1076 acquire_spinlock(&sUcodeUpdateLock); 1077 detect_intel_patch_level(cpu); 1078 uint32 revision = cpu->arch.patch_level; 1079 struct intel_microcode_header* update = sLoadedUcodeUpdate; 1080 if (update == NULL) { 1081 update = find_microcode_intel((addr_t)sUcodeData, sUcodeDataSize, 1082 revision); 1083 } 1084 if (update != NULL) { 1085 addr_t data = (addr_t)update + sizeof(struct intel_microcode_header); 1086 wbinvd(); 1087 x86_write_msr(IA32_MSR_UCODE_WRITE, data); 1088 detect_intel_patch_level(cpu); 1089 if (revision == cpu->arch.patch_level) { 1090 dprintf("CPU %d: update failed\n", currentCPU); 1091 } else { 1092 if (sLoadedUcodeUpdate == NULL) 1093 sLoadedUcodeUpdate = update; 1094 dprintf("CPU %d: updated from revision %" B_PRIu32 " to %" B_PRIu32 1095 "\n", currentCPU, revision, cpu->arch.patch_level); 1096 } 1097 } else { 1098 dprintf("CPU %d: no update found\n", currentCPU); 1099 } 1100 if (currentCPU != 0) 1101 release_spinlock(&sUcodeUpdateLock); 1102 } 1103 1104 1105 static void 1106 load_microcode_amd(int currentCPU, cpu_ent* cpu) 1107 { 1108 dprintf("CPU %d: no update found\n", currentCPU); 1109 } 1110 1111 1112 static void 1113 load_microcode(int currentCPU) 1114 { 1115 if (sUcodeData == NULL) 1116 return; 1117 cpu_ent* cpu = get_cpu_struct(); 1118 if ((cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) != 0) 1119 return; 1120 if (cpu->arch.vendor == VENDOR_INTEL) 1121 load_microcode_intel(currentCPU, cpu); 1122 else if (cpu->arch.vendor == VENDOR_AMD) 1123 load_microcode_amd(currentCPU, cpu); 1124 } 1125 1126 1127 static void 1128 detect_cpu(int currentCPU) 1129 { 1130 cpu_ent* cpu = get_cpu_struct(); 1131 char vendorString[17]; 1132 cpuid_info cpuid; 1133 1134 // clear out the cpu info data 1135 cpu->arch.vendor = VENDOR_UNKNOWN; 1136 cpu->arch.vendor_name = "UNKNOWN VENDOR"; 1137 cpu->arch.feature[FEATURE_COMMON] = 0; 1138 cpu->arch.feature[FEATURE_EXT] = 0; 1139 cpu->arch.feature[FEATURE_EXT_AMD] = 0; 1140 cpu->arch.feature[FEATURE_7_EBX] = 0; 1141 cpu->arch.feature[FEATURE_7_ECX] = 0; 1142 cpu->arch.feature[FEATURE_7_EDX] = 0; 1143 cpu->arch.feature[FEATURE_D_1_EAX] = 0; 1144 cpu->arch.model_name[0] = 0; 1145 1146 // print some fun data 1147 get_current_cpuid(&cpuid, 0, 0); 1148 uint32 maxBasicLeaf = cpuid.eax_0.max_eax; 1149 1150 // build the vendor string 1151 memset(vendorString, 0, sizeof(vendorString)); 1152 memcpy(vendorString, cpuid.eax_0.vendor_id, sizeof(cpuid.eax_0.vendor_id)); 1153 1154 // get the family, model, stepping 1155 get_current_cpuid(&cpuid, 1, 0); 1156 cpu->arch.type = cpuid.eax_1.type; 1157 cpu->arch.family = cpuid.eax_1.family; 1158 cpu->arch.extended_family = cpuid.eax_1.extended_family; 1159 cpu->arch.model = cpuid.eax_1.model; 1160 cpu->arch.extended_model = cpuid.eax_1.extended_model; 1161 cpu->arch.stepping = cpuid.eax_1.stepping; 1162 dprintf("CPU %d: type %d family %d extended_family %d model %d " 1163 "extended_model %d stepping %d, string '%s'\n", 1164 currentCPU, cpu->arch.type, cpu->arch.family, 1165 cpu->arch.extended_family, cpu->arch.model, 1166 cpu->arch.extended_model, cpu->arch.stepping, vendorString); 1167 1168 // figure out what vendor we have here 1169 1170 for (int32 i = 0; i < VENDOR_NUM; i++) { 1171 if (vendor_info[i].ident_string[0] 1172 && !strcmp(vendorString, vendor_info[i].ident_string[0])) { 1173 cpu->arch.vendor = (x86_vendors)i; 1174 cpu->arch.vendor_name = vendor_info[i].vendor; 1175 break; 1176 } 1177 if (vendor_info[i].ident_string[1] 1178 && !strcmp(vendorString, vendor_info[i].ident_string[1])) { 1179 cpu->arch.vendor = (x86_vendors)i; 1180 cpu->arch.vendor_name = vendor_info[i].vendor; 1181 break; 1182 } 1183 } 1184 1185 // see if we can get the model name 1186 get_current_cpuid(&cpuid, 0x80000000, 0); 1187 uint32 maxExtendedLeaf = cpuid.eax_0.max_eax; 1188 if (maxExtendedLeaf >= 0x80000004) { 1189 // build the model string (need to swap ecx/edx data before copying) 1190 unsigned int temp; 1191 memset(cpu->arch.model_name, 0, sizeof(cpu->arch.model_name)); 1192 1193 get_current_cpuid(&cpuid, 0x80000002, 0); 1194 temp = cpuid.regs.edx; 1195 cpuid.regs.edx = cpuid.regs.ecx; 1196 cpuid.regs.ecx = temp; 1197 memcpy(cpu->arch.model_name, cpuid.as_chars, sizeof(cpuid.as_chars)); 1198 1199 get_current_cpuid(&cpuid, 0x80000003, 0); 1200 temp = cpuid.regs.edx; 1201 cpuid.regs.edx = cpuid.regs.ecx; 1202 cpuid.regs.ecx = temp; 1203 memcpy(cpu->arch.model_name + 16, cpuid.as_chars, 1204 sizeof(cpuid.as_chars)); 1205 1206 get_current_cpuid(&cpuid, 0x80000004, 0); 1207 temp = cpuid.regs.edx; 1208 cpuid.regs.edx = cpuid.regs.ecx; 1209 cpuid.regs.ecx = temp; 1210 memcpy(cpu->arch.model_name + 32, cpuid.as_chars, 1211 sizeof(cpuid.as_chars)); 1212 1213 // some cpus return a right-justified string 1214 int32 i = 0; 1215 while (cpu->arch.model_name[i] == ' ') 1216 i++; 1217 if (i > 0) { 1218 memmove(cpu->arch.model_name, &cpu->arch.model_name[i], 1219 strlen(&cpu->arch.model_name[i]) + 1); 1220 } 1221 1222 dprintf("CPU %d: vendor '%s' model name '%s'\n", 1223 currentCPU, cpu->arch.vendor_name, cpu->arch.model_name); 1224 } else { 1225 strlcpy(cpu->arch.model_name, "unknown", sizeof(cpu->arch.model_name)); 1226 } 1227 1228 // load feature bits 1229 get_current_cpuid(&cpuid, 1, 0); 1230 cpu->arch.feature[FEATURE_COMMON] = cpuid.eax_1.features; // edx 1231 cpu->arch.feature[FEATURE_EXT] = cpuid.eax_1.extended_features; // ecx 1232 1233 if (maxExtendedLeaf >= 0x80000001) { 1234 get_current_cpuid(&cpuid, 0x80000001, 0); 1235 if (cpu->arch.vendor == VENDOR_AMD) 1236 cpu->arch.feature[FEATURE_EXT_AMD_ECX] = cpuid.regs.ecx; // ecx 1237 cpu->arch.feature[FEATURE_EXT_AMD] = cpuid.regs.edx; // edx 1238 if (cpu->arch.vendor != VENDOR_AMD) 1239 cpu->arch.feature[FEATURE_EXT_AMD] &= IA32_FEATURES_INTEL_EXT; 1240 } 1241 1242 if (maxBasicLeaf >= 5) { 1243 get_current_cpuid(&cpuid, 5, 0); 1244 cpu->arch.feature[FEATURE_5_ECX] = cpuid.regs.ecx; 1245 } 1246 1247 if (maxBasicLeaf >= 6) { 1248 get_current_cpuid(&cpuid, 6, 0); 1249 cpu->arch.feature[FEATURE_6_EAX] = cpuid.regs.eax; 1250 cpu->arch.feature[FEATURE_6_ECX] = cpuid.regs.ecx; 1251 } 1252 1253 if (maxBasicLeaf >= 7) { 1254 get_current_cpuid(&cpuid, 7, 0); 1255 cpu->arch.feature[FEATURE_7_EBX] = cpuid.regs.ebx; 1256 cpu->arch.feature[FEATURE_7_ECX] = cpuid.regs.ecx; 1257 cpu->arch.feature[FEATURE_7_EDX] = cpuid.regs.edx; 1258 } 1259 1260 if (maxBasicLeaf >= 0xd) { 1261 get_current_cpuid(&cpuid, 0xd, 1); 1262 cpu->arch.feature[FEATURE_D_1_EAX] = cpuid.regs.eax; 1263 } 1264 1265 if (maxExtendedLeaf >= 0x80000007) { 1266 get_current_cpuid(&cpuid, 0x80000007, 0); 1267 cpu->arch.feature[FEATURE_EXT_7_EDX] = cpuid.regs.edx; 1268 } 1269 1270 if (maxExtendedLeaf >= 0x80000008) { 1271 get_current_cpuid(&cpuid, 0x80000008, 0); 1272 cpu->arch.feature[FEATURE_EXT_8_EBX] = cpuid.regs.ebx; 1273 } 1274 1275 detect_cpu_topology(currentCPU, cpu, maxBasicLeaf, maxExtendedLeaf); 1276 1277 if (cpu->arch.vendor == VENDOR_INTEL) 1278 detect_intel_patch_level(cpu); 1279 else if (cpu->arch.vendor == VENDOR_AMD) 1280 detect_amd_patch_level(cpu); 1281 1282 #if DUMP_FEATURE_STRING 1283 dump_feature_string(currentCPU, cpu); 1284 #endif 1285 #if DUMP_CPU_PATCHLEVEL 1286 dprintf("CPU %d: patch_level %" B_PRIu32 "\n", currentCPU, 1287 cpu->arch.patch_level); 1288 #endif 1289 } 1290 1291 1292 bool 1293 x86_check_feature(uint32 feature, enum x86_feature_type type) 1294 { 1295 cpu_ent* cpu = get_cpu_struct(); 1296 1297 #if 0 1298 int i; 1299 dprintf("x86_check_feature: feature 0x%x, type %d\n", feature, type); 1300 for (i = 0; i < FEATURE_NUM; i++) { 1301 dprintf("features %d: 0x%x\n", i, cpu->arch.feature[i]); 1302 } 1303 #endif 1304 1305 return (cpu->arch.feature[type] & feature) != 0; 1306 } 1307 1308 1309 void* 1310 x86_get_double_fault_stack(int32 cpu, size_t* _size) 1311 { 1312 *_size = kDoubleFaultStackSize; 1313 return sDoubleFaultStacks + kDoubleFaultStackSize * cpu; 1314 } 1315 1316 1317 /*! Returns the index of the current CPU. Can only be called from the double 1318 fault handler. 1319 */ 1320 int32 1321 x86_double_fault_get_cpu(void) 1322 { 1323 addr_t stack = x86_get_stack_frame(); 1324 return (stack - (addr_t)sDoubleFaultStacks) / kDoubleFaultStackSize; 1325 } 1326 1327 1328 // #pragma mark - 1329 1330 1331 status_t 1332 arch_cpu_preboot_init_percpu(kernel_args* args, int cpu) 1333 { 1334 // On SMP system we want to synchronize the CPUs' TSCs, so system_time() 1335 // will return consistent values. 1336 if (smp_get_num_cpus() > 1) { 1337 // let the first CPU prepare the rendezvous point 1338 if (cpu == 0) 1339 sTSCSyncRendezvous = smp_get_num_cpus() - 1; 1340 1341 // One CPU after the other will drop out of this loop and be caught by 1342 // the loop below, until the last CPU (0) gets there. Save for +/- a few 1343 // cycles the CPUs should pass the second loop at the same time. 1344 while (sTSCSyncRendezvous != cpu) { 1345 } 1346 1347 sTSCSyncRendezvous = cpu - 1; 1348 1349 while (sTSCSyncRendezvous != -1) { 1350 } 1351 1352 // reset TSC to 0 1353 x86_write_msr(IA32_MSR_TSC, 0); 1354 } 1355 1356 x86_descriptors_preboot_init_percpu(args, cpu); 1357 1358 return B_OK; 1359 } 1360 1361 1362 static void 1363 halt_idle(void) 1364 { 1365 asm("hlt"); 1366 } 1367 1368 1369 static void 1370 amdc1e_noarat_idle(void) 1371 { 1372 uint64 msr = x86_read_msr(K8_MSR_IPM); 1373 if (msr & K8_CMPHALT) 1374 x86_write_msr(K8_MSR_IPM, msr & ~K8_CMPHALT); 1375 halt_idle(); 1376 } 1377 1378 1379 static bool 1380 detect_amdc1e_noarat() 1381 { 1382 cpu_ent* cpu = get_cpu_struct(); 1383 1384 if (cpu->arch.vendor != VENDOR_AMD) 1385 return false; 1386 1387 // Family 0x12 and higher processors support ARAT 1388 // Family lower than 0xf processors doesn't support C1E 1389 // Family 0xf with model <= 0x40 procssors doesn't support C1E 1390 uint32 family = cpu->arch.family + cpu->arch.extended_family; 1391 uint32 model = (cpu->arch.extended_model << 4) | cpu->arch.model; 1392 return (family < 0x12 && family > 0xf) || (family == 0xf && model > 0x40); 1393 } 1394 1395 1396 status_t 1397 arch_cpu_init_percpu(kernel_args* args, int cpu) 1398 { 1399 load_microcode(cpu); 1400 detect_cpu(cpu); 1401 1402 if (!gCpuIdleFunc) { 1403 if (detect_amdc1e_noarat()) 1404 gCpuIdleFunc = amdc1e_noarat_idle; 1405 else 1406 gCpuIdleFunc = halt_idle; 1407 } 1408 1409 if (x86_check_feature(IA32_FEATURE_MCE, FEATURE_COMMON)) 1410 x86_write_cr4(x86_read_cr4() | IA32_CR4_MCE); 1411 1412 #ifdef __x86_64__ 1413 // if RDTSCP is available write cpu number in TSC_AUX 1414 if (x86_check_feature(IA32_FEATURE_AMD_EXT_RDTSCP, FEATURE_EXT_AMD)) 1415 x86_write_msr(IA32_MSR_TSC_AUX, cpu); 1416 #endif 1417 1418 return __x86_patch_errata_percpu(cpu); 1419 } 1420 1421 1422 status_t 1423 arch_cpu_init(kernel_args* args) 1424 { 1425 if (args->ucode_data != NULL 1426 && args->ucode_data_size > 0) { 1427 sUcodeData = args->ucode_data; 1428 sUcodeDataSize = args->ucode_data_size; 1429 } else { 1430 dprintf("CPU: no microcode provided\n"); 1431 } 1432 1433 // init the TSC -> system_time() conversion factors 1434 1435 uint32 conversionFactor = args->arch_args.system_time_cv_factor; 1436 uint64 conversionFactorNsecs = (uint64)conversionFactor * 1000; 1437 1438 #ifdef __x86_64__ 1439 // The x86_64 system_time() implementation uses 64-bit multiplication and 1440 // therefore shifting is not necessary for low frequencies (it's also not 1441 // too likely that there'll be any x86_64 CPUs clocked under 1GHz). 1442 __x86_setup_system_time((uint64)conversionFactor << 32, 1443 conversionFactorNsecs); 1444 #else 1445 if (conversionFactorNsecs >> 32 != 0) { 1446 // the TSC frequency is < 1 GHz, which forces us to shift the factor 1447 __x86_setup_system_time(conversionFactor, conversionFactorNsecs >> 16, 1448 true); 1449 } else { 1450 // the TSC frequency is >= 1 GHz 1451 __x86_setup_system_time(conversionFactor, conversionFactorNsecs, false); 1452 } 1453 #endif 1454 1455 // Initialize descriptor tables. 1456 x86_descriptors_init(args); 1457 1458 return B_OK; 1459 } 1460 1461 1462 #ifdef __x86_64__ 1463 static void 1464 enable_smap(void* dummy, int cpu) 1465 { 1466 x86_write_cr4(x86_read_cr4() | IA32_CR4_SMAP); 1467 } 1468 1469 1470 static void 1471 enable_smep(void* dummy, int cpu) 1472 { 1473 x86_write_cr4(x86_read_cr4() | IA32_CR4_SMEP); 1474 } 1475 1476 1477 static void 1478 enable_osxsave(void* dummy, int cpu) 1479 { 1480 x86_write_cr4(x86_read_cr4() | IA32_CR4_OSXSAVE); 1481 } 1482 1483 1484 static void 1485 enable_xsavemask(void* dummy, int cpu) 1486 { 1487 xsetbv(0, gXsaveMask); 1488 } 1489 #endif 1490 1491 1492 status_t 1493 arch_cpu_init_post_vm(kernel_args* args) 1494 { 1495 uint32 i; 1496 1497 // allocate an area for the double fault stacks 1498 virtual_address_restrictions virtualRestrictions = {}; 1499 virtualRestrictions.address_specification = B_ANY_KERNEL_ADDRESS; 1500 physical_address_restrictions physicalRestrictions = {}; 1501 create_area_etc(B_SYSTEM_TEAM, "double fault stacks", 1502 kDoubleFaultStackSize * smp_get_num_cpus(), B_FULL_LOCK, 1503 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, CREATE_AREA_DONT_WAIT, 0, 1504 &virtualRestrictions, &physicalRestrictions, 1505 (void**)&sDoubleFaultStacks); 1506 1507 X86PagingStructures* kernelPagingStructures 1508 = static_cast<X86VMTranslationMap*>( 1509 VMAddressSpace::Kernel()->TranslationMap())->PagingStructures(); 1510 1511 // Set active translation map on each CPU. 1512 for (i = 0; i < args->num_cpus; i++) { 1513 gCPU[i].arch.active_paging_structures = kernelPagingStructures; 1514 kernelPagingStructures->AddReference(); 1515 } 1516 1517 if (!apic_available()) 1518 x86_init_fpu(); 1519 // else fpu gets set up in smp code 1520 1521 #ifdef __x86_64__ 1522 // if available enable SMEP (Supervisor Memory Execution Protection) 1523 if (x86_check_feature(IA32_FEATURE_SMEP, FEATURE_7_EBX)) { 1524 if (!get_safemode_boolean(B_SAFEMODE_DISABLE_SMEP_SMAP, false)) { 1525 dprintf("enable SMEP\n"); 1526 call_all_cpus_sync(&enable_smep, NULL); 1527 } else 1528 dprintf("SMEP disabled per safemode setting\n"); 1529 } 1530 1531 // if available enable SMAP (Supervisor Memory Access Protection) 1532 if (x86_check_feature(IA32_FEATURE_SMAP, FEATURE_7_EBX)) { 1533 if (!get_safemode_boolean(B_SAFEMODE_DISABLE_SMEP_SMAP, false)) { 1534 dprintf("enable SMAP\n"); 1535 call_all_cpus_sync(&enable_smap, NULL); 1536 1537 arch_altcodepatch_replace(ALTCODEPATCH_TAG_STAC, &_stac, 3); 1538 arch_altcodepatch_replace(ALTCODEPATCH_TAG_CLAC, &_clac, 3); 1539 } else 1540 dprintf("SMAP disabled per safemode setting\n"); 1541 } 1542 1543 // if available enable XSAVE (XSAVE and extended states) 1544 gHasXsave = x86_check_feature(IA32_FEATURE_EXT_XSAVE, FEATURE_EXT); 1545 if (gHasXsave) { 1546 gHasXsavec = x86_check_feature(IA32_FEATURE_XSAVEC, 1547 FEATURE_D_1_EAX); 1548 1549 call_all_cpus_sync(&enable_osxsave, NULL); 1550 gXsaveMask = IA32_XCR0_X87 | IA32_XCR0_SSE; 1551 cpuid_info cpuid; 1552 get_current_cpuid(&cpuid, 0xd, 0); 1553 gXsaveMask |= (cpuid.regs.eax & IA32_XCR0_AVX); 1554 call_all_cpus_sync(&enable_xsavemask, NULL); 1555 get_current_cpuid(&cpuid, 0xd, 0); 1556 gFPUSaveLength = cpuid.regs.ebx; 1557 if (gFPUSaveLength > sizeof(((struct arch_thread *)0)->fpu_state)) 1558 gFPUSaveLength = 832; 1559 1560 arch_altcodepatch_replace(ALTCODEPATCH_TAG_XSAVE, 1561 gHasXsavec ? &_xsavec : &_xsave, 4); 1562 arch_altcodepatch_replace(ALTCODEPATCH_TAG_XRSTOR, 1563 &_xrstor, 4); 1564 1565 dprintf("enable %s 0x%" B_PRIx64 " %" B_PRId64 "\n", 1566 gHasXsavec ? "XSAVEC" : "XSAVE", gXsaveMask, gFPUSaveLength); 1567 } 1568 1569 #endif 1570 1571 return B_OK; 1572 } 1573 1574 1575 status_t 1576 arch_cpu_init_post_modules(kernel_args* args) 1577 { 1578 // initialize CPU module 1579 1580 void* cookie = open_module_list("cpu"); 1581 1582 while (true) { 1583 char name[B_FILE_NAME_LENGTH]; 1584 size_t nameLength = sizeof(name); 1585 1586 if (read_next_module_name(cookie, name, &nameLength) != B_OK 1587 || get_module(name, (module_info**)&sCpuModule) == B_OK) 1588 break; 1589 } 1590 1591 close_module_list(cookie); 1592 1593 // initialize MTRRs if available 1594 if (x86_count_mtrrs() > 0) { 1595 sCpuRendezvous = sCpuRendezvous2 = 0; 1596 call_all_cpus(&init_mtrrs, NULL); 1597 } 1598 1599 size_t threadExitLen = (addr_t)x86_end_userspace_thread_exit 1600 - (addr_t)x86_userspace_thread_exit; 1601 addr_t threadExitPosition = fill_commpage_entry( 1602 COMMPAGE_ENTRY_X86_THREAD_EXIT, (const void*)x86_userspace_thread_exit, 1603 threadExitLen); 1604 1605 // add the functions to the commpage image 1606 image_id image = get_commpage_image(); 1607 1608 elf_add_memory_image_symbol(image, "commpage_thread_exit", 1609 threadExitPosition, threadExitLen, B_SYMBOL_TYPE_TEXT); 1610 1611 return B_OK; 1612 } 1613 1614 1615 void 1616 arch_cpu_user_TLB_invalidate(void) 1617 { 1618 x86_write_cr3(x86_read_cr3()); 1619 } 1620 1621 1622 void 1623 arch_cpu_global_TLB_invalidate(void) 1624 { 1625 uint32 flags = x86_read_cr4(); 1626 1627 if (flags & IA32_CR4_GLOBAL_PAGES) { 1628 // disable and reenable the global pages to flush all TLBs regardless 1629 // of the global page bit 1630 x86_write_cr4(flags & ~IA32_CR4_GLOBAL_PAGES); 1631 x86_write_cr4(flags | IA32_CR4_GLOBAL_PAGES); 1632 } else { 1633 cpu_status state = disable_interrupts(); 1634 arch_cpu_user_TLB_invalidate(); 1635 restore_interrupts(state); 1636 } 1637 } 1638 1639 1640 void 1641 arch_cpu_invalidate_TLB_range(addr_t start, addr_t end) 1642 { 1643 int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE; 1644 while (num_pages-- >= 0) { 1645 invalidate_TLB(start); 1646 start += B_PAGE_SIZE; 1647 } 1648 } 1649 1650 1651 void 1652 arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages) 1653 { 1654 int i; 1655 for (i = 0; i < num_pages; i++) { 1656 invalidate_TLB(pages[i]); 1657 } 1658 } 1659 1660 1661 status_t 1662 arch_cpu_shutdown(bool rebootSystem) 1663 { 1664 if (acpi_shutdown(rebootSystem) == B_OK) 1665 return B_OK; 1666 1667 if (!rebootSystem) { 1668 #ifndef __x86_64__ 1669 return apm_shutdown(); 1670 #else 1671 return B_NOT_SUPPORTED; 1672 #endif 1673 } 1674 1675 cpu_status state = disable_interrupts(); 1676 1677 // try to reset the system using the keyboard controller 1678 out8(0xfe, 0x64); 1679 1680 // Give some time to the controller to do its job (0.5s) 1681 snooze(500000); 1682 1683 // if that didn't help, try it this way 1684 x86_reboot(); 1685 1686 restore_interrupts(state); 1687 return B_ERROR; 1688 } 1689 1690 1691 void 1692 arch_cpu_sync_icache(void* address, size_t length) 1693 { 1694 // instruction cache is always consistent on x86 1695 } 1696 1697