1 /* 2 * Copyright 2018, Jérôme Duval, jerome.duval@gmail.com. 3 * Copyright 2002-2010, Axel Dörfler, axeld@pinc-software.de. 4 * Copyright 2013, Paweł Dziepak, pdziepak@quarnos.org. 5 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 6 * Distributed under the terms of the MIT License. 7 * 8 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 9 * Distributed under the terms of the NewOS License. 10 */ 11 12 13 #include <cpu.h> 14 15 #include <string.h> 16 #include <stdlib.h> 17 #include <stdio.h> 18 19 #include <algorithm> 20 21 #include <ACPI.h> 22 23 #include <boot_device.h> 24 #include <commpage.h> 25 #include <debug.h> 26 #include <elf.h> 27 #include <safemode.h> 28 #include <smp.h> 29 #include <util/BitUtils.h> 30 #include <vm/vm.h> 31 #include <vm/vm_types.h> 32 #include <vm/VMAddressSpace.h> 33 34 #include <arch_system_info.h> 35 #include <arch/x86/apic.h> 36 #include <boot/kernel_args.h> 37 38 #include "paging/X86PagingStructures.h" 39 #include "paging/X86VMTranslationMap.h" 40 41 42 #define DUMP_FEATURE_STRING 1 43 #define DUMP_CPU_TOPOLOGY 1 44 #define DUMP_CPU_PATCHLEVEL 1 45 46 47 /* cpu vendor info */ 48 struct cpu_vendor_info { 49 const char *vendor; 50 const char *ident_string[2]; 51 }; 52 53 static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = { 54 { "Intel", { "GenuineIntel" } }, 55 { "AMD", { "AuthenticAMD" } }, 56 { "Cyrix", { "CyrixInstead" } }, 57 { "UMC", { "UMC UMC UMC" } }, 58 { "NexGen", { "NexGenDriven" } }, 59 { "Centaur", { "CentaurHauls" } }, 60 { "Rise", { "RiseRiseRise" } }, 61 { "Transmeta", { "GenuineTMx86", "TransmetaCPU" } }, 62 { "NSC", { "Geode by NSC" } }, 63 { "Hygon", { "HygonGenuine" } }, 64 }; 65 66 #define K8_SMIONCMPHALT (1ULL << 27) 67 #define K8_C1EONCMPHALT (1ULL << 28) 68 69 #define K8_CMPHALT (K8_SMIONCMPHALT | K8_C1EONCMPHALT) 70 71 struct set_mtrr_parameter { 72 int32 index; 73 uint64 base; 74 uint64 length; 75 uint8 type; 76 }; 77 78 struct set_mtrrs_parameter { 79 const x86_mtrr_info* infos; 80 uint32 count; 81 uint8 defaultType; 82 }; 83 84 85 #ifdef __x86_64__ 86 extern addr_t _stac; 87 extern addr_t _clac; 88 extern addr_t _xsave; 89 extern addr_t _xsavec; 90 extern addr_t _xrstor; 91 uint64 gXsaveMask; 92 uint64 gFPUSaveLength = 512; 93 bool gHasXsave = false; 94 bool gHasXsavec = false; 95 #endif 96 97 extern "C" void x86_reboot(void); 98 // from arch.S 99 100 void (*gCpuIdleFunc)(void); 101 #ifndef __x86_64__ 102 void (*gX86SwapFPUFunc)(void* oldState, const void* newState) = x86_noop_swap; 103 bool gHasSSE = false; 104 #endif 105 106 static uint32 sCpuRendezvous; 107 static uint32 sCpuRendezvous2; 108 static uint32 sCpuRendezvous3; 109 static vint32 sTSCSyncRendezvous; 110 111 /* Some specials for the double fault handler */ 112 static uint8* sDoubleFaultStacks; 113 static const size_t kDoubleFaultStackSize = 4096; // size per CPU 114 115 static x86_cpu_module_info* sCpuModule; 116 117 118 /* CPU topology information */ 119 static uint32 (*sGetCPUTopologyID)(int currentCPU); 120 static uint32 sHierarchyMask[CPU_TOPOLOGY_LEVELS]; 121 static uint32 sHierarchyShift[CPU_TOPOLOGY_LEVELS]; 122 123 /* Cache topology information */ 124 static uint32 sCacheSharingMask[CPU_MAX_CACHE_LEVEL]; 125 126 static void* sUcodeData = NULL; 127 static size_t sUcodeDataSize = 0; 128 static struct intel_microcode_header* sLoadedUcodeUpdate; 129 static spinlock sUcodeUpdateLock = B_SPINLOCK_INITIALIZER; 130 131 132 static status_t 133 acpi_shutdown(bool rebootSystem) 134 { 135 if (debug_debugger_running() || !are_interrupts_enabled()) 136 return B_ERROR; 137 138 acpi_module_info* acpi; 139 if (get_module(B_ACPI_MODULE_NAME, (module_info**)&acpi) != B_OK) 140 return B_NOT_SUPPORTED; 141 142 status_t status; 143 if (rebootSystem) { 144 status = acpi->reboot(); 145 } else { 146 status = acpi->prepare_sleep_state(ACPI_POWER_STATE_OFF, NULL, 0); 147 if (status == B_OK) { 148 //cpu_status state = disable_interrupts(); 149 status = acpi->enter_sleep_state(ACPI_POWER_STATE_OFF); 150 //restore_interrupts(state); 151 } 152 } 153 154 put_module(B_ACPI_MODULE_NAME); 155 return status; 156 } 157 158 159 /*! Disable CPU caches, and invalidate them. */ 160 static void 161 disable_caches() 162 { 163 x86_write_cr0((x86_read_cr0() | CR0_CACHE_DISABLE) 164 & ~CR0_NOT_WRITE_THROUGH); 165 wbinvd(); 166 arch_cpu_global_TLB_invalidate(); 167 } 168 169 170 /*! Invalidate CPU caches, and enable them. */ 171 static void 172 enable_caches() 173 { 174 wbinvd(); 175 arch_cpu_global_TLB_invalidate(); 176 x86_write_cr0(x86_read_cr0() 177 & ~(CR0_CACHE_DISABLE | CR0_NOT_WRITE_THROUGH)); 178 } 179 180 181 static void 182 set_mtrr(void* _parameter, int cpu) 183 { 184 struct set_mtrr_parameter* parameter 185 = (struct set_mtrr_parameter*)_parameter; 186 187 // wait until all CPUs have arrived here 188 smp_cpu_rendezvous(&sCpuRendezvous); 189 190 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 191 // that initiated the call_all_cpus() from doing that again and clearing 192 // sCpuRendezvous2 before the last CPU has actually left the loop in 193 // smp_cpu_rendezvous(); 194 if (cpu == 0) 195 atomic_set((int32*)&sCpuRendezvous3, 0); 196 197 disable_caches(); 198 199 sCpuModule->set_mtrr(parameter->index, parameter->base, parameter->length, 200 parameter->type); 201 202 enable_caches(); 203 204 // wait until all CPUs have arrived here 205 smp_cpu_rendezvous(&sCpuRendezvous2); 206 smp_cpu_rendezvous(&sCpuRendezvous3); 207 } 208 209 210 static void 211 set_mtrrs(void* _parameter, int cpu) 212 { 213 set_mtrrs_parameter* parameter = (set_mtrrs_parameter*)_parameter; 214 215 // wait until all CPUs have arrived here 216 smp_cpu_rendezvous(&sCpuRendezvous); 217 218 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 219 // that initiated the call_all_cpus() from doing that again and clearing 220 // sCpuRendezvous2 before the last CPU has actually left the loop in 221 // smp_cpu_rendezvous(); 222 if (cpu == 0) 223 atomic_set((int32*)&sCpuRendezvous3, 0); 224 225 disable_caches(); 226 227 sCpuModule->set_mtrrs(parameter->defaultType, parameter->infos, 228 parameter->count); 229 230 enable_caches(); 231 232 // wait until all CPUs have arrived here 233 smp_cpu_rendezvous(&sCpuRendezvous2); 234 smp_cpu_rendezvous(&sCpuRendezvous3); 235 } 236 237 238 static void 239 init_mtrrs(void* _unused, int cpu) 240 { 241 // wait until all CPUs have arrived here 242 smp_cpu_rendezvous(&sCpuRendezvous); 243 244 // One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU 245 // that initiated the call_all_cpus() from doing that again and clearing 246 // sCpuRendezvous2 before the last CPU has actually left the loop in 247 // smp_cpu_rendezvous(); 248 if (cpu == 0) 249 atomic_set((int32*)&sCpuRendezvous3, 0); 250 251 disable_caches(); 252 253 sCpuModule->init_mtrrs(); 254 255 enable_caches(); 256 257 // wait until all CPUs have arrived here 258 smp_cpu_rendezvous(&sCpuRendezvous2); 259 smp_cpu_rendezvous(&sCpuRendezvous3); 260 } 261 262 263 uint32 264 x86_count_mtrrs(void) 265 { 266 if (sCpuModule == NULL) 267 return 0; 268 269 return sCpuModule->count_mtrrs(); 270 } 271 272 273 void 274 x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type) 275 { 276 struct set_mtrr_parameter parameter; 277 parameter.index = index; 278 parameter.base = base; 279 parameter.length = length; 280 parameter.type = type; 281 282 sCpuRendezvous = sCpuRendezvous2 = 0; 283 call_all_cpus(&set_mtrr, ¶meter); 284 } 285 286 287 status_t 288 x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, uint8* _type) 289 { 290 // the MTRRs are identical on all CPUs, so it doesn't matter 291 // on which CPU this runs 292 return sCpuModule->get_mtrr(index, _base, _length, _type); 293 } 294 295 296 void 297 x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, uint32 count) 298 { 299 if (sCpuModule == NULL) 300 return; 301 302 struct set_mtrrs_parameter parameter; 303 parameter.defaultType = defaultType; 304 parameter.infos = infos; 305 parameter.count = count; 306 307 sCpuRendezvous = sCpuRendezvous2 = 0; 308 call_all_cpus(&set_mtrrs, ¶meter); 309 } 310 311 312 void 313 x86_init_fpu(void) 314 { 315 // All x86_64 CPUs support SSE, don't need to bother checking for it. 316 #ifndef __x86_64__ 317 if (!x86_check_feature(IA32_FEATURE_FPU, FEATURE_COMMON)) { 318 // No FPU... time to install one in your 386? 319 dprintf("%s: Warning: CPU has no reported FPU.\n", __func__); 320 gX86SwapFPUFunc = x86_noop_swap; 321 return; 322 } 323 324 if (!x86_check_feature(IA32_FEATURE_SSE, FEATURE_COMMON) 325 || !x86_check_feature(IA32_FEATURE_FXSR, FEATURE_COMMON)) { 326 dprintf("%s: CPU has no SSE... just enabling FPU.\n", __func__); 327 // we don't have proper SSE support, just enable FPU 328 x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU)); 329 gX86SwapFPUFunc = x86_fnsave_swap; 330 return; 331 } 332 #endif 333 334 dprintf("%s: CPU has SSE... enabling FXSR and XMM.\n", __func__); 335 #ifndef __x86_64__ 336 // enable OS support for SSE 337 x86_write_cr4(x86_read_cr4() | CR4_OS_FXSR | CR4_OS_XMM_EXCEPTION); 338 x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU)); 339 340 gX86SwapFPUFunc = x86_fxsave_swap; 341 gHasSSE = true; 342 #endif 343 } 344 345 346 #if DUMP_FEATURE_STRING 347 static void 348 dump_feature_string(int currentCPU, cpu_ent* cpu) 349 { 350 char features[512]; 351 features[0] = 0; 352 353 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FPU) 354 strlcat(features, "fpu ", sizeof(features)); 355 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_VME) 356 strlcat(features, "vme ", sizeof(features)); 357 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DE) 358 strlcat(features, "de ", sizeof(features)); 359 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE) 360 strlcat(features, "pse ", sizeof(features)); 361 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TSC) 362 strlcat(features, "tsc ", sizeof(features)); 363 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MSR) 364 strlcat(features, "msr ", sizeof(features)); 365 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAE) 366 strlcat(features, "pae ", sizeof(features)); 367 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCE) 368 strlcat(features, "mce ", sizeof(features)); 369 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CX8) 370 strlcat(features, "cx8 ", sizeof(features)); 371 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_APIC) 372 strlcat(features, "apic ", sizeof(features)); 373 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SEP) 374 strlcat(features, "sep ", sizeof(features)); 375 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MTRR) 376 strlcat(features, "mtrr ", sizeof(features)); 377 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PGE) 378 strlcat(features, "pge ", sizeof(features)); 379 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCA) 380 strlcat(features, "mca ", sizeof(features)); 381 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CMOV) 382 strlcat(features, "cmov ", sizeof(features)); 383 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAT) 384 strlcat(features, "pat ", sizeof(features)); 385 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE36) 386 strlcat(features, "pse36 ", sizeof(features)); 387 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSN) 388 strlcat(features, "psn ", sizeof(features)); 389 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CLFSH) 390 strlcat(features, "clfsh ", sizeof(features)); 391 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DS) 392 strlcat(features, "ds ", sizeof(features)); 393 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_ACPI) 394 strlcat(features, "acpi ", sizeof(features)); 395 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MMX) 396 strlcat(features, "mmx ", sizeof(features)); 397 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FXSR) 398 strlcat(features, "fxsr ", sizeof(features)); 399 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE) 400 strlcat(features, "sse ", sizeof(features)); 401 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE2) 402 strlcat(features, "sse2 ", sizeof(features)); 403 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SS) 404 strlcat(features, "ss ", sizeof(features)); 405 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_HTT) 406 strlcat(features, "htt ", sizeof(features)); 407 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TM) 408 strlcat(features, "tm ", sizeof(features)); 409 if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PBE) 410 strlcat(features, "pbe ", sizeof(features)); 411 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE3) 412 strlcat(features, "sse3 ", sizeof(features)); 413 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCLMULQDQ) 414 strlcat(features, "pclmulqdq ", sizeof(features)); 415 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DTES64) 416 strlcat(features, "dtes64 ", sizeof(features)); 417 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MONITOR) 418 strlcat(features, "monitor ", sizeof(features)); 419 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DSCPL) 420 strlcat(features, "dscpl ", sizeof(features)); 421 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_VMX) 422 strlcat(features, "vmx ", sizeof(features)); 423 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SMX) 424 strlcat(features, "smx ", sizeof(features)); 425 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_EST) 426 strlcat(features, "est ", sizeof(features)); 427 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TM2) 428 strlcat(features, "tm2 ", sizeof(features)); 429 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSSE3) 430 strlcat(features, "ssse3 ", sizeof(features)); 431 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CNXTID) 432 strlcat(features, "cnxtid ", sizeof(features)); 433 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_FMA) 434 strlcat(features, "fma ", sizeof(features)); 435 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CX16) 436 strlcat(features, "cx16 ", sizeof(features)); 437 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XTPR) 438 strlcat(features, "xtpr ", sizeof(features)); 439 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PDCM) 440 strlcat(features, "pdcm ", sizeof(features)); 441 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCID) 442 strlcat(features, "pcid ", sizeof(features)); 443 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DCA) 444 strlcat(features, "dca ", sizeof(features)); 445 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_1) 446 strlcat(features, "sse4_1 ", sizeof(features)); 447 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_2) 448 strlcat(features, "sse4_2 ", sizeof(features)); 449 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_X2APIC) 450 strlcat(features, "x2apic ", sizeof(features)); 451 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MOVBE) 452 strlcat(features, "movbe ", sizeof(features)); 453 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_POPCNT) 454 strlcat(features, "popcnt ", sizeof(features)); 455 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TSCDEADLINE) 456 strlcat(features, "tscdeadline ", sizeof(features)); 457 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AES) 458 strlcat(features, "aes ", sizeof(features)); 459 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XSAVE) 460 strlcat(features, "xsave ", sizeof(features)); 461 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_OSXSAVE) 462 strlcat(features, "osxsave ", sizeof(features)); 463 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AVX) 464 strlcat(features, "avx ", sizeof(features)); 465 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_F16C) 466 strlcat(features, "f16c ", sizeof(features)); 467 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_RDRND) 468 strlcat(features, "rdrnd ", sizeof(features)); 469 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) 470 strlcat(features, "hypervisor ", sizeof(features)); 471 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_SYSCALL) 472 strlcat(features, "syscall ", sizeof(features)); 473 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_NX) 474 strlcat(features, "nx ", sizeof(features)); 475 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_MMXEXT) 476 strlcat(features, "mmxext ", sizeof(features)); 477 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_FFXSR) 478 strlcat(features, "ffxsr ", sizeof(features)); 479 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_PDPE1GB) 480 strlcat(features, "pdpe1gb ", sizeof(features)); 481 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_LONG) 482 strlcat(features, "long ", sizeof(features)); 483 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOWEXT) 484 strlcat(features, "3dnowext ", sizeof(features)); 485 if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOW) 486 strlcat(features, "3dnow ", sizeof(features)); 487 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_DTS) 488 strlcat(features, "dts ", sizeof(features)); 489 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ITB) 490 strlcat(features, "itb ", sizeof(features)); 491 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ARAT) 492 strlcat(features, "arat ", sizeof(features)); 493 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PLN) 494 strlcat(features, "pln ", sizeof(features)); 495 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ECMD) 496 strlcat(features, "ecmd ", sizeof(features)); 497 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PTM) 498 strlcat(features, "ptm ", sizeof(features)); 499 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP) 500 strlcat(features, "hwp ", sizeof(features)); 501 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_NOTIFY) 502 strlcat(features, "hwp_notify ", sizeof(features)); 503 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_ACTWIN) 504 strlcat(features, "hwp_actwin ", sizeof(features)); 505 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_EPP) 506 strlcat(features, "hwp_epp ", sizeof(features)); 507 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PLR) 508 strlcat(features, "hwp_plr ", sizeof(features)); 509 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HDC) 510 strlcat(features, "hdc ", sizeof(features)); 511 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_TBMT3) 512 strlcat(features, "tbmt3 ", sizeof(features)); 513 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_CAP) 514 strlcat(features, "hwp_cap ", sizeof(features)); 515 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PECI) 516 strlcat(features, "hwp_peci ", sizeof(features)); 517 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FLEX) 518 strlcat(features, "hwp_flex ", sizeof(features)); 519 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FAST) 520 strlcat(features, "hwp_fast ", sizeof(features)); 521 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HW_FEEDBACK) 522 strlcat(features, "hw_feedback ", sizeof(features)); 523 if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_IGNIDL) 524 strlcat(features, "hwp_ignidl ", sizeof(features)); 525 if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_APERFMPERF) 526 strlcat(features, "aperfmperf ", sizeof(features)); 527 if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_EPB) 528 strlcat(features, "epb ", sizeof(features)); 529 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_TSC_ADJUST) 530 strlcat(features, "tsc_adjust ", sizeof(features)); 531 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SGX) 532 strlcat(features, "sgx ", sizeof(features)); 533 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI1) 534 strlcat(features, "bmi1 ", sizeof(features)); 535 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_HLE) 536 strlcat(features, "hle ", sizeof(features)); 537 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX2) 538 strlcat(features, "avx2 ", sizeof(features)); 539 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMEP) 540 strlcat(features, "smep ", sizeof(features)); 541 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI2) 542 strlcat(features, "bmi2 ", sizeof(features)); 543 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ERMS) 544 strlcat(features, "erms ", sizeof(features)); 545 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INVPCID) 546 strlcat(features, "invpcid ", sizeof(features)); 547 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RTM) 548 strlcat(features, "rtm ", sizeof(features)); 549 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CQM) 550 strlcat(features, "cqm ", sizeof(features)); 551 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_MPX) 552 strlcat(features, "mpx ", sizeof(features)); 553 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDT_A) 554 strlcat(features, "rdt_a ", sizeof(features)); 555 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512F) 556 strlcat(features, "avx512f ", sizeof(features)); 557 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512DQ) 558 strlcat(features, "avx512dq ", sizeof(features)); 559 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDSEED) 560 strlcat(features, "rdseed ", sizeof(features)); 561 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ADX) 562 strlcat(features, "adx ", sizeof(features)); 563 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMAP) 564 strlcat(features, "smap ", sizeof(features)); 565 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512IFMA) 566 strlcat(features, "avx512ifma ", sizeof(features)); 567 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_PCOMMIT) 568 strlcat(features, "pcommit ", sizeof(features)); 569 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLFLUSHOPT) 570 strlcat(features, "cflushopt ", sizeof(features)); 571 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLWB) 572 strlcat(features, "clwb ", sizeof(features)); 573 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INTEL_PT) 574 strlcat(features, "intel_pt ", sizeof(features)); 575 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512PF) 576 strlcat(features, "avx512pf ", sizeof(features)); 577 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512ER) 578 strlcat(features, "avx512er ", sizeof(features)); 579 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512CD) 580 strlcat(features, "avx512cd ", sizeof(features)); 581 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SHA_NI) 582 strlcat(features, "sha_ni ", sizeof(features)); 583 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512BW) 584 strlcat(features, "avx512bw ", sizeof(features)); 585 if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512VI) 586 strlcat(features, "avx512vi ", sizeof(features)); 587 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI) 588 strlcat(features, "avx512vmbi ", sizeof(features)); 589 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_UMIP) 590 strlcat(features, "umip ", sizeof(features)); 591 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_PKU) 592 strlcat(features, "pku ", sizeof(features)); 593 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_OSPKE) 594 strlcat(features, "ospke ", sizeof(features)); 595 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI2) 596 strlcat(features, "avx512vmbi2 ", sizeof(features)); 597 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_GFNI) 598 strlcat(features, "gfni ", sizeof(features)); 599 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VAES) 600 strlcat(features, "vaes ", sizeof(features)); 601 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VPCLMULQDQ) 602 strlcat(features, "vpclmulqdq ", sizeof(features)); 603 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VNNI) 604 strlcat(features, "avx512vnni ", sizeof(features)); 605 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_BITALG) 606 strlcat(features, "avx512bitalg ", sizeof(features)); 607 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VPOPCNTDQ) 608 strlcat(features, "avx512vpopcntdq ", sizeof(features)); 609 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_LA57) 610 strlcat(features, "la57 ", sizeof(features)); 611 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_RDPID) 612 strlcat(features, "rdpid ", sizeof(features)); 613 if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_SGX_LC) 614 strlcat(features, "sgx_lc ", sizeof(features)); 615 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_IBRS) 616 strlcat(features, "ibrs ", sizeof(features)); 617 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_STIBP) 618 strlcat(features, "stibp ", sizeof(features)); 619 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_L1D_FLUSH) 620 strlcat(features, "l1d_flush ", sizeof(features)); 621 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_ARCH_CAPABILITIES) 622 strlcat(features, "msr_arch ", sizeof(features)); 623 if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_SSBD) 624 strlcat(features, "ssbd ", sizeof(features)); 625 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEOPT) 626 strlcat(features, "xsaveopt ", sizeof(features)); 627 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEC) 628 strlcat(features, "xsavec ", sizeof(features)); 629 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XGETBV1) 630 strlcat(features, "xgetbv1 ", sizeof(features)); 631 if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVES) 632 strlcat(features, "xsaves ", sizeof(features)); 633 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_CLZERO) 634 strlcat(features, "clzero ", sizeof(features)); 635 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_IBPB) 636 strlcat(features, "ibpb ", sizeof(features)); 637 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSBD) 638 strlcat(features, "amd_ssbd ", sizeof(features)); 639 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_VIRT_SSBD) 640 strlcat(features, "virt_ssbd ", sizeof(features)); 641 if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSB_NO) 642 strlcat(features, "amd_ssb_no ", sizeof(features)); 643 dprintf("CPU %d: features: %s\n", currentCPU, features); 644 } 645 #endif // DUMP_FEATURE_STRING 646 647 648 static void 649 compute_cpu_hierarchy_masks(int maxLogicalID, int maxCoreID) 650 { 651 ASSERT(maxLogicalID >= maxCoreID); 652 const int kMaxSMTID = maxLogicalID / maxCoreID; 653 654 sHierarchyMask[CPU_TOPOLOGY_SMT] = kMaxSMTID - 1; 655 sHierarchyShift[CPU_TOPOLOGY_SMT] = 0; 656 657 sHierarchyMask[CPU_TOPOLOGY_CORE] = (maxCoreID - 1) * kMaxSMTID; 658 sHierarchyShift[CPU_TOPOLOGY_CORE] 659 = count_set_bits(sHierarchyMask[CPU_TOPOLOGY_SMT]); 660 661 const uint32 kSinglePackageMask = sHierarchyMask[CPU_TOPOLOGY_SMT] 662 | sHierarchyMask[CPU_TOPOLOGY_CORE]; 663 sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~kSinglePackageMask; 664 sHierarchyShift[CPU_TOPOLOGY_PACKAGE] = count_set_bits(kSinglePackageMask); 665 } 666 667 668 static uint32 669 get_cpu_legacy_initial_apic_id(int /* currentCPU */) 670 { 671 cpuid_info cpuid; 672 get_current_cpuid(&cpuid, 1, 0); 673 return cpuid.regs.ebx >> 24; 674 } 675 676 677 static inline status_t 678 detect_amd_cpu_topology(uint32 maxBasicLeaf, uint32 maxExtendedLeaf) 679 { 680 sGetCPUTopologyID = get_cpu_legacy_initial_apic_id; 681 682 cpuid_info cpuid; 683 get_current_cpuid(&cpuid, 1, 0); 684 int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff); 685 686 int maxCoreID = 1; 687 if (maxExtendedLeaf >= 0x80000008) { 688 get_current_cpuid(&cpuid, 0x80000008, 0); 689 maxCoreID = (cpuid.regs.ecx >> 12) & 0xf; 690 if (maxCoreID != 0) 691 maxCoreID = 1 << maxCoreID; 692 else 693 maxCoreID = next_power_of_2((cpuid.regs.edx & 0xf) + 1); 694 } 695 696 if (maxExtendedLeaf >= 0x80000001) { 697 get_current_cpuid(&cpuid, 0x80000001, 0); 698 if (x86_check_feature(IA32_FEATURE_AMD_EXT_CMPLEGACY, 699 FEATURE_EXT_AMD_ECX)) 700 maxCoreID = maxLogicalID; 701 } 702 703 compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID); 704 705 return B_OK; 706 } 707 708 709 static void 710 detect_amd_cache_topology(uint32 maxExtendedLeaf) 711 { 712 if (!x86_check_feature(IA32_FEATURE_AMD_EXT_TOPOLOGY, FEATURE_EXT_AMD_ECX)) 713 return; 714 715 if (maxExtendedLeaf < 0x8000001d) 716 return; 717 718 uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL]; 719 int maxCacheLevel = 0; 720 721 int currentLevel = 0; 722 int cacheType; 723 do { 724 cpuid_info cpuid; 725 get_current_cpuid(&cpuid, 0x8000001d, currentLevel); 726 727 cacheType = cpuid.regs.eax & 0x1f; 728 if (cacheType == 0) 729 break; 730 731 int cacheLevel = (cpuid.regs.eax >> 5) & 0x7; 732 int coresCount = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1); 733 hierarchyLevels[cacheLevel - 1] 734 = coresCount * (sHierarchyMask[CPU_TOPOLOGY_SMT] + 1); 735 maxCacheLevel = std::max(maxCacheLevel, cacheLevel); 736 737 currentLevel++; 738 } while (true); 739 740 for (int i = 0; i < maxCacheLevel; i++) 741 sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1); 742 gCPUCacheLevelCount = maxCacheLevel; 743 } 744 745 746 static uint32 747 get_intel_cpu_initial_x2apic_id(int /* currentCPU */) 748 { 749 cpuid_info cpuid; 750 get_current_cpuid(&cpuid, 11, 0); 751 return cpuid.regs.edx; 752 } 753 754 755 static inline status_t 756 detect_intel_cpu_topology_x2apic(uint32 maxBasicLeaf) 757 { 758 759 uint32 leaf = 0; 760 cpuid_info cpuid; 761 if (maxBasicLeaf >= 0x1f) { 762 get_current_cpuid(&cpuid, 0x1f, 0); 763 if (cpuid.regs.ebx != 0) 764 leaf = 0x1f; 765 } 766 if (maxBasicLeaf >= 0xb && leaf == 0) { 767 get_current_cpuid(&cpuid, 0xb, 0); 768 if (cpuid.regs.ebx != 0) 769 leaf = 0xb; 770 } 771 if (leaf == 0) 772 return B_UNSUPPORTED; 773 774 uint8 hierarchyLevels[CPU_TOPOLOGY_LEVELS] = { 0 }; 775 776 int currentLevel = 0; 777 unsigned int levelsSet = 0; 778 do { 779 cpuid_info cpuid; 780 get_current_cpuid(&cpuid, leaf, currentLevel++); 781 int levelType = (cpuid.regs.ecx >> 8) & 0xff; 782 int levelValue = cpuid.regs.eax & 0x1f; 783 784 if (levelType == 0) 785 break; 786 787 switch (levelType) { 788 case 1: // SMT 789 hierarchyLevels[CPU_TOPOLOGY_SMT] = levelValue; 790 levelsSet |= 1; 791 break; 792 case 2: // core 793 hierarchyLevels[CPU_TOPOLOGY_CORE] = levelValue; 794 levelsSet |= 2; 795 break; 796 } 797 798 } while (levelsSet != 3); 799 800 sGetCPUTopologyID = get_intel_cpu_initial_x2apic_id; 801 802 for (int i = 1; i < CPU_TOPOLOGY_LEVELS; i++) { 803 if ((levelsSet & (1u << i)) != 0) 804 continue; 805 hierarchyLevels[i] = hierarchyLevels[i - 1]; 806 } 807 808 for (int i = 0; i < CPU_TOPOLOGY_LEVELS; i++) { 809 uint32 mask = ~uint32(0); 810 if (i < CPU_TOPOLOGY_LEVELS - 1) 811 mask = (1u << hierarchyLevels[i]) - 1; 812 if (i > 0) 813 mask &= ~sHierarchyMask[i - 1]; 814 sHierarchyMask[i] = mask; 815 sHierarchyShift[i] = i > 0 ? hierarchyLevels[i - 1] : 0; 816 } 817 818 return B_OK; 819 } 820 821 822 static inline status_t 823 detect_intel_cpu_topology_legacy(uint32 maxBasicLeaf) 824 { 825 sGetCPUTopologyID = get_cpu_legacy_initial_apic_id; 826 827 cpuid_info cpuid; 828 829 get_current_cpuid(&cpuid, 1, 0); 830 int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff); 831 832 int maxCoreID = 1; 833 if (maxBasicLeaf >= 4) { 834 get_current_cpuid(&cpuid, 4, 0); 835 maxCoreID = next_power_of_2((cpuid.regs.eax >> 26) + 1); 836 } 837 838 compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID); 839 840 return B_OK; 841 } 842 843 844 static void 845 detect_intel_cache_topology(uint32 maxBasicLeaf) 846 { 847 if (maxBasicLeaf < 4) 848 return; 849 850 uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL]; 851 int maxCacheLevel = 0; 852 853 int currentLevel = 0; 854 int cacheType; 855 do { 856 cpuid_info cpuid; 857 get_current_cpuid(&cpuid, 4, currentLevel); 858 859 cacheType = cpuid.regs.eax & 0x1f; 860 if (cacheType == 0) 861 break; 862 863 int cacheLevel = (cpuid.regs.eax >> 5) & 0x7; 864 hierarchyLevels[cacheLevel - 1] 865 = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1); 866 maxCacheLevel = std::max(maxCacheLevel, cacheLevel); 867 868 currentLevel++; 869 } while (true); 870 871 for (int i = 0; i < maxCacheLevel; i++) 872 sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1); 873 874 gCPUCacheLevelCount = maxCacheLevel; 875 } 876 877 878 static uint32 879 get_simple_cpu_topology_id(int currentCPU) 880 { 881 return currentCPU; 882 } 883 884 885 static inline int 886 get_topology_level_id(uint32 id, cpu_topology_level level) 887 { 888 ASSERT(level < CPU_TOPOLOGY_LEVELS); 889 return (id & sHierarchyMask[level]) >> sHierarchyShift[level]; 890 } 891 892 893 static void 894 detect_cpu_topology(int currentCPU, cpu_ent* cpu, uint32 maxBasicLeaf, 895 uint32 maxExtendedLeaf) 896 { 897 if (currentCPU == 0) { 898 memset(sCacheSharingMask, 0xff, sizeof(sCacheSharingMask)); 899 900 status_t result = B_UNSUPPORTED; 901 if (x86_check_feature(IA32_FEATURE_HTT, FEATURE_COMMON)) { 902 if (cpu->arch.vendor == VENDOR_AMD 903 || cpu->arch.vendor == VENDOR_HYGON) { 904 result = detect_amd_cpu_topology(maxBasicLeaf, maxExtendedLeaf); 905 906 if (result == B_OK) 907 detect_amd_cache_topology(maxExtendedLeaf); 908 } 909 910 if (cpu->arch.vendor == VENDOR_INTEL) { 911 result = detect_intel_cpu_topology_x2apic(maxBasicLeaf); 912 if (result != B_OK) 913 result = detect_intel_cpu_topology_legacy(maxBasicLeaf); 914 915 if (result == B_OK) 916 detect_intel_cache_topology(maxBasicLeaf); 917 } 918 } 919 920 if (result != B_OK) { 921 dprintf("No CPU topology information available.\n"); 922 923 sGetCPUTopologyID = get_simple_cpu_topology_id; 924 925 sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~uint32(0); 926 } 927 } 928 929 ASSERT(sGetCPUTopologyID != NULL); 930 int topologyID = sGetCPUTopologyID(currentCPU); 931 cpu->topology_id[CPU_TOPOLOGY_SMT] 932 = get_topology_level_id(topologyID, CPU_TOPOLOGY_SMT); 933 cpu->topology_id[CPU_TOPOLOGY_CORE] 934 = get_topology_level_id(topologyID, CPU_TOPOLOGY_CORE); 935 cpu->topology_id[CPU_TOPOLOGY_PACKAGE] 936 = get_topology_level_id(topologyID, CPU_TOPOLOGY_PACKAGE); 937 938 unsigned int i; 939 for (i = 0; i < gCPUCacheLevelCount; i++) 940 cpu->cache_id[i] = topologyID & sCacheSharingMask[i]; 941 for (; i < CPU_MAX_CACHE_LEVEL; i++) 942 cpu->cache_id[i] = -1; 943 944 #if DUMP_CPU_TOPOLOGY 945 dprintf("CPU %d: apic id %d, package %d, core %d, smt %d\n", currentCPU, 946 topologyID, cpu->topology_id[CPU_TOPOLOGY_PACKAGE], 947 cpu->topology_id[CPU_TOPOLOGY_CORE], 948 cpu->topology_id[CPU_TOPOLOGY_SMT]); 949 950 if (gCPUCacheLevelCount > 0) { 951 char cacheLevels[256]; 952 unsigned int offset = 0; 953 for (i = 0; i < gCPUCacheLevelCount; i++) { 954 offset += snprintf(cacheLevels + offset, 955 sizeof(cacheLevels) - offset, 956 " L%d id %d%s", i + 1, cpu->cache_id[i], 957 i < gCPUCacheLevelCount - 1 ? "," : ""); 958 959 if (offset >= sizeof(cacheLevels)) 960 break; 961 } 962 963 dprintf("CPU %d: cache sharing:%s\n", currentCPU, cacheLevels); 964 } 965 #endif 966 } 967 968 969 static void 970 detect_intel_patch_level(cpu_ent* cpu) 971 { 972 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) { 973 cpu->arch.patch_level = 0; 974 return; 975 } 976 977 x86_write_msr(IA32_MSR_UCODE_REV, 0); 978 cpuid_info cpuid; 979 get_current_cpuid(&cpuid, 1, 0); 980 981 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV); 982 cpu->arch.patch_level = value >> 32; 983 } 984 985 986 static void 987 detect_amd_patch_level(cpu_ent* cpu) 988 { 989 if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) { 990 cpu->arch.patch_level = 0; 991 return; 992 } 993 994 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV); 995 cpu->arch.patch_level = value >> 32; 996 } 997 998 999 static struct intel_microcode_header* 1000 find_microcode_intel(addr_t data, size_t size, uint32 patchLevel) 1001 { 1002 // 9.11.3 Processor Identification 1003 cpuid_info cpuid; 1004 get_current_cpuid(&cpuid, 1, 0); 1005 uint32 signature = cpuid.regs.eax; 1006 // 9.11.4 Platform Identification 1007 uint64 platformBits = (x86_read_msr(IA32_MSR_PLATFORM_ID) >> 50) & 0x7; 1008 uint64 mask = 1 << platformBits; 1009 1010 while (size > 0) { 1011 if (size < sizeof(struct intel_microcode_header)) { 1012 dprintf("find_microcode_intel update is too small for header\n"); 1013 break; 1014 } 1015 struct intel_microcode_header* header = 1016 (struct intel_microcode_header*)data; 1017 1018 uint32 totalSize = header->total_size; 1019 uint32 dataSize = header->data_size; 1020 if (dataSize == 0) { 1021 dataSize = 2000; 1022 totalSize = sizeof(struct intel_microcode_header) 1023 + dataSize; 1024 } 1025 if (totalSize > size) { 1026 dprintf("find_microcode_intel update is too small for data\n"); 1027 break; 1028 } 1029 1030 uint32* dwords = (uint32*)data; 1031 // prepare the next update 1032 size -= totalSize; 1033 data += totalSize; 1034 1035 if (header->loader_revision != 1) { 1036 dprintf("find_microcode_intel incorrect loader version\n"); 1037 continue; 1038 } 1039 // 9.11.6 The microcode update data requires a 16-byte boundary 1040 // alignment. 1041 if (((addr_t)header % 16) != 0) { 1042 dprintf("find_microcode_intel incorrect alignment\n"); 1043 continue; 1044 } 1045 uint32 sum = 0; 1046 for (uint32 i = 0; i < totalSize / 4; i++) { 1047 sum += dwords[i]; 1048 } 1049 if (sum != 0) { 1050 dprintf("find_microcode_intel incorrect checksum\n"); 1051 continue; 1052 } 1053 if (patchLevel > header->update_revision) { 1054 dprintf("find_microcode_intel update_revision is lower\n"); 1055 continue; 1056 } 1057 if (signature == header->processor_signature 1058 && (mask & header->processor_flags) != 0) { 1059 return header; 1060 } 1061 if (totalSize <= (sizeof(struct intel_microcode_header) + dataSize 1062 + sizeof(struct intel_microcode_extended_signature_header))) { 1063 continue; 1064 } 1065 struct intel_microcode_extended_signature_header* extSigHeader = 1066 (struct intel_microcode_extended_signature_header*)((addr_t)header 1067 + sizeof(struct intel_microcode_header) + dataSize); 1068 struct intel_microcode_extended_signature* extended_signature = 1069 (struct intel_microcode_extended_signature*)((addr_t)extSigHeader 1070 + sizeof(struct intel_microcode_extended_signature_header)); 1071 for (uint32 i = 0; i < extSigHeader->extended_signature_count; i++) { 1072 if (signature == extended_signature[i].processor_signature 1073 && (mask & extended_signature[i].processor_flags) != 0) 1074 return header; 1075 } 1076 } 1077 return NULL; 1078 } 1079 1080 1081 static void 1082 load_microcode_intel(int currentCPU, cpu_ent* cpu) 1083 { 1084 // serialize for HT cores 1085 if (currentCPU != 0) 1086 acquire_spinlock(&sUcodeUpdateLock); 1087 detect_intel_patch_level(cpu); 1088 uint32 revision = cpu->arch.patch_level; 1089 struct intel_microcode_header* update = sLoadedUcodeUpdate; 1090 if (update == NULL) { 1091 update = find_microcode_intel((addr_t)sUcodeData, sUcodeDataSize, 1092 revision); 1093 } 1094 if (update != NULL) { 1095 addr_t data = (addr_t)update + sizeof(struct intel_microcode_header); 1096 wbinvd(); 1097 x86_write_msr(IA32_MSR_UCODE_WRITE, data); 1098 detect_intel_patch_level(cpu); 1099 if (revision == cpu->arch.patch_level) { 1100 dprintf("CPU %d: update failed\n", currentCPU); 1101 } else { 1102 if (sLoadedUcodeUpdate == NULL) 1103 sLoadedUcodeUpdate = update; 1104 dprintf("CPU %d: updated from revision %" B_PRIu32 " to %" B_PRIu32 1105 "\n", currentCPU, revision, cpu->arch.patch_level); 1106 } 1107 } else { 1108 dprintf("CPU %d: no update found\n", currentCPU); 1109 } 1110 if (currentCPU != 0) 1111 release_spinlock(&sUcodeUpdateLock); 1112 } 1113 1114 1115 static void 1116 load_microcode_amd(int currentCPU, cpu_ent* cpu) 1117 { 1118 dprintf("CPU %d: no update found\n", currentCPU); 1119 } 1120 1121 1122 static void 1123 load_microcode(int currentCPU) 1124 { 1125 if (sUcodeData == NULL) 1126 return; 1127 cpu_ent* cpu = get_cpu_struct(); 1128 if ((cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) != 0) 1129 return; 1130 if (cpu->arch.vendor == VENDOR_INTEL) 1131 load_microcode_intel(currentCPU, cpu); 1132 else if (cpu->arch.vendor == VENDOR_AMD) 1133 load_microcode_amd(currentCPU, cpu); 1134 } 1135 1136 1137 static void 1138 detect_cpu(int currentCPU) 1139 { 1140 cpu_ent* cpu = get_cpu_struct(); 1141 char vendorString[17]; 1142 cpuid_info cpuid; 1143 1144 // clear out the cpu info data 1145 cpu->arch.vendor = VENDOR_UNKNOWN; 1146 cpu->arch.vendor_name = "UNKNOWN VENDOR"; 1147 cpu->arch.feature[FEATURE_COMMON] = 0; 1148 cpu->arch.feature[FEATURE_EXT] = 0; 1149 cpu->arch.feature[FEATURE_EXT_AMD] = 0; 1150 cpu->arch.feature[FEATURE_7_EBX] = 0; 1151 cpu->arch.feature[FEATURE_7_ECX] = 0; 1152 cpu->arch.feature[FEATURE_7_EDX] = 0; 1153 cpu->arch.feature[FEATURE_D_1_EAX] = 0; 1154 cpu->arch.model_name[0] = 0; 1155 1156 // print some fun data 1157 get_current_cpuid(&cpuid, 0, 0); 1158 uint32 maxBasicLeaf = cpuid.eax_0.max_eax; 1159 1160 // build the vendor string 1161 memset(vendorString, 0, sizeof(vendorString)); 1162 memcpy(vendorString, cpuid.eax_0.vendor_id, sizeof(cpuid.eax_0.vendor_id)); 1163 1164 // get the family, model, stepping 1165 get_current_cpuid(&cpuid, 1, 0); 1166 cpu->arch.type = cpuid.eax_1.type; 1167 cpu->arch.family = cpuid.eax_1.family; 1168 cpu->arch.extended_family = cpuid.eax_1.extended_family; 1169 cpu->arch.model = cpuid.eax_1.model; 1170 cpu->arch.extended_model = cpuid.eax_1.extended_model; 1171 cpu->arch.stepping = cpuid.eax_1.stepping; 1172 dprintf("CPU %d: type %d family %d extended_family %d model %d " 1173 "extended_model %d stepping %d, string '%s'\n", 1174 currentCPU, cpu->arch.type, cpu->arch.family, 1175 cpu->arch.extended_family, cpu->arch.model, 1176 cpu->arch.extended_model, cpu->arch.stepping, vendorString); 1177 1178 // figure out what vendor we have here 1179 1180 for (int32 i = 0; i < VENDOR_NUM; i++) { 1181 if (vendor_info[i].ident_string[0] 1182 && !strcmp(vendorString, vendor_info[i].ident_string[0])) { 1183 cpu->arch.vendor = (x86_vendors)i; 1184 cpu->arch.vendor_name = vendor_info[i].vendor; 1185 break; 1186 } 1187 if (vendor_info[i].ident_string[1] 1188 && !strcmp(vendorString, vendor_info[i].ident_string[1])) { 1189 cpu->arch.vendor = (x86_vendors)i; 1190 cpu->arch.vendor_name = vendor_info[i].vendor; 1191 break; 1192 } 1193 } 1194 1195 // see if we can get the model name 1196 get_current_cpuid(&cpuid, 0x80000000, 0); 1197 uint32 maxExtendedLeaf = cpuid.eax_0.max_eax; 1198 if (maxExtendedLeaf >= 0x80000004) { 1199 // build the model string (need to swap ecx/edx data before copying) 1200 unsigned int temp; 1201 memset(cpu->arch.model_name, 0, sizeof(cpu->arch.model_name)); 1202 1203 get_current_cpuid(&cpuid, 0x80000002, 0); 1204 temp = cpuid.regs.edx; 1205 cpuid.regs.edx = cpuid.regs.ecx; 1206 cpuid.regs.ecx = temp; 1207 memcpy(cpu->arch.model_name, cpuid.as_chars, sizeof(cpuid.as_chars)); 1208 1209 get_current_cpuid(&cpuid, 0x80000003, 0); 1210 temp = cpuid.regs.edx; 1211 cpuid.regs.edx = cpuid.regs.ecx; 1212 cpuid.regs.ecx = temp; 1213 memcpy(cpu->arch.model_name + 16, cpuid.as_chars, 1214 sizeof(cpuid.as_chars)); 1215 1216 get_current_cpuid(&cpuid, 0x80000004, 0); 1217 temp = cpuid.regs.edx; 1218 cpuid.regs.edx = cpuid.regs.ecx; 1219 cpuid.regs.ecx = temp; 1220 memcpy(cpu->arch.model_name + 32, cpuid.as_chars, 1221 sizeof(cpuid.as_chars)); 1222 1223 // some cpus return a right-justified string 1224 int32 i = 0; 1225 while (cpu->arch.model_name[i] == ' ') 1226 i++; 1227 if (i > 0) { 1228 memmove(cpu->arch.model_name, &cpu->arch.model_name[i], 1229 strlen(&cpu->arch.model_name[i]) + 1); 1230 } 1231 1232 dprintf("CPU %d: vendor '%s' model name '%s'\n", 1233 currentCPU, cpu->arch.vendor_name, cpu->arch.model_name); 1234 } else { 1235 strlcpy(cpu->arch.model_name, "unknown", sizeof(cpu->arch.model_name)); 1236 } 1237 1238 // load feature bits 1239 get_current_cpuid(&cpuid, 1, 0); 1240 cpu->arch.feature[FEATURE_COMMON] = cpuid.eax_1.features; // edx 1241 cpu->arch.feature[FEATURE_EXT] = cpuid.eax_1.extended_features; // ecx 1242 1243 if (maxExtendedLeaf >= 0x80000001) { 1244 get_current_cpuid(&cpuid, 0x80000001, 0); 1245 if (cpu->arch.vendor == VENDOR_AMD) 1246 cpu->arch.feature[FEATURE_EXT_AMD_ECX] = cpuid.regs.ecx; // ecx 1247 cpu->arch.feature[FEATURE_EXT_AMD] = cpuid.regs.edx; // edx 1248 if (cpu->arch.vendor != VENDOR_AMD) 1249 cpu->arch.feature[FEATURE_EXT_AMD] &= IA32_FEATURES_INTEL_EXT; 1250 } 1251 1252 if (maxBasicLeaf >= 5) { 1253 get_current_cpuid(&cpuid, 5, 0); 1254 cpu->arch.feature[FEATURE_5_ECX] = cpuid.regs.ecx; 1255 } 1256 1257 if (maxBasicLeaf >= 6) { 1258 get_current_cpuid(&cpuid, 6, 0); 1259 cpu->arch.feature[FEATURE_6_EAX] = cpuid.regs.eax; 1260 cpu->arch.feature[FEATURE_6_ECX] = cpuid.regs.ecx; 1261 } 1262 1263 if (maxBasicLeaf >= 7) { 1264 get_current_cpuid(&cpuid, 7, 0); 1265 cpu->arch.feature[FEATURE_7_EBX] = cpuid.regs.ebx; 1266 cpu->arch.feature[FEATURE_7_ECX] = cpuid.regs.ecx; 1267 cpu->arch.feature[FEATURE_7_EDX] = cpuid.regs.edx; 1268 } 1269 1270 if (maxBasicLeaf >= 0xd) { 1271 get_current_cpuid(&cpuid, 0xd, 1); 1272 cpu->arch.feature[FEATURE_D_1_EAX] = cpuid.regs.eax; 1273 } 1274 1275 if (maxExtendedLeaf >= 0x80000007) { 1276 get_current_cpuid(&cpuid, 0x80000007, 0); 1277 cpu->arch.feature[FEATURE_EXT_7_EDX] = cpuid.regs.edx; 1278 } 1279 1280 if (maxExtendedLeaf >= 0x80000008) { 1281 get_current_cpuid(&cpuid, 0x80000008, 0); 1282 cpu->arch.feature[FEATURE_EXT_8_EBX] = cpuid.regs.ebx; 1283 } 1284 1285 detect_cpu_topology(currentCPU, cpu, maxBasicLeaf, maxExtendedLeaf); 1286 1287 if (cpu->arch.vendor == VENDOR_INTEL) 1288 detect_intel_patch_level(cpu); 1289 else if (cpu->arch.vendor == VENDOR_AMD) 1290 detect_amd_patch_level(cpu); 1291 1292 #if DUMP_FEATURE_STRING 1293 dump_feature_string(currentCPU, cpu); 1294 #endif 1295 #if DUMP_CPU_PATCHLEVEL 1296 dprintf("CPU %d: patch_level %" B_PRIu32 "\n", currentCPU, 1297 cpu->arch.patch_level); 1298 #endif 1299 } 1300 1301 1302 bool 1303 x86_check_feature(uint32 feature, enum x86_feature_type type) 1304 { 1305 cpu_ent* cpu = get_cpu_struct(); 1306 1307 #if 0 1308 int i; 1309 dprintf("x86_check_feature: feature 0x%x, type %d\n", feature, type); 1310 for (i = 0; i < FEATURE_NUM; i++) { 1311 dprintf("features %d: 0x%x\n", i, cpu->arch.feature[i]); 1312 } 1313 #endif 1314 1315 return (cpu->arch.feature[type] & feature) != 0; 1316 } 1317 1318 1319 void* 1320 x86_get_double_fault_stack(int32 cpu, size_t* _size) 1321 { 1322 *_size = kDoubleFaultStackSize; 1323 return sDoubleFaultStacks + kDoubleFaultStackSize * cpu; 1324 } 1325 1326 1327 /*! Returns the index of the current CPU. Can only be called from the double 1328 fault handler. 1329 */ 1330 int32 1331 x86_double_fault_get_cpu(void) 1332 { 1333 addr_t stack = x86_get_stack_frame(); 1334 return (stack - (addr_t)sDoubleFaultStacks) / kDoubleFaultStackSize; 1335 } 1336 1337 1338 // #pragma mark - 1339 1340 1341 status_t 1342 arch_cpu_preboot_init_percpu(kernel_args* args, int cpu) 1343 { 1344 // On SMP system we want to synchronize the CPUs' TSCs, so system_time() 1345 // will return consistent values. 1346 if (smp_get_num_cpus() > 1) { 1347 // let the first CPU prepare the rendezvous point 1348 if (cpu == 0) 1349 sTSCSyncRendezvous = smp_get_num_cpus() - 1; 1350 1351 // One CPU after the other will drop out of this loop and be caught by 1352 // the loop below, until the last CPU (0) gets there. Save for +/- a few 1353 // cycles the CPUs should pass the second loop at the same time. 1354 while (sTSCSyncRendezvous != cpu) { 1355 } 1356 1357 sTSCSyncRendezvous = cpu - 1; 1358 1359 while (sTSCSyncRendezvous != -1) { 1360 } 1361 1362 // reset TSC to 0 1363 x86_write_msr(IA32_MSR_TSC, 0); 1364 } 1365 1366 x86_descriptors_preboot_init_percpu(args, cpu); 1367 1368 return B_OK; 1369 } 1370 1371 1372 static void 1373 halt_idle(void) 1374 { 1375 asm("hlt"); 1376 } 1377 1378 1379 static void 1380 amdc1e_noarat_idle(void) 1381 { 1382 uint64 msr = x86_read_msr(K8_MSR_IPM); 1383 if (msr & K8_CMPHALT) 1384 x86_write_msr(K8_MSR_IPM, msr & ~K8_CMPHALT); 1385 halt_idle(); 1386 } 1387 1388 1389 static bool 1390 detect_amdc1e_noarat() 1391 { 1392 cpu_ent* cpu = get_cpu_struct(); 1393 1394 if (cpu->arch.vendor != VENDOR_AMD) 1395 return false; 1396 1397 // Family 0x12 and higher processors support ARAT 1398 // Family lower than 0xf processors doesn't support C1E 1399 // Family 0xf with model <= 0x40 procssors doesn't support C1E 1400 uint32 family = cpu->arch.family + cpu->arch.extended_family; 1401 uint32 model = (cpu->arch.extended_model << 4) | cpu->arch.model; 1402 return (family < 0x12 && family > 0xf) || (family == 0xf && model > 0x40); 1403 } 1404 1405 1406 static void 1407 init_tsc_with_cpuid(kernel_args* args, uint32* conversionFactor) 1408 { 1409 cpu_ent* cpu = get_cpu_struct(); 1410 if (cpu->arch.vendor != VENDOR_INTEL) 1411 return; 1412 uint32 model = (cpu->arch.extended_model << 4) | cpu->arch.model; 1413 cpuid_info cpuid; 1414 get_current_cpuid(&cpuid, 0, 0); 1415 uint32 maxBasicLeaf = cpuid.eax_0.max_eax; 1416 if (maxBasicLeaf < 0x15) 1417 return; 1418 1419 get_current_cpuid(&cpuid, 0x15, 0); 1420 if (cpuid.regs.eax == 0 || cpuid.regs.ebx == 0) 1421 return; 1422 uint32 khz = cpuid.regs.ecx / 1000; 1423 uint32 denominator = cpuid.regs.eax; 1424 uint32 numerator = cpuid.regs.ebx; 1425 if (khz == 0 && model == 0x5f) { 1426 // CPUID 0x16 isn't supported, hardcoding 1427 khz = 25000; 1428 } 1429 1430 if (khz == 0 && maxBasicLeaf >= 0x16) { 1431 // for these CPUs the base frequency is also the tsc frequency 1432 get_current_cpuid(&cpuid, 0x16, 0); 1433 khz = cpuid.regs.eax * 1000 * denominator / numerator; 1434 } 1435 if (khz == 0) 1436 return; 1437 dprintf("CPU: using TSC frequency from CPUID\n"); 1438 // compute for microseconds as follows (1000000 << 32) / (tsc freq in Hz), 1439 // or (1000 << 32) / (tsc freq in kHz) 1440 *conversionFactor = (1000ULL << 32) / (khz * numerator / denominator); 1441 // overwrite the bootloader value 1442 args->arch_args.system_time_cv_factor = *conversionFactor; 1443 } 1444 1445 1446 static void 1447 init_tsc_with_msr(kernel_args* args, uint32* conversionFactor) 1448 { 1449 cpu_ent* cpuEnt = get_cpu_struct(); 1450 if (cpuEnt->arch.vendor != VENDOR_AMD) 1451 return; 1452 uint32 family = cpuEnt->arch.family + cpuEnt->arch.extended_family; 1453 if (family < 0x10) 1454 return; 1455 uint64 value = x86_read_msr(MSR_F10H_HWCR); 1456 if ((value & HWCR_TSCFREQSEL) == 0) 1457 return; 1458 1459 value = x86_read_msr(MSR_F10H_PSTATEDEF(0)); 1460 if ((value & PSTATEDEF_EN) == 0) 1461 return; 1462 if (family != 0x17 && family != 0x19) 1463 return; 1464 1465 uint64 khz = 200 * 1000; 1466 uint32 denominator = (value >> 8) & 0x3f; 1467 if (denominator < 0x8 || denominator > 0x2c) 1468 return; 1469 if (denominator > 0x1a && (denominator % 2) == 1) 1470 return; 1471 uint32 numerator = value & 0xff; 1472 if (numerator < 0x10) 1473 return; 1474 1475 dprintf("CPU: using TSC frequency from MSR %" B_PRIu64 "\n", khz * numerator / denominator); 1476 // compute for microseconds as follows (1000000 << 32) / (tsc freq in Hz), 1477 // or (1000 << 32) / (tsc freq in kHz) 1478 *conversionFactor = (1000ULL << 32) / (khz * numerator / denominator); 1479 // overwrite the bootloader value 1480 args->arch_args.system_time_cv_factor = *conversionFactor; 1481 } 1482 1483 1484 static void 1485 init_tsc(kernel_args* args) 1486 { 1487 // init the TSC -> system_time() conversion factors 1488 1489 // try to find the TSC frequency with CPUID 1490 uint32 conversionFactor = args->arch_args.system_time_cv_factor; 1491 init_tsc_with_cpuid(args, &conversionFactor); 1492 init_tsc_with_msr(args, &conversionFactor); 1493 uint64 conversionFactorNsecs = (uint64)conversionFactor * 1000; 1494 1495 1496 #ifdef __x86_64__ 1497 // The x86_64 system_time() implementation uses 64-bit multiplication and 1498 // therefore shifting is not necessary for low frequencies (it's also not 1499 // too likely that there'll be any x86_64 CPUs clocked under 1GHz). 1500 __x86_setup_system_time((uint64)conversionFactor << 32, 1501 conversionFactorNsecs); 1502 #else 1503 if (conversionFactorNsecs >> 32 != 0) { 1504 // the TSC frequency is < 1 GHz, which forces us to shift the factor 1505 __x86_setup_system_time(conversionFactor, conversionFactorNsecs >> 16, 1506 true); 1507 } else { 1508 // the TSC frequency is >= 1 GHz 1509 __x86_setup_system_time(conversionFactor, conversionFactorNsecs, false); 1510 } 1511 #endif 1512 } 1513 1514 1515 status_t 1516 arch_cpu_init_percpu(kernel_args* args, int cpu) 1517 { 1518 load_microcode(cpu); 1519 detect_cpu(cpu); 1520 1521 if (cpu == 0) 1522 init_tsc(args); 1523 1524 if (!gCpuIdleFunc) { 1525 if (detect_amdc1e_noarat()) 1526 gCpuIdleFunc = amdc1e_noarat_idle; 1527 else 1528 gCpuIdleFunc = halt_idle; 1529 } 1530 1531 if (x86_check_feature(IA32_FEATURE_MCE, FEATURE_COMMON)) 1532 x86_write_cr4(x86_read_cr4() | IA32_CR4_MCE); 1533 1534 #ifdef __x86_64__ 1535 // if RDTSCP is available write cpu number in TSC_AUX 1536 if (x86_check_feature(IA32_FEATURE_AMD_EXT_RDTSCP, FEATURE_EXT_AMD)) 1537 x86_write_msr(IA32_MSR_TSC_AUX, cpu); 1538 1539 // make LFENCE a dispatch serializing instruction on AMD 64bit 1540 cpu_ent* cpuEnt = get_cpu_struct(); 1541 if (cpuEnt->arch.vendor == VENDOR_AMD) { 1542 uint32 family = cpuEnt->arch.family + cpuEnt->arch.extended_family; 1543 if (family >= 0x10 && family != 0x11) { 1544 uint64 value = x86_read_msr(MSR_F10H_DE_CFG); 1545 if ((value & DE_CFG_SERIALIZE_LFENCE) == 0) 1546 x86_write_msr(MSR_F10H_DE_CFG, value | DE_CFG_SERIALIZE_LFENCE); 1547 } 1548 } 1549 #endif 1550 1551 if (x86_check_feature(IA32_FEATURE_APERFMPERF, FEATURE_6_ECX)) { 1552 gCPU[cpu].arch.mperf_prev = x86_read_msr(IA32_MSR_MPERF); 1553 gCPU[cpu].arch.aperf_prev = x86_read_msr(IA32_MSR_APERF); 1554 gCPU[cpu].arch.frequency = 0; 1555 gCPU[cpu].arch.perf_timestamp = 0; 1556 } 1557 return __x86_patch_errata_percpu(cpu); 1558 } 1559 1560 1561 status_t 1562 arch_cpu_init(kernel_args* args) 1563 { 1564 if (args->ucode_data != NULL 1565 && args->ucode_data_size > 0) { 1566 sUcodeData = args->ucode_data; 1567 sUcodeDataSize = args->ucode_data_size; 1568 } else { 1569 dprintf("CPU: no microcode provided\n"); 1570 } 1571 1572 // Initialize descriptor tables. 1573 x86_descriptors_init(args); 1574 1575 return B_OK; 1576 } 1577 1578 1579 #ifdef __x86_64__ 1580 static void 1581 enable_smap(void* dummy, int cpu) 1582 { 1583 x86_write_cr4(x86_read_cr4() | IA32_CR4_SMAP); 1584 } 1585 1586 1587 static void 1588 enable_smep(void* dummy, int cpu) 1589 { 1590 x86_write_cr4(x86_read_cr4() | IA32_CR4_SMEP); 1591 } 1592 1593 1594 static void 1595 enable_osxsave(void* dummy, int cpu) 1596 { 1597 x86_write_cr4(x86_read_cr4() | IA32_CR4_OSXSAVE); 1598 } 1599 1600 1601 static void 1602 enable_xsavemask(void* dummy, int cpu) 1603 { 1604 xsetbv(0, gXsaveMask); 1605 } 1606 #endif 1607 1608 1609 status_t 1610 arch_cpu_init_post_vm(kernel_args* args) 1611 { 1612 uint32 i; 1613 1614 // allocate an area for the double fault stacks 1615 virtual_address_restrictions virtualRestrictions = {}; 1616 virtualRestrictions.address_specification = B_ANY_KERNEL_ADDRESS; 1617 physical_address_restrictions physicalRestrictions = {}; 1618 create_area_etc(B_SYSTEM_TEAM, "double fault stacks", 1619 kDoubleFaultStackSize * smp_get_num_cpus(), B_FULL_LOCK, 1620 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, CREATE_AREA_DONT_WAIT, 0, 1621 &virtualRestrictions, &physicalRestrictions, 1622 (void**)&sDoubleFaultStacks); 1623 1624 X86PagingStructures* kernelPagingStructures 1625 = static_cast<X86VMTranslationMap*>( 1626 VMAddressSpace::Kernel()->TranslationMap())->PagingStructures(); 1627 1628 // Set active translation map on each CPU. 1629 for (i = 0; i < args->num_cpus; i++) { 1630 gCPU[i].arch.active_paging_structures = kernelPagingStructures; 1631 kernelPagingStructures->AddReference(); 1632 } 1633 1634 if (!apic_available()) 1635 x86_init_fpu(); 1636 // else fpu gets set up in smp code 1637 1638 #ifdef __x86_64__ 1639 // if available enable SMEP (Supervisor Memory Execution Protection) 1640 if (x86_check_feature(IA32_FEATURE_SMEP, FEATURE_7_EBX)) { 1641 if (!get_safemode_boolean(B_SAFEMODE_DISABLE_SMEP_SMAP, false)) { 1642 dprintf("enable SMEP\n"); 1643 call_all_cpus_sync(&enable_smep, NULL); 1644 } else 1645 dprintf("SMEP disabled per safemode setting\n"); 1646 } 1647 1648 // if available enable SMAP (Supervisor Memory Access Protection) 1649 if (x86_check_feature(IA32_FEATURE_SMAP, FEATURE_7_EBX)) { 1650 if (!get_safemode_boolean(B_SAFEMODE_DISABLE_SMEP_SMAP, false)) { 1651 dprintf("enable SMAP\n"); 1652 call_all_cpus_sync(&enable_smap, NULL); 1653 1654 arch_altcodepatch_replace(ALTCODEPATCH_TAG_STAC, &_stac, 3); 1655 arch_altcodepatch_replace(ALTCODEPATCH_TAG_CLAC, &_clac, 3); 1656 } else 1657 dprintf("SMAP disabled per safemode setting\n"); 1658 } 1659 1660 // if available enable XSAVE (XSAVE and extended states) 1661 gHasXsave = x86_check_feature(IA32_FEATURE_EXT_XSAVE, FEATURE_EXT); 1662 if (gHasXsave) { 1663 gHasXsavec = x86_check_feature(IA32_FEATURE_XSAVEC, 1664 FEATURE_D_1_EAX); 1665 1666 call_all_cpus_sync(&enable_osxsave, NULL); 1667 gXsaveMask = IA32_XCR0_X87 | IA32_XCR0_SSE; 1668 cpuid_info cpuid; 1669 get_current_cpuid(&cpuid, 0xd, 0); 1670 gXsaveMask |= (cpuid.regs.eax & IA32_XCR0_AVX); 1671 call_all_cpus_sync(&enable_xsavemask, NULL); 1672 get_current_cpuid(&cpuid, 0xd, 0); 1673 gFPUSaveLength = cpuid.regs.ebx; 1674 if (gFPUSaveLength > sizeof(((struct arch_thread *)0)->fpu_state)) 1675 gFPUSaveLength = 832; 1676 1677 arch_altcodepatch_replace(ALTCODEPATCH_TAG_XSAVE, 1678 gHasXsavec ? &_xsavec : &_xsave, 4); 1679 arch_altcodepatch_replace(ALTCODEPATCH_TAG_XRSTOR, 1680 &_xrstor, 4); 1681 1682 dprintf("enable %s 0x%" B_PRIx64 " %" B_PRId64 "\n", 1683 gHasXsavec ? "XSAVEC" : "XSAVE", gXsaveMask, gFPUSaveLength); 1684 } 1685 1686 #endif 1687 1688 return B_OK; 1689 } 1690 1691 1692 status_t 1693 arch_cpu_init_post_modules(kernel_args* args) 1694 { 1695 // initialize CPU module 1696 1697 void* cookie = open_module_list("cpu"); 1698 1699 while (true) { 1700 char name[B_FILE_NAME_LENGTH]; 1701 size_t nameLength = sizeof(name); 1702 1703 if (read_next_module_name(cookie, name, &nameLength) != B_OK 1704 || get_module(name, (module_info**)&sCpuModule) == B_OK) 1705 break; 1706 } 1707 1708 close_module_list(cookie); 1709 1710 // initialize MTRRs if available 1711 if (x86_count_mtrrs() > 0) { 1712 sCpuRendezvous = sCpuRendezvous2 = 0; 1713 call_all_cpus(&init_mtrrs, NULL); 1714 } 1715 1716 size_t threadExitLen = (addr_t)x86_end_userspace_thread_exit 1717 - (addr_t)x86_userspace_thread_exit; 1718 addr_t threadExitPosition = fill_commpage_entry( 1719 COMMPAGE_ENTRY_X86_THREAD_EXIT, (const void*)x86_userspace_thread_exit, 1720 threadExitLen); 1721 1722 // add the functions to the commpage image 1723 image_id image = get_commpage_image(); 1724 1725 elf_add_memory_image_symbol(image, "commpage_thread_exit", 1726 threadExitPosition, threadExitLen, B_SYMBOL_TYPE_TEXT); 1727 1728 return B_OK; 1729 } 1730 1731 1732 void 1733 arch_cpu_user_TLB_invalidate(void) 1734 { 1735 x86_write_cr3(x86_read_cr3()); 1736 } 1737 1738 1739 void 1740 arch_cpu_global_TLB_invalidate(void) 1741 { 1742 uint32 flags = x86_read_cr4(); 1743 1744 if (flags & IA32_CR4_GLOBAL_PAGES) { 1745 // disable and reenable the global pages to flush all TLBs regardless 1746 // of the global page bit 1747 x86_write_cr4(flags & ~IA32_CR4_GLOBAL_PAGES); 1748 x86_write_cr4(flags | IA32_CR4_GLOBAL_PAGES); 1749 } else { 1750 cpu_status state = disable_interrupts(); 1751 arch_cpu_user_TLB_invalidate(); 1752 restore_interrupts(state); 1753 } 1754 } 1755 1756 1757 void 1758 arch_cpu_invalidate_TLB_range(addr_t start, addr_t end) 1759 { 1760 int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE; 1761 while (num_pages-- >= 0) { 1762 invalidate_TLB(start); 1763 start += B_PAGE_SIZE; 1764 } 1765 } 1766 1767 1768 void 1769 arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages) 1770 { 1771 int i; 1772 for (i = 0; i < num_pages; i++) { 1773 invalidate_TLB(pages[i]); 1774 } 1775 } 1776 1777 1778 status_t 1779 arch_cpu_shutdown(bool rebootSystem) 1780 { 1781 if (acpi_shutdown(rebootSystem) == B_OK) 1782 return B_OK; 1783 1784 if (!rebootSystem) { 1785 #ifndef __x86_64__ 1786 return apm_shutdown(); 1787 #else 1788 return B_NOT_SUPPORTED; 1789 #endif 1790 } 1791 1792 cpu_status state = disable_interrupts(); 1793 1794 // try to reset the system using the keyboard controller 1795 out8(0xfe, 0x64); 1796 1797 // Give some time to the controller to do its job (0.5s) 1798 snooze(500000); 1799 1800 // if that didn't help, try it this way 1801 x86_reboot(); 1802 1803 restore_interrupts(state); 1804 return B_ERROR; 1805 } 1806 1807 1808 void 1809 arch_cpu_sync_icache(void* address, size_t length) 1810 { 1811 // instruction cache is always consistent on x86 1812 } 1813 1814