1 /* 2 * Copyright 2011-2012 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 9 10 #include <debug.h> 11 #include <arch/arm/reg.h> 12 #include <arch/generic/debug_uart.h> 13 #include <arch/arm/arch_uart_pl011.h> 14 #include <new> 15 16 17 #define PL01x_DR 0x00 // Data read or written 18 #define PL01x_RSR 0x04 // Receive status, read 19 #define PL01x_ECR 0x04 // Error clear, write 20 #define PL010_LCRH 0x08 // Line control, high 21 #define PL010_LCRM 0x0C // Line control, middle 22 #define PL010_LCRL 0x10 // Line control, low 23 #define PL010_CR 0x14 // Control 24 #define PL01x_FR 0x18 // Flag (r/o) 25 #define PL010_IIR 0x1C // Interrupt ID (r) 26 #define PL010_ICR 0x1C // Interrupt clear (w) 27 #define PL01x_ILPR 0x20 // IrDA low power 28 #define PL011_IBRD 0x24 // Interrupt baud rate divisor 29 #define PL011_FBRD 0x28 // Fractional baud rate divisor 30 #define PL011_LCRH 0x2C // Line control 31 #define PL011_CR 0x30 // Control 32 #define PL011_IFLS 0x34 // Interrupt fifo level 33 #define PL011_IMSC 0x38 // Interrupt mask 34 #define PL011_RIS 0x3C // Raw interrupt 35 #define PL011_MIS 0x40 // Masked interrupt 36 #define PL011_ICR 0x44 // Interrupt clear 37 #define PL011_DMACR 0x48 // DMA control register 38 39 #define PL011_DR_OE (1 << 11) 40 #define PL011_DR_BE (1 << 10) 41 #define PL011_DR_PE (1 << 9) 42 #define PL011_DR_FE (1 << 8) 43 44 #define PL01x_RSR_OE 0x08 45 #define PL01x_RSR_BE 0x04 46 #define PL01x_RSR_PE 0x02 47 #define PL01x_RSR_FE 0x01 48 49 #define PL011_FR_RI 0x100 50 #define PL011_FR_TXFE 0x080 51 #define PL011_FR_RXFF 0x040 52 #define PL01x_FR_TXFF 0x020 53 #define PL01x_FR_RXFE 0x010 54 #define PL01x_FR_BUSY 0x008 55 #define PL01x_FR_DCD 0x004 56 #define PL01x_FR_DSR 0x002 57 #define PL01x_FR_CTS 0x001 58 #define PL01x_FR_TMSK (PL01x_FR_TXFF | PL01x_FR_BUSY) 59 60 #define PL011_CR_CTSEN 0x8000 // CTS flow control 61 #define PL011_CR_RTSEN 0x4000 // RTS flow control 62 #define PL011_CR_OUT2 0x2000 // OUT2 63 #define PL011_CR_OUT1 0x1000 // OUT1 64 #define PL011_CR_RTS 0x0800 // RTS 65 #define PL011_CR_DTR 0x0400 // DTR 66 #define PL011_CR_RXE 0x0200 // Receive enable 67 #define PL011_CR_TXE 0x0100 // Transmit enable 68 #define PL011_CR_LBE 0x0080 // Loopback enable 69 #define PL010_CR_RTIE 0x0040 70 #define PL010_CR_TIE 0x0020 71 #define PL010_CR_RIE 0x0010 72 #define PL010_CR_MSIE 0x0008 73 #define PL01x_CR_IIRLP 0x0004 // SIR low power mode 74 #define PL01x_CR_SIREN 0x0002 // SIR enable 75 #define PL01x_CR_UARTEN 0x0001 // UART enable 76 77 #define PL011_LCRH_SPS 0x80 78 #define PL01x_LCRH_WLEN_8 0x60 79 #define PL01x_LCRH_WLEN_7 0x40 80 #define PL01x_LCRH_WLEN_6 0x20 81 #define PL01x_LCRH_WLEN_5 0x00 82 #define PL01x_LCRH_FEN 0x10 83 #define PL01x_LCRH_STP2 0x08 84 #define PL01x_LCRH_EPS 0x04 85 #define PL01x_LCRH_PEN 0x02 86 #define PL01x_LCRH_BRK 0x01 87 88 #define PL010_IIR_RTIS 0x08 89 #define PL010_IIR_TIS 0x04 90 #define PL010_IIR_RIS 0x02 91 #define PL010_IIR_MIS 0x01 92 93 #define PL011_IFLS_RX1_8 (0 << 3) 94 #define PL011_IFLS_RX2_8 (1 << 3) 95 #define PL011_IFLS_RX4_8 (2 << 3) 96 #define PL011_IFLS_RX6_8 (3 << 3) 97 #define PL011_IFLS_RX7_8 (4 << 3) 98 #define PL011_IFLS_TX1_8 (0 << 0) 99 #define PL011_IFLS_TX2_8 (1 << 0) 100 #define PL011_IFLS_TX4_8 (2 << 0) 101 #define PL011_IFLS_TX6_8 (3 << 0) 102 #define PL011_IFLS_TX7_8 (4 << 0) 103 104 #define PL011_IFLS_RX_HALF (5 << 3) // ST vendor only 105 #define PL011_IFLS_TX_HALF (5 << 0) // ST vendor only 106 107 #define PL011_OEIM (1 << 10) // overrun error interrupt mask 108 #define PL011_BEIM (1 << 9) // break error interrupt mask 109 #define PL011_PEIM (1 << 8) // parity error interrupt mask 110 #define PL011_FEIM (1 << 7) // framing error interrupt mask 111 #define PL011_RTIM (1 << 6) // receive timeout interrupt mask 112 #define PL011_TXIM (1 << 5) // transmit interrupt mask 113 #define PL011_RXIM (1 << 4) // receive interrupt mask 114 #define PL011_DSRMIM (1 << 3) // DSR interrupt mask 115 #define PL011_DCDMIM (1 << 2) // DCD interrupt mask 116 #define PL011_CTSMIM (1 << 1) // CTS interrupt mask 117 #define PL011_RIMIM (1 << 0) // RI interrupt mask 118 119 #define PL011_OEIS (1 << 10) // overrun error interrupt state 120 #define PL011_BEIS (1 << 9) // break error interrupt state 121 #define PL011_PEIS (1 << 8) // parity error interrupt state 122 #define PL011_FEIS (1 << 7) // framing error interrupt state 123 #define PL011_RTIS (1 << 6) // receive timeout interrupt state 124 #define PL011_TXIS (1 << 5) // transmit interrupt state 125 #define PL011_RXIS (1 << 4) // receive interrupt state 126 #define PL011_DSRMIS (1 << 3) // DSR interrupt state 127 #define PL011_DCDMIS (1 << 2) // DCD interrupt state 128 #define PL011_CTSMIS (1 << 1) // CTS interrupt state 129 #define PL011_RIMIS (1 << 0) // RI interrupt state 130 131 #define PL011_OEIC (1 << 10) // overrun error interrupt clear 132 #define PL011_BEIC (1 << 9) // break error interrupt clear 133 #define PL011_PEIC (1 << 8) // parity error interrupt clear 134 #define PL011_FEIC (1 << 7) // framing error interrupt clear 135 #define PL011_RTIC (1 << 6) // receive timeout interrupt clear 136 #define PL011_TXIC (1 << 5) // transmit interrupt clear 137 #define PL011_RXIC (1 << 4) // receive interrupt clear 138 #define PL011_DSRMIC (1 << 3) // DSR interrupt clear 139 #define PL011_DCDMIC (1 << 2) // DCD interrupt clear 140 #define PL011_CTSMIC (1 << 1) // CTS interrupt clear 141 #define PL011_RIMIC (1 << 0) // RI interrupt clear 142 143 #define PL011_DMAONERR (1 << 2) // disable dma on err 144 #define PL011_TXDMAE (1 << 1) // enable transmit dma 145 #define PL011_RXDMAE (1 << 0) // enable receive dma 146 147 148 ArchUARTPL011::ArchUARTPL011(addr_t base, int64 clock) 149 : 150 DebugUART(base, clock) 151 { 152 Barrier(); 153 154 // ** Loopback test 155 uint32 cr = PL01x_CR_UARTEN; 156 // Enable UART 157 cr |= PL011_CR_TXE; 158 // Enable TX 159 cr |= PL011_CR_LBE; 160 // Enable Loopback mode 161 Out32(PL011_CR, cr); 162 163 Out32(PL011_FBRD, 0); 164 Out32(PL011_IBRD, 1); 165 Out32(PL011_LCRH, 0); // TODO: ST is different tx, rx lcr 166 167 // Write a 0 to the port and wait for confim.. 168 Out32(PL01x_DR, 0); 169 170 while (In32(PL01x_FR) & PL01x_FR_BUSY) 171 Barrier(); 172 173 // ** Disable loopback, enable uart 174 cr = PL01x_CR_UARTEN | PL011_CR_RXE | PL011_CR_TXE; 175 Out32(PL011_CR, cr); 176 177 // ** Clear interrupts 178 Out32(PL011_ICR, PL011_OEIS | PL011_BEIS 179 | PL011_PEIS | PL011_FEIS); 180 181 // ** Disable interrupts 182 Out32(PL011_IMSC, 0); 183 } 184 185 186 ArchUARTPL011::~ArchUARTPL011() 187 { 188 } 189 190 191 void 192 ArchUARTPL011::Out32(int reg, uint32 data) 193 { 194 *(volatile uint32*)(Base() + reg) = data; 195 } 196 197 198 uint32 199 ArchUARTPL011::In32(int reg) 200 { 201 return *(volatile uint32*)(Base() + reg); 202 } 203 204 205 void 206 ArchUARTPL011::Barrier() 207 { 208 asm volatile ("" : : : "memory"); 209 } 210 211 212 void 213 ArchUARTPL011::InitPort(uint32 baud) 214 { 215 // Calculate baud divisor 216 uint32 baudDivisor = Clock() / (16 * baud); 217 uint32 remainder = Clock() % (16 * baud); 218 uint32 baudFractional = ((8 * remainder) / baud >> 1) 219 + ((8 * remainder) / baud & 1); 220 221 // Disable UART 222 Disable(); 223 224 // Set baud divisor 225 Out32(PL011_IBRD, baudDivisor); 226 Out32(PL011_FBRD, baudFractional); 227 228 // Set LCR 8n1, enable fifo 229 Out32(PL011_LCRH, PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN); 230 231 // Enable UART 232 Enable(); 233 } 234 235 236 void 237 ArchUARTPL011::InitEarly() 238 { 239 // Perform special hardware UART configuration 240 } 241 242 243 void 244 ArchUARTPL011::Enable() 245 { 246 uint32 cr = PL01x_CR_UARTEN; 247 // Enable UART 248 cr |= PL011_CR_TXE | PL011_CR_RXE; 249 // Enable TX and RX 250 251 Out32(PL011_CR, cr); 252 253 DebugUART::Enable(); 254 } 255 256 257 void 258 ArchUARTPL011::Disable() 259 { 260 // Disable everything 261 Out32(PL011_CR, 0); 262 263 DebugUART::Disable(); 264 } 265 266 267 int 268 ArchUARTPL011::PutChar(char c) 269 { 270 if (Enabled() == true) { 271 // Wait until there is room in fifo 272 while ((In32(PL01x_FR) & PL01x_FR_TXFF) != 0) 273 Barrier(); 274 275 Out32(PL01x_DR, c); 276 return 0; 277 } 278 279 return -1; 280 } 281 282 283 int 284 ArchUARTPL011::GetChar(bool wait) 285 { 286 if (Enabled() == true) { 287 // Wait until a character is received? 288 if (wait) { 289 while ((In32(PL01x_FR) & PL01x_FR_RXFE) != 0) 290 Barrier(); 291 } 292 return In32(PL01x_DR); 293 } 294 295 return -1; 296 } 297 298 299 void 300 ArchUARTPL011::FlushTx() 301 { 302 // Wait until transmit fifo empty 303 while ((In32(PL01x_FR) & PL011_FR_TXFE) == 0) 304 Barrier(); 305 } 306 307 308 void 309 ArchUARTPL011::FlushRx() 310 { 311 // Wait until receive fifo empty 312 while ((In32(PL01x_FR) & PL01x_FR_RXFE) == 0) 313 Barrier(); 314 } 315 316 317 ArchUARTPL011 *arch_get_uart_pl011(addr_t base, int64 clock) 318 { 319 static char buffer[sizeof(ArchUARTPL011)]; 320 ArchUARTPL011 *uart = new(buffer) ArchUARTPL011(base, clock); 321 return uart; 322 } 323