1 /* 2 * Copyright 2011-2012 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 9 10 #include <debug.h> 11 #include <arch/arm/reg.h> 12 #include <arch/generic/debug_uart.h> 13 #include <arch/arm/arch_uart_pl011.h> 14 //#include <board_config.h> 15 #include <new> 16 //#include <target/debugconfig.h> 17 18 19 #define PL01x_DR 0x00 // Data read or written 20 #define PL01x_RSR 0x04 // Receive status, read 21 #define PL01x_ECR 0x04 // Error clear, write 22 #define PL010_LCRH 0x08 // Line control, high 23 #define PL010_LCRM 0x0C // Line control, middle 24 #define PL010_LCRL 0x10 // Line control, low 25 #define PL010_CR 0x14 // Control 26 #define PL01x_FR 0x18 // Flag (r/o) 27 #define PL010_IIR 0x1C // Interrupt ID (r) 28 #define PL010_ICR 0x1C // Interrupt clear (w) 29 #define PL01x_ILPR 0x20 // IrDA low power 30 #define PL011_IBRD 0x24 // Interrupt baud rate divisor 31 #define PL011_FBRD 0x28 // Fractional baud rate divisor 32 #define PL011_LCRH 0x2C // Line control 33 #define PL011_CR 0x30 // Control 34 #define PL011_IFLS 0x34 // Interrupt fifo level 35 #define PL011_IMSC 0x38 // Interrupt mask 36 #define PL011_RIS 0x3C // Raw interrupt 37 #define PL011_MIS 0x40 // Masked interrupt 38 #define PL011_ICR 0x44 // Interrupt clear 39 #define PL011_DMACR 0x48 // DMA control register 40 41 #define PL011_DR_OE (1 << 11) 42 #define PL011_DR_BE (1 << 10) 43 #define PL011_DR_PE (1 << 9) 44 #define PL011_DR_FE (1 << 8) 45 46 #define PL01x_RSR_OE 0x08 47 #define PL01x_RSR_BE 0x04 48 #define PL01x_RSR_PE 0x02 49 #define PL01x_RSR_FE 0x01 50 51 #define PL011_FR_RI 0x100 52 #define PL011_FR_TXFE 0x080 53 #define PL011_FR_RXFF 0x040 54 #define PL01x_FR_TXFF 0x020 55 #define PL01x_FR_RXFE 0x010 56 #define PL01x_FR_BUSY 0x008 57 #define PL01x_FR_DCD 0x004 58 #define PL01x_FR_DSR 0x002 59 #define PL01x_FR_CTS 0x001 60 #define PL01x_FR_TMSK (PL01x_FR_TXFF | PL01x_FR_BUSY) 61 62 #define PL011_CR_CTSEN 0x8000 // CTS flow control 63 #define PL011_CR_RTSEN 0x4000 // RTS flow control 64 #define PL011_CR_OUT2 0x2000 // OUT2 65 #define PL011_CR_OUT1 0x1000 // OUT1 66 #define PL011_CR_RTS 0x0800 // RTS 67 #define PL011_CR_DTR 0x0400 // DTR 68 #define PL011_CR_RXE 0x0200 // Receive enable 69 #define PL011_CR_TXE 0x0100 // Transmit enable 70 #define PL011_CR_LBE 0x0080 // Loopback enable 71 #define PL010_CR_RTIE 0x0040 72 #define PL010_CR_TIE 0x0020 73 #define PL010_CR_RIE 0x0010 74 #define PL010_CR_MSIE 0x0008 75 #define PL01x_CR_IIRLP 0x0004 // SIR low power mode 76 #define PL01x_CR_SIREN 0x0002 // SIR enable 77 #define PL01x_CR_UARTEN 0x0001 // UART enable 78 79 #define PL011_LCRH_SPS 0x80 80 #define PL01x_LCRH_WLEN_8 0x60 81 #define PL01x_LCRH_WLEN_7 0x40 82 #define PL01x_LCRH_WLEN_6 0x20 83 #define PL01x_LCRH_WLEN_5 0x00 84 #define PL01x_LCRH_FEN 0x10 85 #define PL01x_LCRH_STP2 0x08 86 #define PL01x_LCRH_EPS 0x04 87 #define PL01x_LCRH_PEN 0x02 88 #define PL01x_LCRH_BRK 0x01 89 90 #define PL010_IIR_RTIS 0x08 91 #define PL010_IIR_TIS 0x04 92 #define PL010_IIR_RIS 0x02 93 #define PL010_IIR_MIS 0x01 94 95 #define PL011_IFLS_RX1_8 (0 << 3) 96 #define PL011_IFLS_RX2_8 (1 << 3) 97 #define PL011_IFLS_RX4_8 (2 << 3) 98 #define PL011_IFLS_RX6_8 (3 << 3) 99 #define PL011_IFLS_RX7_8 (4 << 3) 100 #define PL011_IFLS_TX1_8 (0 << 0) 101 #define PL011_IFLS_TX2_8 (1 << 0) 102 #define PL011_IFLS_TX4_8 (2 << 0) 103 #define PL011_IFLS_TX6_8 (3 << 0) 104 #define PL011_IFLS_TX7_8 (4 << 0) 105 106 #define PL011_IFLS_RX_HALF (5 << 3) // ST vendor only 107 #define PL011_IFLS_TX_HALF (5 << 0) // ST vendor only 108 109 #define PL011_OEIM (1 << 10) // overrun error interrupt mask 110 #define PL011_BEIM (1 << 9) // break error interrupt mask 111 #define PL011_PEIM (1 << 8) // parity error interrupt mask 112 #define PL011_FEIM (1 << 7) // framing error interrupt mask 113 #define PL011_RTIM (1 << 6) // receive timeout interrupt mask 114 #define PL011_TXIM (1 << 5) // transmit interrupt mask 115 #define PL011_RXIM (1 << 4) // receive interrupt mask 116 #define PL011_DSRMIM (1 << 3) // DSR interrupt mask 117 #define PL011_DCDMIM (1 << 2) // DCD interrupt mask 118 #define PL011_CTSMIM (1 << 1) // CTS interrupt mask 119 #define PL011_RIMIM (1 << 0) // RI interrupt mask 120 121 #define PL011_OEIS (1 << 10) // overrun error interrupt state 122 #define PL011_BEIS (1 << 9) // break error interrupt state 123 #define PL011_PEIS (1 << 8) // parity error interrupt state 124 #define PL011_FEIS (1 << 7) // framing error interrupt state 125 #define PL011_RTIS (1 << 6) // receive timeout interrupt state 126 #define PL011_TXIS (1 << 5) // transmit interrupt state 127 #define PL011_RXIS (1 << 4) // receive interrupt state 128 #define PL011_DSRMIS (1 << 3) // DSR interrupt state 129 #define PL011_DCDMIS (1 << 2) // DCD interrupt state 130 #define PL011_CTSMIS (1 << 1) // CTS interrupt state 131 #define PL011_RIMIS (1 << 0) // RI interrupt state 132 133 #define PL011_OEIC (1 << 10) // overrun error interrupt clear 134 #define PL011_BEIC (1 << 9) // break error interrupt clear 135 #define PL011_PEIC (1 << 8) // parity error interrupt clear 136 #define PL011_FEIC (1 << 7) // framing error interrupt clear 137 #define PL011_RTIC (1 << 6) // receive timeout interrupt clear 138 #define PL011_TXIC (1 << 5) // transmit interrupt clear 139 #define PL011_RXIC (1 << 4) // receive interrupt clear 140 #define PL011_DSRMIC (1 << 3) // DSR interrupt clear 141 #define PL011_DCDMIC (1 << 2) // DCD interrupt clear 142 #define PL011_CTSMIC (1 << 1) // CTS interrupt clear 143 #define PL011_RIMIC (1 << 0) // RI interrupt clear 144 145 #define PL011_DMAONERR (1 << 2) // disable dma on err 146 #define PL011_TXDMAE (1 << 1) // enable transmit dma 147 #define PL011_RXDMAE (1 << 0) // enable receive dma 148 149 150 ArchUARTPL011::ArchUARTPL011(addr_t base, int64 clock) 151 : DebugUART(base, clock) 152 { 153 Barrier(); 154 155 // ** Loopback test 156 uint32 cr = PL01x_CR_UARTEN; 157 // Enable UART 158 cr |= PL011_CR_TXE; 159 // Enable TX 160 cr |= PL011_CR_LBE; 161 // Enable Loopback mode 162 Out32(PL011_CR, cr); 163 164 Out32(PL011_FBRD, 0); 165 Out32(PL011_IBRD, 1); 166 Out32(PL011_LCRH, 0); // TODO: ST is different tx, rx lcr 167 168 // Write a 0 to the port and wait for confim.. 169 Out32(PL01x_DR, 0); 170 171 while (In32(PL01x_FR) & PL01x_FR_BUSY) 172 Barrier(); 173 174 // ** Disable loopback, enable uart 175 cr = PL01x_CR_UARTEN | PL011_CR_RXE | PL011_CR_TXE; 176 Out32(PL011_CR, cr); 177 178 // ** Clear interrupts 179 Out32(PL011_ICR, PL011_OEIS | PL011_BEIS 180 | PL011_PEIS | PL011_FEIS); 181 182 // ** Disable interrupts 183 Out32(PL011_IMSC, 0); 184 } 185 186 187 ArchUARTPL011::~ArchUARTPL011() 188 { 189 } 190 191 192 void 193 ArchUARTPL011::Out32(int reg, uint32 data) 194 { 195 *(volatile uint32*)(Base() + reg) = data; 196 } 197 198 199 uint32 200 ArchUARTPL011::In32(int reg) 201 { 202 return *(volatile uint32*)(Base() + reg); 203 } 204 205 206 void 207 ArchUARTPL011::Barrier() 208 { 209 asm volatile ("" : : : "memory"); 210 } 211 212 213 void 214 ArchUARTPL011::InitPort(uint32 baud) 215 { 216 // Calculate baud divisor 217 uint32 baudDivisor = Clock() / (16 * baud); 218 uint32 remainder = Clock() % (16 * baud); 219 uint32 baudFractional = ((8 * remainder) / baud >> 1) 220 + ((8 * remainder) / baud & 1); 221 222 // Disable UART 223 Disable(); 224 225 // Set baud divisor 226 Out32(PL011_IBRD, baudDivisor); 227 Out32(PL011_FBRD, baudFractional); 228 229 // Set LCR 8n1, enable fifo 230 Out32(PL011_LCRH, PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN); 231 232 // Enable UART 233 Enable(); 234 } 235 236 237 void 238 ArchUARTPL011::InitEarly() 239 { 240 // Perform special hardware UART configuration 241 } 242 243 244 void 245 ArchUARTPL011::Enable() 246 { 247 uint32 cr = PL01x_CR_UARTEN; 248 // Enable UART 249 cr |= PL011_CR_TXE | PL011_CR_RXE; 250 // Enable TX and RX 251 252 Out32(PL011_CR, cr); 253 254 DebugUART::Enable(); 255 } 256 257 258 void 259 ArchUARTPL011::Disable() 260 { 261 // Disable everything 262 Out32(PL011_CR, 0); 263 264 DebugUART::Disable(); 265 } 266 267 268 int 269 ArchUARTPL011::PutChar(char c) 270 { 271 if (Enabled() == true) { 272 // Wait until there is room in fifo 273 while ((In32(PL01x_FR) & PL01x_FR_TXFF) != 0) 274 Barrier(); 275 276 Out32(PL01x_DR, c); 277 return 0; 278 } 279 280 return -1; 281 } 282 283 284 int 285 ArchUARTPL011::GetChar(bool wait) 286 { 287 if (Enabled() == true) { 288 // Wait until a character is received? 289 if (wait) { 290 while ((In32(PL01x_FR) & PL01x_FR_RXFE) != 0) 291 Barrier(); 292 } 293 return In32(PL01x_DR); 294 } 295 296 return -1; 297 } 298 299 300 void 301 ArchUARTPL011::FlushTx() 302 { 303 // Wait until transmit fifo empty 304 while ((In32(PL01x_FR) & PL011_FR_TXFE) == 0) 305 Barrier(); 306 } 307 308 309 void 310 ArchUARTPL011::FlushRx() 311 { 312 // Wait until receive fifo empty 313 while ((In32(PL01x_FR) & PL01x_FR_RXFE) == 0) 314 Barrier(); 315 } 316 317 318 ArchUARTPL011 *arch_get_uart_pl011(addr_t base, int64 clock) 319 { 320 static char buffer[sizeof(ArchUARTPL011)]; 321 ArchUARTPL011 *uart = new(buffer) ArchUARTPL011(base, clock); 322 return uart; 323 } 324