1a42249dbSAlexander von Gluck IV /*
2a42249dbSAlexander von Gluck IV * Copyright 2011-2012 Haiku, Inc. All rights reserved.
3a42249dbSAlexander von Gluck IV * Distributed under the terms of the MIT License.
4a42249dbSAlexander von Gluck IV *
5a42249dbSAlexander von Gluck IV * Authors:
6a42249dbSAlexander von Gluck IV * François Revol, revol@free.fr
7a42249dbSAlexander von Gluck IV */
8a42249dbSAlexander von Gluck IV
9a42249dbSAlexander von Gluck IV
10a42249dbSAlexander von Gluck IV #include <arch/arm/reg.h>
11*441e6e67SDavid Karoly #include <arch/arm/arch_uart_8250_omap.h>
12a42249dbSAlexander von Gluck IV #include <debug.h>
13a42249dbSAlexander von Gluck IV #include <omap3.h>
14a42249dbSAlexander von Gluck IV #include <new>
15a42249dbSAlexander von Gluck IV
16a42249dbSAlexander von Gluck IV
ArchUART8250Omap(addr_t base,int64 clock)17a42249dbSAlexander von Gluck IV ArchUART8250Omap::ArchUART8250Omap(addr_t base, int64 clock)
18a42249dbSAlexander von Gluck IV :
19a42249dbSAlexander von Gluck IV DebugUART8250(base, clock)
20a42249dbSAlexander von Gluck IV {
21a42249dbSAlexander von Gluck IV }
22a42249dbSAlexander von Gluck IV
23a42249dbSAlexander von Gluck IV
~ArchUART8250Omap()24a42249dbSAlexander von Gluck IV ArchUART8250Omap::~ArchUART8250Omap()
25a42249dbSAlexander von Gluck IV {
26a42249dbSAlexander von Gluck IV }
27a42249dbSAlexander von Gluck IV
28a42249dbSAlexander von Gluck IV
29a42249dbSAlexander von Gluck IV void
InitEarly()30a42249dbSAlexander von Gluck IV ArchUART8250Omap::InitEarly()
31a42249dbSAlexander von Gluck IV {
32a42249dbSAlexander von Gluck IV // Perform special hardware UART configuration
33a42249dbSAlexander von Gluck IV /* UART1 */
34a42249dbSAlexander von Gluck IV RMWREG32(CM_FCLKEN1_CORE, 13, 1, 1);
35a42249dbSAlexander von Gluck IV RMWREG32(CM_ICLKEN1_CORE, 13, 1, 1);
36a42249dbSAlexander von Gluck IV
37a42249dbSAlexander von Gluck IV /* UART2 */
38a42249dbSAlexander von Gluck IV RMWREG32(CM_FCLKEN1_CORE, 14, 1, 1);
39a42249dbSAlexander von Gluck IV RMWREG32(CM_ICLKEN1_CORE, 14, 1, 1);
40a42249dbSAlexander von Gluck IV
41a42249dbSAlexander von Gluck IV /* UART3 */
42a42249dbSAlexander von Gluck IV RMWREG32(CM_FCLKEN_PER, 11, 1, 1);
43a42249dbSAlexander von Gluck IV RMWREG32(CM_ICLKEN_PER, 11, 1, 1);
44a42249dbSAlexander von Gluck IV }
45a42249dbSAlexander von Gluck IV
46a42249dbSAlexander von Gluck IV
47a42249dbSAlexander von Gluck IV void
Out8(int reg,uint8 value)48a42249dbSAlexander von Gluck IV ArchUART8250Omap::Out8(int reg, uint8 value)
49a42249dbSAlexander von Gluck IV {
50a42249dbSAlexander von Gluck IV *((uint8 *)Base() + reg * sizeof(uint32)) = value;
51a42249dbSAlexander von Gluck IV }
52a42249dbSAlexander von Gluck IV
53a42249dbSAlexander von Gluck IV
54a42249dbSAlexander von Gluck IV uint8
In8(int reg)55a42249dbSAlexander von Gluck IV ArchUART8250Omap::In8(int reg)
56a42249dbSAlexander von Gluck IV {
57a42249dbSAlexander von Gluck IV return *((uint8 *)Base() + reg * sizeof(uint32));
58a42249dbSAlexander von Gluck IV }
59a42249dbSAlexander von Gluck IV
60a42249dbSAlexander von Gluck IV
611648ab52SAlexander von Gluck IV DebugUART8250*
arch_get_uart_8250_omap(addr_t base,int64 clock)621648ab52SAlexander von Gluck IV arch_get_uart_8250_omap(addr_t base, int64 clock)
63a42249dbSAlexander von Gluck IV {
64a42249dbSAlexander von Gluck IV static char buffer[sizeof(ArchUART8250Omap)];
65a42249dbSAlexander von Gluck IV ArchUART8250Omap* uart = new(buffer) ArchUART8250Omap(base, clock);
66a42249dbSAlexander von Gluck IV return uart;
67a42249dbSAlexander von Gluck IV }
68