1/* 2 * Copyright 2021-2022, Oliver Ruiz Dorantes. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6/*- 7 * Copyright (c) 2012-2014 Andrew Turner 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#include <asm_defs.h> 35#include <kernel/arch/arm64/arm_registers.h> 36#include <kernel/arch/arm64/arch_hypervisor.h> 37 38 39 .text 40 41.macro mreg origin, destination, temporal 42 mrs \temporal, \origin 43 msr \destination, \temporal 44.endm 45 46 47FUNCTION(_arch_transition_EL2_EL1): 48 // Translation Table Base Register 49 mreg TTBR0_EL2, TTBR0_EL1, x10 50 // Memory Attribute Indirection Register 51 mreg MAIR_EL2, MAIR_EL1, x10 52 // Vector Base Address Register 53 mreg vbar_el2, vbar_el1, x10 54 // Migrate SP 55 mov x10, sp 56 msr sp_el1, x10 57 58 // Enable FP/SIMD 59 mov x10, #3 << 20 60 msr cpacr_el1, x10 61 62 b drop_to_el1 63 // eret will return to caller 64FUNCTION_END(_arch_transition_EL2_EL1) 65 66 67/* 68 * If we are started in EL2, configure the required hypervisor 69 * registers and drop to EL1. 70 */ 71FUNCTION(drop_to_el1): 72 mrs x1, CurrentEL 73 lsr x1, x1, #2 74 cmp x1, #0x2 75 b.eq 1f 76 ret 771: 78 /* Configure the Hypervisor */ 79 mov x2, #(HCR_RW) 80 msr hcr_el2, x2 81 82 /* Load the Virtualization Process ID Register */ 83 mrs x2, midr_el1 84 msr vpidr_el2, x2 85 86 /* Load the Virtualization Multiprocess ID Register */ 87 mrs x2, mpidr_el1 88 msr vmpidr_el2, x2 89 90 /* Set the bits that need to be 1 in sctlr_el1 */ 91 ldr x2, .Lsctlr_res1 92 msr sctlr_el1, x2 93 94 /* Don't trap to EL2 for exceptions */ 95 mov x2, #CPTR_RES1 96 msr cptr_el2, x2 97 98 /* Don't trap to EL2 for CP15 traps */ 99 msr hstr_el2, xzr 100 101 /* Enable access to the physical timers at EL1 */ 102 mrs x2, cnthctl_el2 103 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 104 msr cnthctl_el2, x2 105 106 /* Set the counter offset to a known value */ 107 msr cntvoff_el2, xzr 108 109 /* Hypervisor trap functions */ 110// adr x2, hyp_vectors 111// msr vbar_el2, x2 112 113 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 114 msr spsr_el2, x2 115 116 /* Configure GICv3 CPU interface */ 117 mrs x2, id_aa64pfr0_el1 118 /* Extract GIC bits from the register */ 119 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 120 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 121 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 122 b.ne 2f 123 124 mrs x2, S3_4_C12_C9_5 125 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 126 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 127 msr S3_4_C12_C9_5, x2 1282: 129 130 /* Set the address to return to our return address */ 131 msr elr_el2, x30 132 isb 133 134 eret 135FUNCTION_END(drop_to_el1) 136 137/* Macro Definitions */ 138 .align 3 139.Lsctlr_res1: 140 .quad SCTLR_RES1 141