1f9412d9fSurnenfeld/* 2f9412d9fSurnenfeld * Copyright 2021-2022, Oliver Ruiz Dorantes. All rights reserved. 3f9412d9fSurnenfeld * Distributed under the terms of the MIT License. 4f9412d9fSurnenfeld */ 5f9412d9fSurnenfeld 6f9412d9fSurnenfeld/*- 7f9412d9fSurnenfeld * Copyright (c) 2012-2014 Andrew Turner 8f9412d9fSurnenfeld * All rights reserved. 9f9412d9fSurnenfeld * 10f9412d9fSurnenfeld * Redistribution and use in source and binary forms, with or without 11f9412d9fSurnenfeld * modification, are permitted provided that the following conditions 12f9412d9fSurnenfeld * are met: 13f9412d9fSurnenfeld * 1. Redistributions of source code must retain the above copyright 14f9412d9fSurnenfeld * notice, this list of conditions and the following disclaimer. 15f9412d9fSurnenfeld * 2. Redistributions in binary form must reproduce the above copyright 16f9412d9fSurnenfeld * notice, this list of conditions and the following disclaimer in the 17f9412d9fSurnenfeld * documentation and/or other materials provided with the distribution. 18f9412d9fSurnenfeld * 19f9412d9fSurnenfeld * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20f9412d9fSurnenfeld * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21f9412d9fSurnenfeld * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22f9412d9fSurnenfeld * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23f9412d9fSurnenfeld * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24f9412d9fSurnenfeld * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25f9412d9fSurnenfeld * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26f9412d9fSurnenfeld * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27f9412d9fSurnenfeld * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28f9412d9fSurnenfeld * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29f9412d9fSurnenfeld * SUCH DAMAGE. 30f9412d9fSurnenfeld * 31f9412d9fSurnenfeld * $FreeBSD$ 32f9412d9fSurnenfeld */ 33f9412d9fSurnenfeld 34f9412d9fSurnenfeld#include <asm_defs.h> 35f9412d9fSurnenfeld#include <kernel/arch/arm64/arm_registers.h> 36f9412d9fSurnenfeld#include <kernel/arch/arm64/arch_hypervisor.h> 37f9412d9fSurnenfeld 38f9412d9fSurnenfeld 39f9412d9fSurnenfeld .text 40f9412d9fSurnenfeld 41f9412d9fSurnenfeld.macro mreg origin, destination, temporal 42f9412d9fSurnenfeld mrs \temporal, \origin 43f9412d9fSurnenfeld msr \destination, \temporal 44f9412d9fSurnenfeld.endm 45f9412d9fSurnenfeld 46f9412d9fSurnenfeld 47f9412d9fSurnenfeldFUNCTION(_arch_transition_EL2_EL1): 48f9412d9fSurnenfeld // Translation Table Base Register 49f9412d9fSurnenfeld mreg TTBR0_EL2, TTBR0_EL1, x10 50f9412d9fSurnenfeld // Memory Attribute Indirection Register 51f9412d9fSurnenfeld mreg MAIR_EL2, MAIR_EL1, x10 52f9412d9fSurnenfeld // Vector Base Address Register 53f9412d9fSurnenfeld mreg vbar_el2, vbar_el1, x10 54f9412d9fSurnenfeld // Migrate SP 55f9412d9fSurnenfeld mov x10, sp 56f9412d9fSurnenfeld msr sp_el1, x10 57f9412d9fSurnenfeld 58*20b3c898Surnenfeld // Enable FP/SIMD 59*20b3c898Surnenfeld mov x10, #3 << 20 60*20b3c898Surnenfeld msr cpacr_el1, x10 61*20b3c898Surnenfeld 62f9412d9fSurnenfeld b drop_to_el1 63f9412d9fSurnenfeld // eret will return to caller 64f9412d9fSurnenfeldFUNCTION_END(_arch_transition_EL2_EL1) 65f9412d9fSurnenfeld 66f9412d9fSurnenfeld 67f9412d9fSurnenfeld/* 68f9412d9fSurnenfeld * If we are started in EL2, configure the required hypervisor 69f9412d9fSurnenfeld * registers and drop to EL1. 70f9412d9fSurnenfeld */ 71f9412d9fSurnenfeldFUNCTION(drop_to_el1): 72f9412d9fSurnenfeld mrs x1, CurrentEL 73f9412d9fSurnenfeld lsr x1, x1, #2 74f9412d9fSurnenfeld cmp x1, #0x2 75f9412d9fSurnenfeld b.eq 1f 76f9412d9fSurnenfeld ret 77f9412d9fSurnenfeld1: 78f9412d9fSurnenfeld /* Configure the Hypervisor */ 79f9412d9fSurnenfeld mov x2, #(HCR_RW) 80f9412d9fSurnenfeld msr hcr_el2, x2 81f9412d9fSurnenfeld 82f9412d9fSurnenfeld /* Load the Virtualization Process ID Register */ 83f9412d9fSurnenfeld mrs x2, midr_el1 84f9412d9fSurnenfeld msr vpidr_el2, x2 85f9412d9fSurnenfeld 86f9412d9fSurnenfeld /* Load the Virtualization Multiprocess ID Register */ 87f9412d9fSurnenfeld mrs x2, mpidr_el1 88f9412d9fSurnenfeld msr vmpidr_el2, x2 89f9412d9fSurnenfeld 90f9412d9fSurnenfeld /* Set the bits that need to be 1 in sctlr_el1 */ 91f9412d9fSurnenfeld ldr x2, .Lsctlr_res1 92f9412d9fSurnenfeld msr sctlr_el1, x2 93f9412d9fSurnenfeld 94f9412d9fSurnenfeld /* Don't trap to EL2 for exceptions */ 95f9412d9fSurnenfeld mov x2, #CPTR_RES1 96f9412d9fSurnenfeld msr cptr_el2, x2 97f9412d9fSurnenfeld 98f9412d9fSurnenfeld /* Don't trap to EL2 for CP15 traps */ 99f9412d9fSurnenfeld msr hstr_el2, xzr 100f9412d9fSurnenfeld 101f9412d9fSurnenfeld /* Enable access to the physical timers at EL1 */ 102f9412d9fSurnenfeld mrs x2, cnthctl_el2 103f9412d9fSurnenfeld orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 104f9412d9fSurnenfeld msr cnthctl_el2, x2 105f9412d9fSurnenfeld 106f9412d9fSurnenfeld /* Set the counter offset to a known value */ 107f9412d9fSurnenfeld msr cntvoff_el2, xzr 108f9412d9fSurnenfeld 109f9412d9fSurnenfeld /* Hypervisor trap functions */ 110f9412d9fSurnenfeld// adr x2, hyp_vectors 111f9412d9fSurnenfeld// msr vbar_el2, x2 112f9412d9fSurnenfeld 113f9412d9fSurnenfeld mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 114f9412d9fSurnenfeld msr spsr_el2, x2 115f9412d9fSurnenfeld 116f9412d9fSurnenfeld /* Configure GICv3 CPU interface */ 117f9412d9fSurnenfeld mrs x2, id_aa64pfr0_el1 118f9412d9fSurnenfeld /* Extract GIC bits from the register */ 119f9412d9fSurnenfeld ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 120f9412d9fSurnenfeld /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 121f9412d9fSurnenfeld cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 122f9412d9fSurnenfeld b.ne 2f 123f9412d9fSurnenfeld 124f9412d9fSurnenfeld mrs x2, S3_4_C12_C9_5 125f9412d9fSurnenfeld orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 126f9412d9fSurnenfeld orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 127f9412d9fSurnenfeld msr S3_4_C12_C9_5, x2 128f9412d9fSurnenfeld2: 129f9412d9fSurnenfeld 130f9412d9fSurnenfeld /* Set the address to return to our return address */ 131f9412d9fSurnenfeld msr elr_el2, x30 132f9412d9fSurnenfeld isb 133f9412d9fSurnenfeld 134f9412d9fSurnenfeld eret 135f9412d9fSurnenfeldFUNCTION_END(drop_to_el1) 136f9412d9fSurnenfeld 137f9412d9fSurnenfeld/* Macro Definitions */ 138f9412d9fSurnenfeld .align 3 139f9412d9fSurnenfeld.Lsctlr_res1: 140f9412d9fSurnenfeld .quad SCTLR_RES1 141