1/* 2 * Copyright 2011, François Revol <revol@free.fr>. 3 * All rights reserved. Distributed under the terms of the MIT License. 4 */ 5 6#include <asm_defs.h> 7 8 9 .arch_extension virt 10 .text 11 12/* status_t arch_enter_kernel(uint32_t ttbr, struct kernel_args *kernelArgs, 13 addr_t kernelEntry, addr_t kernelStackTop); 14 15 r0 - ttbr 16 r1 - kernelArgs 17 r2 - kernelEntry 18 r3 - kernelStackTop 19*/ 20FUNCTION(arch_enter_kernel): 21 22 // check whether we are running in HYP mode 23 mrs r9, cpsr 24 and r9, r9, #0x1f 25 26 // proceed to _pl1_entry if we're not in HYP mode 27 cmp r9, #0x1a 28 bne _pl1_entry 29 30 // set SVC mode in SPSR 31 mrs r9, cpsr 32 bic r9, r9, #0x1f 33 orr r9, r9, #0x13 34 msr spsr_cxsf, r9 35 36 // load PL1 entry point address 37 adr lr, _pl1_entry 38 msr elr_hyp, lr 39 40 // drop to PL1 SVC mode 41 eret 42 43_pl1_entry: 44 45 mov r5,r0 46 mov r4,r2 47 48 // set up kernel _start args 49 mov r0,r1 // kernelArgs 50 mov r1,#0 // currentCPU=0 51 52 // enable full access for coprocessors P10, P11 53 // by setting the required flags in Access Control Register 54 MRC p15, #0, r9, c1, c0, #2 55 orr r9, r9, #0x00f00000 56 MCR p15, #0, r9, c1, c0, #2 57 58 // flush prefetch buffer 59 mov r9, #0 60 MCR p15, #0, r9, c7, c5, #4 61 62 // enable FPU 63 mov r9, #0x40000000 64 FMXR FPEXC, r9 65 66 // flush TLB 67 MCR p15, 0, r1, c8, c7, 0 68 69 // set TTBR0 70 // cacheability attributes for the page tables are: 71 // Normal Memory, Inner/Outer Write-Back no Write-Allocate Cacheable 72 73 // Note that this relies on ARMv7 multiprocessing extensions 74 // on uniprocessors we need only the flag 0x01 i.e. Inner Cacheable 75 76 orr r5, r5, #0x59 77 mcr p15, 0, r5, c2, c0, 0 78 79 // initialize TTBCR to zero (no LPAE, use only TTBR0) 80 MCR p15, 0, r1, c2, c0, 2 81 82 // flush TLB (again) 83 MCR p15, 0, r1, c8, c7, 0 84 85 // write DACR 86 mov r9, #0x00000001 87 mcr p15, 0, r9, c3, c0, 0 88 89 // configure PRRR and NMRR for TEX remap 90 91 // set PRRR as follows: 92 // - memory type 0 is Strongly Ordered 93 // - memory type 1 is Shareable Device 94 // - all others are normal memory 95 // - NS/DS bits are configured as 'pass-through' 96 // - all Shareable Normal memory regions are Outer Shareable 97 mov r9, #0x0000aaa4 98 orr r9, #0x000a0000 99 mcr p15, 0, r9, c10, c2, 0 100 101 // set NMRR as follows: 102 // - memory type 2 is Inner/Outer Write-Through 103 // - memory type 3 is Inner/Outer Write-Back, no Write-Allocate 104 // - don't care about the rest 105 mov r9, #0x000000e0 106 orr r9, #0x00e00000 107 mcr p15, 0, r9, c10, c2, 1 108 109 // ensure the PRRR and NMRR registers are updated before enabling MMU 110 dsb 111 isb 112 113 // enable MMU and caches 114 mrc p15, 0, r9, c1, c0, 0 115 orr r9, r9, #0x20000000 // access flag enabled 116 orr r9, r9, #0x10000000 // TEX remap enabled 117 orr r9, r9, #0x00001000 // i-cache enabled 118 orr r9, r9, #0x00000004 // d-cache enabled 119 orr r9, r9, #0x00000001 // MMU enabled 120 mcr p15, 0, r9, c1, c0, 0 121 122 // set the kernel stack 123 mov sp,r3 124 125 // call the kernel 126 mov pc,r4 127 128 // return 129 mov r0,#-1 // B_ERROR 130 mov pc,lr 131 132FUNCTION_END(arch_enter_kernel) 133 134