1 /* 2 * Copyright 2010, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT license. 4 * 5 * Author: 6 * François Revol, revol@free.fr. 7 * 8 */ 9 #ifndef _AMICALLS_H 10 #define _AMICALLS_H 11 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 #ifndef __ASSEMBLER__ 18 #include <OS.h> 19 #include <SupportDefs.h> 20 21 /* 22 General macros for Amiga function calls. Not all the possibilities have 23 been created - only the ones which exist in OS 3.1. Third party libraries 24 and future versions of AmigaOS will maybe need some new ones... 25 26 LPX - functions that take X arguments. 27 28 Modifiers (variations are possible): 29 NR - no return (void), 30 A4, A5 - "a4" or "a5" is used as one of the arguments, 31 UB - base will be given explicitly by user (see cia.resource). 32 FP - one of the parameters has type "pointer to function". 33 34 "bt" arguments are not used - they are provided for backward compatibility 35 only. 36 */ 37 /* those were taken from fd2pragma, but no copyright seems to be claimed on them */ 38 39 #define LP0(offs, rt, name, bt, bn) \ 40 ({ \ 41 ({ \ 42 register int _d1 __asm("d1"); \ 43 register int _a0 __asm("a0"); \ 44 register int _a1 __asm("a1"); \ 45 register rt _##name##_re __asm("d0"); \ 46 register void *const _##name##_bn __asm("a6") = (bn); \ 47 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 48 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 49 : "r" (_##name##_bn) \ 50 : "fp0", "fp1", "cc", "memory"); \ 51 _##name##_re; \ 52 }); \ 53 }) 54 55 #define LP0NR(offs, name, bt, bn) \ 56 ({ \ 57 { \ 58 register int _d0 __asm("d0"); \ 59 register int _d1 __asm("d1"); \ 60 register int _a0 __asm("a0"); \ 61 register int _a1 __asm("a1"); \ 62 register void *const _##name##_bn __asm("a6") = (bn); \ 63 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 64 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 65 : "r" (_##name##_bn) \ 66 : "fp0", "fp1", "cc", "memory"); \ 67 } \ 68 }) 69 70 #define LP1(offs, rt, name, t1, v1, r1, bt, bn) \ 71 ({ \ 72 t1 _##name##_v1 = (v1); \ 73 ({ \ 74 register int _d1 __asm("d1"); \ 75 register int _a0 __asm("a0"); \ 76 register int _a1 __asm("a1"); \ 77 register rt _##name##_re __asm("d0"); \ 78 register void *const _##name##_bn __asm("a6") = (bn); \ 79 register t1 _n1 __asm(#r1) = _##name##_v1; \ 80 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 81 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 82 : "r" (_##name##_bn), "rf"(_n1) \ 83 : "fp0", "fp1", "cc", "memory"); \ 84 _##name##_re; \ 85 }); \ 86 }) 87 88 #define LP1NR(offs, name, t1, v1, r1, bt, bn) \ 89 ({ \ 90 t1 _##name##_v1 = (v1); \ 91 { \ 92 register int _d0 __asm("d0"); \ 93 register int _d1 __asm("d1"); \ 94 register int _a0 __asm("a0"); \ 95 register int _a1 __asm("a1"); \ 96 register void *const _##name##_bn __asm("a6") = (bn); \ 97 register t1 _n1 __asm(#r1) = _##name##_v1; \ 98 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 99 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 100 : "r" (_##name##_bn), "rf"(_n1) \ 101 : "fp0", "fp1", "cc", "memory"); \ 102 } \ 103 }) 104 105 /* Only graphics.library/AttemptLockLayerRom() */ 106 #define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \ 107 ({ \ 108 t1 _##name##_v1 = (v1); \ 109 ({ \ 110 register int _d1 __asm("d1"); \ 111 register int _a0 __asm("a0"); \ 112 register int _a1 __asm("a1"); \ 113 register rt _##name##_re __asm("d0"); \ 114 register void *const _##name##_bn __asm("a6") = (bn); \ 115 register t1 _n1 __asm(#r1) = _##name##_v1; \ 116 __asm volatile ("exg d7,a5\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a5" \ 117 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 118 : "r" (_##name##_bn), "rf"(_n1) \ 119 : "fp0", "fp1", "cc", "memory"); \ 120 _##name##_re; \ 121 }); \ 122 }) 123 124 /* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */ 125 #define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \ 126 ({ \ 127 t1 _##name##_v1 = (v1); \ 128 { \ 129 register int _d0 __asm("d0"); \ 130 register int _d1 __asm("d1"); \ 131 register int _a0 __asm("a0"); \ 132 register int _a1 __asm("a1"); \ 133 register void *const _##name##_bn __asm("a6") = (bn); \ 134 register t1 _n1 __asm(#r1) = _##name##_v1; \ 135 __asm volatile ("exg d7,a5\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a5" \ 136 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 137 : "r" (_##name##_bn), "rf"(_n1) \ 138 : "fp0", "fp1", "cc", "memory"); \ 139 } \ 140 }) 141 142 /* Only exec.library/Supervisor() */ 143 #define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \ 144 ({ \ 145 typedef fpt; \ 146 t1 _##name##_v1 = (v1); \ 147 ({ \ 148 register int _d1 __asm("d1"); \ 149 register int _a0 __asm("a0"); \ 150 register int _a1 __asm("a1"); \ 151 register rt _##name##_re __asm("d0"); \ 152 register void *const _##name##_bn __asm("a6") = (bn); \ 153 register t1 _n1 __asm(#r1) = _##name##_v1; \ 154 __asm volatile ("exg d7,a5\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a5" \ 155 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 156 : "r" (_##name##_bn), "rf"(_n1) \ 157 : "fp0", "fp1", "cc", "memory"); \ 158 _##name##_re; \ 159 }); \ 160 }) 161 162 #define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \ 163 ({ \ 164 t1 _##name##_v1 = (v1); \ 165 t2 _##name##_v2 = (v2); \ 166 ({ \ 167 register int _d1 __asm("d1"); \ 168 register int _a0 __asm("a0"); \ 169 register int _a1 __asm("a1"); \ 170 register rt _##name##_re __asm("d0"); \ 171 register void *const _##name##_bn __asm("a6") = (bn); \ 172 register t1 _n1 __asm(#r1) = _##name##_v1; \ 173 register t2 _n2 __asm(#r2) = _##name##_v2; \ 174 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 175 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 176 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ 177 : "fp0", "fp1", "cc", "memory"); \ 178 _##name##_re; \ 179 }); \ 180 }) 181 182 #define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \ 183 ({ \ 184 t1 _##name##_v1 = (v1); \ 185 t2 _##name##_v2 = (v2); \ 186 { \ 187 register int _d0 __asm("d0"); \ 188 register int _d1 __asm("d1"); \ 189 register int _a0 __asm("a0"); \ 190 register int _a1 __asm("a1"); \ 191 register void *const _##name##_bn __asm("a6") = (bn); \ 192 register t1 _n1 __asm(#r1) = _##name##_v1; \ 193 register t2 _n2 __asm(#r2) = _##name##_v2; \ 194 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 195 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 196 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ 197 : "fp0", "fp1", "cc", "memory"); \ 198 } \ 199 }) 200 201 /* Only cia.resource/AbleICR() and cia.resource/SetICR() */ 202 #define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \ 203 ({ \ 204 t1 _##name##_v1 = (v1); \ 205 t2 _##name##_v2 = (v2); \ 206 ({ \ 207 register int _d1 __asm("d1"); \ 208 register int _a0 __asm("a0"); \ 209 register int _a1 __asm("a1"); \ 210 register rt _##name##_re __asm("d0"); \ 211 register t1 _n1 __asm(#r1) = _##name##_v1; \ 212 register t2 _n2 __asm(#r2) = _##name##_v2; \ 213 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 214 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 215 : "r"(_n1), "rf"(_n2) \ 216 : "fp0", "fp1", "cc", "memory"); \ 217 _##name##_re; \ 218 }); \ 219 }) 220 221 /* Only dos.library/InternalUnLoadSeg() */ 222 #define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \ 223 ({ \ 224 typedef fpt; \ 225 t1 _##name##_v1 = (v1); \ 226 t2 _##name##_v2 = (v2); \ 227 ({ \ 228 register int _d1 __asm("d1"); \ 229 register int _a0 __asm("a0"); \ 230 register int _a1 __asm("a1"); \ 231 register rt _##name##_re __asm("d0"); \ 232 register void *const _##name##_bn __asm("a6") = (bn); \ 233 register t1 _n1 __asm(#r1) = _##name##_v1; \ 234 register t2 _n2 __asm(#r2) = _##name##_v2; \ 235 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 236 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 237 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ 238 : "fp0", "fp1", "cc", "memory"); \ 239 _##name##_re; \ 240 }); \ 241 }) 242 243 #define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ 244 ({ \ 245 t1 _##name##_v1 = (v1); \ 246 t2 _##name##_v2 = (v2); \ 247 t3 _##name##_v3 = (v3); \ 248 ({ \ 249 register int _d1 __asm("d1"); \ 250 register int _a0 __asm("a0"); \ 251 register int _a1 __asm("a1"); \ 252 register rt _##name##_re __asm("d0"); \ 253 register void *const _##name##_bn __asm("a6") = (bn); \ 254 register t1 _n1 __asm(#r1) = _##name##_v1; \ 255 register t2 _n2 __asm(#r2) = _##name##_v2; \ 256 register t3 _n3 __asm(#r3) = _##name##_v3; \ 257 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 258 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 259 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 260 : "fp0", "fp1", "cc", "memory"); \ 261 _##name##_re; \ 262 }); \ 263 }) 264 265 #define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ 266 ({ \ 267 t1 _##name##_v1 = (v1); \ 268 t2 _##name##_v2 = (v2); \ 269 t3 _##name##_v3 = (v3); \ 270 { \ 271 register int _d0 __asm("d0"); \ 272 register int _d1 __asm("d1"); \ 273 register int _a0 __asm("a0"); \ 274 register int _a1 __asm("a1"); \ 275 register void *const _##name##_bn __asm("a6") = (bn); \ 276 register t1 _n1 __asm(#r1) = _##name##_v1; \ 277 register t2 _n2 __asm(#r2) = _##name##_v2; \ 278 register t3 _n3 __asm(#r3) = _##name##_v3; \ 279 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 280 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 281 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 282 : "fp0", "fp1", "cc", "memory"); \ 283 } \ 284 }) 285 286 /* Only cia.resource/AddICRVector() */ 287 #define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ 288 ({ \ 289 t1 _##name##_v1 = (v1); \ 290 t2 _##name##_v2 = (v2); \ 291 t3 _##name##_v3 = (v3); \ 292 ({ \ 293 register int _d1 __asm("d1"); \ 294 register int _a0 __asm("a0"); \ 295 register int _a1 __asm("a1"); \ 296 register rt _##name##_re __asm("d0"); \ 297 register t1 _n1 __asm(#r1) = _##name##_v1; \ 298 register t2 _n2 __asm(#r2) = _##name##_v2; \ 299 register t3 _n3 __asm(#r3) = _##name##_v3; \ 300 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 301 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 302 : "r"(_n1), "rf"(_n2), "rf"(_n3) \ 303 : "fp0", "fp1", "cc", "memory"); \ 304 _##name##_re; \ 305 }); \ 306 }) 307 308 /* Only cia.resource/RemICRVector() */ 309 #define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ 310 ({ \ 311 t1 _##name##_v1 = (v1); \ 312 t2 _##name##_v2 = (v2); \ 313 t3 _##name##_v3 = (v3); \ 314 { \ 315 register int _d0 __asm("d0"); \ 316 register int _d1 __asm("d1"); \ 317 register int _a0 __asm("a0"); \ 318 register int _a1 __asm("a1"); \ 319 register t1 _n1 __asm(#r1) = _##name##_v1; \ 320 register t2 _n2 __asm(#r2) = _##name##_v2; \ 321 register t3 _n3 __asm(#r3) = _##name##_v3; \ 322 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 323 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 324 : "r"(_n1), "rf"(_n2), "rf"(_n3) \ 325 : "fp0", "fp1", "cc", "memory"); \ 326 } \ 327 }) 328 329 /* Only exec.library/SetFunction() */ 330 #define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ 331 ({ \ 332 typedef fpt; \ 333 t1 _##name##_v1 = (v1); \ 334 t2 _##name##_v2 = (v2); \ 335 t3 _##name##_v3 = (v3); \ 336 ({ \ 337 register int _d1 __asm("d1"); \ 338 register int _a0 __asm("a0"); \ 339 register int _a1 __asm("a1"); \ 340 register rt _##name##_re __asm("d0"); \ 341 register void *const _##name##_bn __asm("a6") = (bn); \ 342 register t1 _n1 __asm(#r1) = _##name##_v1; \ 343 register t2 _n2 __asm(#r2) = _##name##_v2; \ 344 register t3 _n3 __asm(#r3) = _##name##_v3; \ 345 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 346 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 347 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 348 : "fp0", "fp1", "cc", "memory"); \ 349 _##name##_re; \ 350 }); \ 351 }) 352 353 /* Only graphics.library/SetCollision() */ 354 #define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ 355 ({ \ 356 typedef fpt; \ 357 t1 _##name##_v1 = (v1); \ 358 t2 _##name##_v2 = (v2); \ 359 t3 _##name##_v3 = (v3); \ 360 { \ 361 register int _d0 __asm("d0"); \ 362 register int _d1 __asm("d1"); \ 363 register int _a0 __asm("a0"); \ 364 register int _a1 __asm("a1"); \ 365 register void *const _##name##_bn __asm("a6") = (bn); \ 366 register t1 _n1 __asm(#r1) = _##name##_v1; \ 367 register t2 _n2 __asm(#r2) = _##name##_v2; \ 368 register t3 _n3 __asm(#r3) = _##name##_v3; \ 369 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 370 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 371 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ 372 : "fp0", "fp1", "cc", "memory"); \ 373 } \ 374 }) 375 376 #define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ 377 ({ \ 378 t1 _##name##_v1 = (v1); \ 379 t2 _##name##_v2 = (v2); \ 380 t3 _##name##_v3 = (v3); \ 381 t4 _##name##_v4 = (v4); \ 382 ({ \ 383 register int _d1 __asm("d1"); \ 384 register int _a0 __asm("a0"); \ 385 register int _a1 __asm("a1"); \ 386 register rt _##name##_re __asm("d0"); \ 387 register void *const _##name##_bn __asm("a6") = (bn); \ 388 register t1 _n1 __asm(#r1) = _##name##_v1; \ 389 register t2 _n2 __asm(#r2) = _##name##_v2; \ 390 register t3 _n3 __asm(#r3) = _##name##_v3; \ 391 register t4 _n4 __asm(#r4) = _##name##_v4; \ 392 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 393 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 394 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ 395 : "fp0", "fp1", "cc", "memory"); \ 396 _##name##_re; \ 397 }); \ 398 }) 399 400 #define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ 401 ({ \ 402 t1 _##name##_v1 = (v1); \ 403 t2 _##name##_v2 = (v2); \ 404 t3 _##name##_v3 = (v3); \ 405 t4 _##name##_v4 = (v4); \ 406 { \ 407 register int _d0 __asm("d0"); \ 408 register int _d1 __asm("d1"); \ 409 register int _a0 __asm("a0"); \ 410 register int _a1 __asm("a1"); \ 411 register void *const _##name##_bn __asm("a6") = (bn); \ 412 register t1 _n1 __asm(#r1) = _##name##_v1; \ 413 register t2 _n2 __asm(#r2) = _##name##_v2; \ 414 register t3 _n3 __asm(#r3) = _##name##_v3; \ 415 register t4 _n4 __asm(#r4) = _##name##_v4; \ 416 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 417 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 418 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ 419 : "fp0", "fp1", "cc", "memory"); \ 420 } \ 421 }) 422 423 /* Only exec.library/RawDoFmt() */ 424 #define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \ 425 ({ \ 426 typedef fpt; \ 427 t1 _##name##_v1 = (v1); \ 428 t2 _##name##_v2 = (v2); \ 429 t3 _##name##_v3 = (v3); \ 430 t4 _##name##_v4 = (v4); \ 431 ({ \ 432 register int _d1 __asm("d1"); \ 433 register int _a0 __asm("a0"); \ 434 register int _a1 __asm("a1"); \ 435 register rt _##name##_re __asm("d0"); \ 436 register void *const _##name##_bn __asm("a6") = (bn); \ 437 register t1 _n1 __asm(#r1) = _##name##_v1; \ 438 register t2 _n2 __asm(#r2) = _##name##_v2; \ 439 register t3 _n3 __asm(#r3) = _##name##_v3; \ 440 register t4 _n4 __asm(#r4) = _##name##_v4; \ 441 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 442 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 443 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ 444 : "fp0", "fp1", "cc", "memory"); \ 445 _##name##_re; \ 446 }); \ 447 }) 448 449 #define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ 450 ({ \ 451 t1 _##name##_v1 = (v1); \ 452 t2 _##name##_v2 = (v2); \ 453 t3 _##name##_v3 = (v3); \ 454 t4 _##name##_v4 = (v4); \ 455 t5 _##name##_v5 = (v5); \ 456 ({ \ 457 register int _d1 __asm("d1"); \ 458 register int _a0 __asm("a0"); \ 459 register int _a1 __asm("a1"); \ 460 register rt _##name##_re __asm("d0"); \ 461 register void *const _##name##_bn __asm("a6") = (bn); \ 462 register t1 _n1 __asm(#r1) = _##name##_v1; \ 463 register t2 _n2 __asm(#r2) = _##name##_v2; \ 464 register t3 _n3 __asm(#r3) = _##name##_v3; \ 465 register t4 _n4 __asm(#r4) = _##name##_v4; \ 466 register t5 _n5 __asm(#r5) = _##name##_v5; \ 467 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 468 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 469 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 470 : "fp0", "fp1", "cc", "memory"); \ 471 _##name##_re; \ 472 }); \ 473 }) 474 475 #define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ 476 ({ \ 477 t1 _##name##_v1 = (v1); \ 478 t2 _##name##_v2 = (v2); \ 479 t3 _##name##_v3 = (v3); \ 480 t4 _##name##_v4 = (v4); \ 481 t5 _##name##_v5 = (v5); \ 482 { \ 483 register int _d0 __asm("d0"); \ 484 register int _d1 __asm("d1"); \ 485 register int _a0 __asm("a0"); \ 486 register int _a1 __asm("a1"); \ 487 register void *const _##name##_bn __asm("a6") = (bn); \ 488 register t1 _n1 __asm(#r1) = _##name##_v1; \ 489 register t2 _n2 __asm(#r2) = _##name##_v2; \ 490 register t3 _n3 __asm(#r3) = _##name##_v3; \ 491 register t4 _n4 __asm(#r4) = _##name##_v4; \ 492 register t5 _n5 __asm(#r5) = _##name##_v5; \ 493 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 494 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 495 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 496 : "fp0", "fp1", "cc", "memory"); \ 497 } \ 498 }) 499 500 /* Only exec.library/MakeLibrary() */ 501 #define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \ 502 ({ \ 503 typedef fpt; \ 504 t1 _##name##_v1 = (v1); \ 505 t2 _##name##_v2 = (v2); \ 506 t3 _##name##_v3 = (v3); \ 507 t4 _##name##_v4 = (v4); \ 508 t5 _##name##_v5 = (v5); \ 509 ({ \ 510 register int _d1 __asm("d1"); \ 511 register int _a0 __asm("a0"); \ 512 register int _a1 __asm("a1"); \ 513 register rt _##name##_re __asm("d0"); \ 514 register void *const _##name##_bn __asm("a6") = (bn); \ 515 register t1 _n1 __asm(#r1) = _##name##_v1; \ 516 register t2 _n2 __asm(#r2) = _##name##_v2; \ 517 register t3 _n3 __asm(#r3) = _##name##_v3; \ 518 register t4 _n4 __asm(#r4) = _##name##_v4; \ 519 register t5 _n5 __asm(#r5) = _##name##_v5; \ 520 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 521 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 522 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 523 : "fp0", "fp1", "cc", "memory"); \ 524 _##name##_re; \ 525 }); \ 526 }) 527 528 /* Only reqtools.library/XXX() */ 529 #define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ 530 ({ \ 531 t1 _##name##_v1 = (v1); \ 532 t2 _##name##_v2 = (v2); \ 533 t3 _##name##_v3 = (v3); \ 534 t4 _##name##_v4 = (v4); \ 535 t5 _##name##_v5 = (v5); \ 536 ({ \ 537 register int _d1 __asm("d1"); \ 538 register int _a0 __asm("a0"); \ 539 register int _a1 __asm("a1"); \ 540 register rt _##name##_re __asm("d0"); \ 541 register void *const _##name##_bn __asm("a6") = (bn); \ 542 register t1 _n1 __asm(#r1) = _##name##_v1; \ 543 register t2 _n2 __asm(#r2) = _##name##_v2; \ 544 register t3 _n3 __asm(#r3) = _##name##_v3; \ 545 register t4 _n4 __asm(#r4) = _##name##_v4; \ 546 register t5 _n5 __asm(#r5) = _##name##_v5; \ 547 __asm volatile ("exg d7,a4\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a4" \ 548 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 549 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ 550 : "fp0", "fp1", "cc", "memory"); \ 551 _##name##_re; \ 552 }); \ 553 }) 554 555 #define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ 556 ({ \ 557 t1 _##name##_v1 = (v1); \ 558 t2 _##name##_v2 = (v2); \ 559 t3 _##name##_v3 = (v3); \ 560 t4 _##name##_v4 = (v4); \ 561 t5 _##name##_v5 = (v5); \ 562 t6 _##name##_v6 = (v6); \ 563 ({ \ 564 register int _d1 __asm("d1"); \ 565 register int _a0 __asm("a0"); \ 566 register int _a1 __asm("a1"); \ 567 register rt _##name##_re __asm("d0"); \ 568 register void *const _##name##_bn __asm("a6") = (bn); \ 569 register t1 _n1 __asm(#r1) = _##name##_v1; \ 570 register t2 _n2 __asm(#r2) = _##name##_v2; \ 571 register t3 _n3 __asm(#r3) = _##name##_v3; \ 572 register t4 _n4 __asm(#r4) = _##name##_v4; \ 573 register t5 _n5 __asm(#r5) = _##name##_v5; \ 574 register t6 _n6 __asm(#r6) = _##name##_v6; \ 575 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 576 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 577 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ 578 : "fp0", "fp1", "cc", "memory"); \ 579 _##name##_re; \ 580 }); \ 581 }) 582 583 #define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ 584 ({ \ 585 t1 _##name##_v1 = (v1); \ 586 t2 _##name##_v2 = (v2); \ 587 t3 _##name##_v3 = (v3); \ 588 t4 _##name##_v4 = (v4); \ 589 t5 _##name##_v5 = (v5); \ 590 t6 _##name##_v6 = (v6); \ 591 { \ 592 register int _d0 __asm("d0"); \ 593 register int _d1 __asm("d1"); \ 594 register int _a0 __asm("a0"); \ 595 register int _a1 __asm("a1"); \ 596 register void *const _##name##_bn __asm("a6") = (bn); \ 597 register t1 _n1 __asm(#r1) = _##name##_v1; \ 598 register t2 _n2 __asm(#r2) = _##name##_v2; \ 599 register t3 _n3 __asm(#r3) = _##name##_v3; \ 600 register t4 _n4 __asm(#r4) = _##name##_v4; \ 601 register t5 _n5 __asm(#r5) = _##name##_v5; \ 602 register t6 _n6 __asm(#r6) = _##name##_v6; \ 603 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 604 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 605 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ 606 : "fp0", "fp1", "cc", "memory"); \ 607 } \ 608 }) 609 610 #define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ 611 ({ \ 612 t1 _##name##_v1 = (v1); \ 613 t2 _##name##_v2 = (v2); \ 614 t3 _##name##_v3 = (v3); \ 615 t4 _##name##_v4 = (v4); \ 616 t5 _##name##_v5 = (v5); \ 617 t6 _##name##_v6 = (v6); \ 618 t7 _##name##_v7 = (v7); \ 619 ({ \ 620 register int _d1 __asm("d1"); \ 621 register int _a0 __asm("a0"); \ 622 register int _a1 __asm("a1"); \ 623 register rt _##name##_re __asm("d0"); \ 624 register void *const _##name##_bn __asm("a6") = (bn); \ 625 register t1 _n1 __asm(#r1) = _##name##_v1; \ 626 register t2 _n2 __asm(#r2) = _##name##_v2; \ 627 register t3 _n3 __asm(#r3) = _##name##_v3; \ 628 register t4 _n4 __asm(#r4) = _##name##_v4; \ 629 register t5 _n5 __asm(#r5) = _##name##_v5; \ 630 register t6 _n6 __asm(#r6) = _##name##_v6; \ 631 register t7 _n7 __asm(#r7) = _##name##_v7; \ 632 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 633 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 634 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ 635 : "fp0", "fp1", "cc", "memory"); \ 636 _##name##_re; \ 637 }); \ 638 }) 639 640 #define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ 641 ({ \ 642 t1 _##name##_v1 = (v1); \ 643 t2 _##name##_v2 = (v2); \ 644 t3 _##name##_v3 = (v3); \ 645 t4 _##name##_v4 = (v4); \ 646 t5 _##name##_v5 = (v5); \ 647 t6 _##name##_v6 = (v6); \ 648 t7 _##name##_v7 = (v7); \ 649 { \ 650 register int _d0 __asm("d0"); \ 651 register int _d1 __asm("d1"); \ 652 register int _a0 __asm("a0"); \ 653 register int _a1 __asm("a1"); \ 654 register void *const _##name##_bn __asm("a6") = (bn); \ 655 register t1 _n1 __asm(#r1) = _##name##_v1; \ 656 register t2 _n2 __asm(#r2) = _##name##_v2; \ 657 register t3 _n3 __asm(#r3) = _##name##_v3; \ 658 register t4 _n4 __asm(#r4) = _##name##_v4; \ 659 register t5 _n5 __asm(#r5) = _##name##_v5; \ 660 register t6 _n6 __asm(#r6) = _##name##_v6; \ 661 register t7 _n7 __asm(#r7) = _##name##_v7; \ 662 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 663 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 664 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ 665 : "fp0", "fp1", "cc", "memory"); \ 666 } \ 667 }) 668 669 /* Only workbench.library/AddAppIconA() */ 670 #define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ 671 ({ \ 672 t1 _##name##_v1 = (v1); \ 673 t2 _##name##_v2 = (v2); \ 674 t3 _##name##_v3 = (v3); \ 675 t4 _##name##_v4 = (v4); \ 676 t5 _##name##_v5 = (v5); \ 677 t6 _##name##_v6 = (v6); \ 678 t7 _##name##_v7 = (v7); \ 679 ({ \ 680 register int _d1 __asm("d1"); \ 681 register int _a0 __asm("a0"); \ 682 register int _a1 __asm("a1"); \ 683 register rt _##name##_re __asm("d0"); \ 684 register void *const _##name##_bn __asm("a6") = (bn); \ 685 register t1 _n1 __asm(#r1) = _##name##_v1; \ 686 register t2 _n2 __asm(#r2) = _##name##_v2; \ 687 register t3 _n3 __asm(#r3) = _##name##_v3; \ 688 register t4 _n4 __asm(#r4) = _##name##_v4; \ 689 register t5 _n5 __asm(#r5) = _##name##_v5; \ 690 register t6 _n6 __asm(#r6) = _##name##_v6; \ 691 register t7 _n7 __asm(#r7) = _##name##_v7; \ 692 __asm volatile ("exg d7,a4\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a4" \ 693 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 694 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ 695 : "fp0", "fp1", "cc", "memory"); \ 696 _##name##_re; \ 697 }); \ 698 }) 699 700 /* Would you believe that there really are beasts that need more than 7 701 arguments? :-) */ 702 703 /* For example intuition.library/AutoRequest() */ 704 #define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ 705 ({ \ 706 t1 _##name##_v1 = (v1); \ 707 t2 _##name##_v2 = (v2); \ 708 t3 _##name##_v3 = (v3); \ 709 t4 _##name##_v4 = (v4); \ 710 t5 _##name##_v5 = (v5); \ 711 t6 _##name##_v6 = (v6); \ 712 t7 _##name##_v7 = (v7); \ 713 t8 _##name##_v8 = (v8); \ 714 ({ \ 715 register int _d1 __asm("d1"); \ 716 register int _a0 __asm("a0"); \ 717 register int _a1 __asm("a1"); \ 718 register rt _##name##_re __asm("d0"); \ 719 register void *const _##name##_bn __asm("a6") = (bn); \ 720 register t1 _n1 __asm(#r1) = _##name##_v1; \ 721 register t2 _n2 __asm(#r2) = _##name##_v2; \ 722 register t3 _n3 __asm(#r3) = _##name##_v3; \ 723 register t4 _n4 __asm(#r4) = _##name##_v4; \ 724 register t5 _n5 __asm(#r5) = _##name##_v5; \ 725 register t6 _n6 __asm(#r6) = _##name##_v6; \ 726 register t7 _n7 __asm(#r7) = _##name##_v7; \ 727 register t8 _n8 __asm(#r8) = _##name##_v8; \ 728 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 729 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 730 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ 731 : "fp0", "fp1", "cc", "memory"); \ 732 _##name##_re; \ 733 }); \ 734 }) 735 736 /* For example intuition.library/ModifyProp() */ 737 #define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ 738 ({ \ 739 t1 _##name##_v1 = (v1); \ 740 t2 _##name##_v2 = (v2); \ 741 t3 _##name##_v3 = (v3); \ 742 t4 _##name##_v4 = (v4); \ 743 t5 _##name##_v5 = (v5); \ 744 t6 _##name##_v6 = (v6); \ 745 t7 _##name##_v7 = (v7); \ 746 t8 _##name##_v8 = (v8); \ 747 { \ 748 register int _d0 __asm("d0"); \ 749 register int _d1 __asm("d1"); \ 750 register int _a0 __asm("a0"); \ 751 register int _a1 __asm("a1"); \ 752 register void *const _##name##_bn __asm("a6") = (bn); \ 753 register t1 _n1 __asm(#r1) = _##name##_v1; \ 754 register t2 _n2 __asm(#r2) = _##name##_v2; \ 755 register t3 _n3 __asm(#r3) = _##name##_v3; \ 756 register t4 _n4 __asm(#r4) = _##name##_v4; \ 757 register t5 _n5 __asm(#r5) = _##name##_v5; \ 758 register t6 _n6 __asm(#r6) = _##name##_v6; \ 759 register t7 _n7 __asm(#r7) = _##name##_v7; \ 760 register t8 _n8 __asm(#r8) = _##name##_v8; \ 761 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 762 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 763 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ 764 : "fp0", "fp1", "cc", "memory"); \ 765 } \ 766 }) 767 768 /* For example layers.library/CreateUpfrontHookLayer() */ 769 #define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ 770 ({ \ 771 t1 _##name##_v1 = (v1); \ 772 t2 _##name##_v2 = (v2); \ 773 t3 _##name##_v3 = (v3); \ 774 t4 _##name##_v4 = (v4); \ 775 t5 _##name##_v5 = (v5); \ 776 t6 _##name##_v6 = (v6); \ 777 t7 _##name##_v7 = (v7); \ 778 t8 _##name##_v8 = (v8); \ 779 t9 _##name##_v9 = (v9); \ 780 ({ \ 781 register int _d1 __asm("d1"); \ 782 register int _a0 __asm("a0"); \ 783 register int _a1 __asm("a1"); \ 784 register rt _##name##_re __asm("d0"); \ 785 register void *const _##name##_bn __asm("a6") = (bn); \ 786 register t1 _n1 __asm(#r1) = _##name##_v1; \ 787 register t2 _n2 __asm(#r2) = _##name##_v2; \ 788 register t3 _n3 __asm(#r3) = _##name##_v3; \ 789 register t4 _n4 __asm(#r4) = _##name##_v4; \ 790 register t5 _n5 __asm(#r5) = _##name##_v5; \ 791 register t6 _n6 __asm(#r6) = _##name##_v6; \ 792 register t7 _n7 __asm(#r7) = _##name##_v7; \ 793 register t8 _n8 __asm(#r8) = _##name##_v8; \ 794 register t9 _n9 __asm(#r9) = _##name##_v9; \ 795 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 796 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 797 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ 798 : "fp0", "fp1", "cc", "memory"); \ 799 _##name##_re; \ 800 }); \ 801 }) 802 803 /* For example intuition.library/NewModifyProp() */ 804 #define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ 805 ({ \ 806 t1 _##name##_v1 = (v1); \ 807 t2 _##name##_v2 = (v2); \ 808 t3 _##name##_v3 = (v3); \ 809 t4 _##name##_v4 = (v4); \ 810 t5 _##name##_v5 = (v5); \ 811 t6 _##name##_v6 = (v6); \ 812 t7 _##name##_v7 = (v7); \ 813 t8 _##name##_v8 = (v8); \ 814 t9 _##name##_v9 = (v9); \ 815 { \ 816 register int _d0 __asm("d0"); \ 817 register int _d1 __asm("d1"); \ 818 register int _a0 __asm("a0"); \ 819 register int _a1 __asm("a1"); \ 820 register void *const _##name##_bn __asm("a6") = (bn); \ 821 register t1 _n1 __asm(#r1) = _##name##_v1; \ 822 register t2 _n2 __asm(#r2) = _##name##_v2; \ 823 register t3 _n3 __asm(#r3) = _##name##_v3; \ 824 register t4 _n4 __asm(#r4) = _##name##_v4; \ 825 register t5 _n5 __asm(#r5) = _##name##_v5; \ 826 register t6 _n6 __asm(#r6) = _##name##_v6; \ 827 register t7 _n7 __asm(#r7) = _##name##_v7; \ 828 register t8 _n8 __asm(#r8) = _##name##_v8; \ 829 register t9 _n9 __asm(#r9) = _##name##_v9; \ 830 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 831 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 832 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ 833 : "fp0", "fp1", "cc", "memory"); \ 834 } \ 835 }) 836 837 /* Kriton Kyrimis <kyrimis@cti.gr> says CyberGraphics needs the following */ 838 #define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ 839 ({ \ 840 t1 _##name##_v1 = (v1); \ 841 t2 _##name##_v2 = (v2); \ 842 t3 _##name##_v3 = (v3); \ 843 t4 _##name##_v4 = (v4); \ 844 t5 _##name##_v5 = (v5); \ 845 t6 _##name##_v6 = (v6); \ 846 t7 _##name##_v7 = (v7); \ 847 t8 _##name##_v8 = (v8); \ 848 t9 _##name##_v9 = (v9); \ 849 t10 _##name##_v10 = (v10); \ 850 ({ \ 851 register int _d1 __asm("d1"); \ 852 register int _a0 __asm("a0"); \ 853 register int _a1 __asm("a1"); \ 854 register rt _##name##_re __asm("d0"); \ 855 register void *const _##name##_bn __asm("a6") = (bn); \ 856 register t1 _n1 __asm(#r1) = _##name##_v1; \ 857 register t2 _n2 __asm(#r2) = _##name##_v2; \ 858 register t3 _n3 __asm(#r3) = _##name##_v3; \ 859 register t4 _n4 __asm(#r4) = _##name##_v4; \ 860 register t5 _n5 __asm(#r5) = _##name##_v5; \ 861 register t6 _n6 __asm(#r6) = _##name##_v6; \ 862 register t7 _n7 __asm(#r7) = _##name##_v7; \ 863 register t8 _n8 __asm(#r8) = _##name##_v8; \ 864 register t9 _n9 __asm(#r9) = _##name##_v9; \ 865 register t10 _n10 __asm(#r10) = _##name##_v10; \ 866 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 867 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 868 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ 869 : "fp0", "fp1", "cc", "memory"); \ 870 _##name##_re; \ 871 }); \ 872 }) 873 874 /* Only graphics.library/BltMaskBitMapRastPort() */ 875 #define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ 876 ({ \ 877 t1 _##name##_v1 = (v1); \ 878 t2 _##name##_v2 = (v2); \ 879 t3 _##name##_v3 = (v3); \ 880 t4 _##name##_v4 = (v4); \ 881 t5 _##name##_v5 = (v5); \ 882 t6 _##name##_v6 = (v6); \ 883 t7 _##name##_v7 = (v7); \ 884 t8 _##name##_v8 = (v8); \ 885 t9 _##name##_v9 = (v9); \ 886 t10 _##name##_v10 = (v10); \ 887 { \ 888 register int _d0 __asm("d0"); \ 889 register int _d1 __asm("d1"); \ 890 register int _a0 __asm("a0"); \ 891 register int _a1 __asm("a1"); \ 892 register void *const _##name##_bn __asm("a6") = (bn); \ 893 register t1 _n1 __asm(#r1) = _##name##_v1; \ 894 register t2 _n2 __asm(#r2) = _##name##_v2; \ 895 register t3 _n3 __asm(#r3) = _##name##_v3; \ 896 register t4 _n4 __asm(#r4) = _##name##_v4; \ 897 register t5 _n5 __asm(#r5) = _##name##_v5; \ 898 register t6 _n6 __asm(#r6) = _##name##_v6; \ 899 register t7 _n7 __asm(#r7) = _##name##_v7; \ 900 register t8 _n8 __asm(#r8) = _##name##_v8; \ 901 register t9 _n9 __asm(#r9) = _##name##_v9; \ 902 register t10 _n10 __asm(#r10) = _##name##_v10; \ 903 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 904 : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 905 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ 906 : "fp0", "fp1", "cc", "memory"); \ 907 } \ 908 }) 909 910 /* Only graphics.library/BltBitMap() */ 911 #define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \ 912 ({ \ 913 t1 _##name##_v1 = (v1); \ 914 t2 _##name##_v2 = (v2); \ 915 t3 _##name##_v3 = (v3); \ 916 t4 _##name##_v4 = (v4); \ 917 t5 _##name##_v5 = (v5); \ 918 t6 _##name##_v6 = (v6); \ 919 t7 _##name##_v7 = (v7); \ 920 t8 _##name##_v8 = (v8); \ 921 t9 _##name##_v9 = (v9); \ 922 t10 _##name##_v10 = (v10); \ 923 t11 _##name##_v11 = (v11); \ 924 ({ \ 925 register int _d1 __asm("d1"); \ 926 register int _a0 __asm("a0"); \ 927 register int _a1 __asm("a1"); \ 928 register rt _##name##_re __asm("d0"); \ 929 register void *const _##name##_bn __asm("a6") = (bn); \ 930 register t1 _n1 __asm(#r1) = _##name##_v1; \ 931 register t2 _n2 __asm(#r2) = _##name##_v2; \ 932 register t3 _n3 __asm(#r3) = _##name##_v3; \ 933 register t4 _n4 __asm(#r4) = _##name##_v4; \ 934 register t5 _n5 __asm(#r5) = _##name##_v5; \ 935 register t6 _n6 __asm(#r6) = _##name##_v6; \ 936 register t7 _n7 __asm(#r7) = _##name##_v7; \ 937 register t8 _n8 __asm(#r8) = _##name##_v8; \ 938 register t9 _n9 __asm(#r9) = _##name##_v9; \ 939 register t10 _n10 __asm(#r10) = _##name##_v10; \ 940 register t11 _n11 __asm(#r11) = _##name##_v11; \ 941 __asm volatile ("jsr %%a6@(-"#offs":W)" \ 942 : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ 943 : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \ 944 : "fp0", "fp1", "cc", "memory"); \ 945 _##name##_re; \ 946 }); \ 947 }) 948 949 typedef void *APTR; 950 951 #endif /* __ASSEMBLER__ */ 952 953 // #pragma mark - 954 955 956 #ifndef __ASSEMBLER__ 957 958 // <exec/types.h> 959 960 961 // <exec/nodes.h> 962 963 964 // <exec/lists.h> 965 966 967 // <exec/interrupts.h> 968 969 970 // <exec/library.h> 971 972 // cf. 973 // http://ftp.netbsd.org/pub/NetBSD/NetBSD-release-4-0/src/sys/arch/amiga/stand/bootblock/boot/amigatypes.h 974 975 struct Library { 976 uint8 dummy1[10]; 977 uint16 Version, Revision; 978 uint8 dummy2[34-24]; 979 }; 980 981 // <exec/execbase.h> 982 983 struct MemHead { 984 struct MemHead *next; 985 uint8 dummy1[9-4]; 986 uint8 Pri; 987 uint8 dummy2[14-10]; 988 uint16 Attribs; 989 uint32 First, Lower, Upper, Free; 990 }; 991 992 struct ExecBase { 993 struct Library LibNode; 994 uint8 dummy1[296-34]; 995 uint16 AttnFlags; 996 uint8 dummy2[300-298]; 997 void *ResModules; 998 uint8 dummy3[322-304]; 999 struct MemHead *MemList; 1000 uint8 dummy4[568-326]; 1001 uint32 EClockFreq; 1002 uint8 dummy5[632-334]; 1003 } _PACKED; 1004 1005 #endif /* __ASSEMBLER__ */ 1006 1007 1008 #define AFF_68010 (0x01) 1009 #define AFF_68020 (0x02) 1010 #define AFF_68030 (0x04) 1011 #define AFF_68040 (0x08) 1012 #define AFF_68881 (0x10) 1013 #define AFF_68882 (0x20) 1014 #define AFF_FPU40 (0x40) 1015 1016 1017 #ifndef __ASSEMBLER__ 1018 1019 // <exec/ports.h> 1020 1021 1022 1023 // <exec/io.h> 1024 1025 /* 1026 struct IORequest { 1027 struct Message io_Message; 1028 struct Device *io_Device; 1029 struct Unit *io_Unit; 1030 uint16 io_Command; 1031 uint8 io_Flags; 1032 int8 io_Error; 1033 }; 1034 1035 struct IOStdReq { 1036 struct Message io_Message; 1037 struct Device *io_Device; 1038 struct Unit *io_Unit; 1039 uint16 io_Command; 1040 uint8 io_Flags; 1041 int8 io_Error; 1042 uint32 io_Actual; 1043 uint32 io_Length; 1044 void *io_Data; 1045 uint32 io_Offset; 1046 }; 1047 */ 1048 1049 #endif /* __ASSEMBLER__ */ 1050 1051 // io_Flags 1052 #define IOB_QUICK 0 1053 #define IOF_QUICK 0x01 1054 1055 1056 #define CMD_INVALID 0 1057 #define CMD_RESET 1 1058 #define CMD_READ 2 1059 #define CMD_WRITE 3 1060 #define CMD_UPDATE 4 1061 #define CMD_CLEAR 5 1062 #define CMD_STOP 6 1063 #define CMD_START 7 1064 #define CMD_FLUSH 8 1065 #define CMD_NONSTD 9 1066 1067 1068 #ifndef __ASSEMBLER__ 1069 1070 // <exec/devices.h> 1071 1072 1073 #endif /* __ASSEMBLER__ */ 1074 1075 1076 // <exec/errors.h> 1077 1078 #define IOERR_OPENFAIL (-1) 1079 #define IOERR_ABORTED (-2) 1080 #define IOERR_NOCMD (-3) 1081 #define IOERR_BADLENGTH (-4) 1082 #define IOERR_BADADDRESS (-5) 1083 #define IOERR_UNITBUSY (-6) 1084 #define IOERR_SELFTEST (-7) 1085 1086 1087 #define EXEC_BASE_NAME SysBase 1088 1089 #define _LVOFindResident (-0x60) 1090 #define _LVOAllocAbs (-0xcc) 1091 #define _LVOOldOpenLibrary (-0x198) 1092 #define _LVOCloseLibrary (-0x19e) 1093 #define _LVODoIO (-0x1c8) 1094 #define _LVOOpenLibrary (-0x228) 1095 1096 1097 #ifndef __ASSEMBLER__ 1098 1099 extern ExecBase *EXEC_BASE_NAME; 1100 1101 #define AllocAbs(par1, last) \ 1102 LP2(0xcc, APTR, AllocAbs, unsigned long, par1, d0, APTR, last, a1, \ 1103 , EXEC_BASE_NAME) 1104 1105 #define CloseLibrary(last) \ 1106 LP1NR(0x19e, CloseLibrary, struct Library *, last, a1, \ 1107 , EXEC_BASE_NAME) 1108 1109 #define DoIO(last) \ 1110 LP1(0x1c8, BYTE, DoIO, struct IORequest *, last, a1, \ 1111 , EXEC_BASE_NAME) 1112 1113 #define OpenLibrary(par1, last) \ 1114 LP2(0x228, struct Library *, OpenLibrary, uint8 *, par1, a1, \ 1115 unsigned long, last, d0, \ 1116 , EXEC_BASE_NAME) 1117 1118 1119 1120 1121 extern "C" status_t exec_error(int32 err); 1122 1123 #endif /* __ASSEMBLER__ */ 1124 1125 1126 // #pragma mark - 1127 1128 1129 // <intuition/intuition.h> 1130 1131 1132 #define ALERT_TYPE 0x80000000 1133 #define RECOVERY_ALERT 0x00000000 1134 #define DEADEND_ALERT 0x80000000 1135 1136 #define INTUITION_BASE_NAME IntuitionBase 1137 1138 #define _LVODisplayAlert (-0x5a) 1139 1140 #ifndef __ASSEMBLER__ 1141 1142 extern Library *INTUITION_BASE_NAME; 1143 1144 #define DisplayAlert(par1, par2, last) \ 1145 LP3(0x5a, bool, DisplayAlert, unsigned long, par1, d0, void *, \ 1146 par2, a0, unsigned long, last, d1, \ 1147 , INTUITION_BASE_NAME) 1148 1149 #endif /* __ASSEMBLER__ */ 1150 1151 1152 #ifdef __cplusplus 1153 } 1154 #endif 1155 1156 #endif /* _AMICALLS_H */ 1157