1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <stdlib.h> 30 31 #ifndef __HAIKU__ 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_acpi.h" 35 #include "opt_sched.h" 36 #else 37 #include <sys/epoch.h> 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/types.h> 42 #include <sys/bus.h> 43 #include <sys/eventhandler.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/sx.h> 48 #include <sys/module.h> 49 #include <sys/kobj.h> 50 #include <sys/rman.h> 51 #include <sys/sbuf.h> 52 #include <sys/smp.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 #include <sys/syslog.h> 57 #include <sys/taskqueue.h> 58 #include <sys/limits.h> 59 60 #include <net/if.h> 61 #include <net/if_var.h> 62 #include <net/if_types.h> 63 #include <net/if_media.h> 64 #include <net/bpf.h> 65 #include <net/ethernet.h> 66 #include <net/if_vlan_var.h> 67 #include <net/mp_ring.h> 68 #include <net/debugnet.h> 69 #include <net/vnet.h> 70 71 #include <netinet/in.h> 72 #ifndef __HAIKU__ 73 #include <netinet/in_pcb.h> 74 #include <netinet/tcp_lro.h> 75 #include <netinet/in_systm.h> 76 #endif 77 #include <netinet/if_ether.h> 78 #include <netinet/ip.h> 79 #include <netinet/ip6.h> 80 #include <netinet/tcp.h> 81 #include <netinet/ip_var.h> 82 #ifndef __HAIKU__ 83 #include <netinet6/ip6_var.h> 84 #endif 85 86 #include <machine/bus.h> 87 #ifndef __HAIKU__ 88 #include <machine/in_cksum.h> 89 #endif 90 91 #include <vm/vm.h> 92 #include <vm/pmap.h> 93 94 #include <dev/led/led.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #ifndef __HAIKU__ 98 #include <dev/pci/pci_private.h> 99 #endif 100 101 #include <net/iflib.h> 102 103 #include <ifdi_if.h> 104 #include <device_if.h> 105 106 #ifdef PCI_IOV 107 #include <dev/pci/pci_iov.h> 108 #endif 109 110 #include <sys/bitstring.h> 111 /* 112 * enable accounting of every mbuf as it comes in to and goes out of 113 * iflib's software descriptor references 114 */ 115 #define MEMORY_LOGGING 0 116 /* 117 * Enable mbuf vectors for compressing long mbuf chains 118 */ 119 120 /* 121 * NB: 122 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 123 * we prefetch needs to be determined by the time spent in m_free vis a vis 124 * the cost of a prefetch. This will of course vary based on the workload: 125 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 126 * is quite expensive, thus suggesting very little prefetch. 127 * - small packet forwarding which is just returning a single mbuf to 128 * UMA will typically be very fast vis a vis the cost of a memory 129 * access. 130 */ 131 132 /* 133 * File organization: 134 * - private structures 135 * - iflib private utility functions 136 * - ifnet functions 137 * - vlan registry and other exported functions 138 * - iflib public core functions 139 * 140 * 141 */ 142 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 143 144 #define IFLIB_RXEOF_MORE (1U << 0) 145 #define IFLIB_RXEOF_EMPTY (2U << 0) 146 147 struct iflib_txq; 148 typedef struct iflib_txq *iflib_txq_t; 149 struct iflib_rxq; 150 typedef struct iflib_rxq *iflib_rxq_t; 151 struct iflib_fl; 152 typedef struct iflib_fl *iflib_fl_t; 153 154 struct iflib_ctx; 155 156 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 157 static void iflib_timer(void *arg); 158 static void iflib_tqg_detach(if_ctx_t ctx); 159 160 typedef struct iflib_filter_info { 161 driver_filter_t *ifi_filter; 162 void *ifi_filter_arg; 163 struct grouptask *ifi_task; 164 void *ifi_ctx; 165 } *iflib_filter_info_t; 166 167 struct iflib_ctx { 168 KOBJ_FIELDS; 169 /* 170 * Pointer to hardware driver's softc 171 */ 172 void *ifc_softc; 173 device_t ifc_dev; 174 if_t ifc_ifp; 175 176 #ifndef __HAIKU__ 177 cpuset_t ifc_cpus; 178 #endif 179 if_shared_ctx_t ifc_sctx; 180 struct if_softc_ctx ifc_softc_ctx; 181 182 struct sx ifc_ctx_sx; 183 struct mtx ifc_state_mtx; 184 185 iflib_txq_t ifc_txqs; 186 iflib_rxq_t ifc_rxqs; 187 uint32_t ifc_if_flags; 188 uint32_t ifc_flags; 189 uint32_t ifc_max_fl_buf_size; 190 uint32_t ifc_rx_mbuf_sz; 191 192 int ifc_link_state; 193 int ifc_watchdog_events; 194 struct cdev *ifc_led_dev; 195 struct resource *ifc_msix_mem; 196 197 struct if_irq ifc_legacy_irq; 198 struct grouptask ifc_admin_task; 199 struct grouptask ifc_vflr_task; 200 struct iflib_filter_info ifc_filter_info; 201 struct ifmedia ifc_media; 202 struct ifmedia *ifc_mediap; 203 204 struct sysctl_oid *ifc_sysctl_node; 205 uint16_t ifc_sysctl_ntxqs; 206 uint16_t ifc_sysctl_nrxqs; 207 uint16_t ifc_sysctl_qs_eq_override; 208 uint16_t ifc_sysctl_rx_budget; 209 uint16_t ifc_sysctl_tx_abdicate; 210 uint16_t ifc_sysctl_core_offset; 211 #define CORE_OFFSET_UNSPECIFIED 0xffff 212 uint8_t ifc_sysctl_separate_txrx; 213 uint8_t ifc_sysctl_use_logical_cores; 214 uint16_t ifc_sysctl_extra_msix_vectors; 215 bool ifc_cpus_are_physical_cores; 216 217 qidx_t ifc_sysctl_ntxds[8]; 218 qidx_t ifc_sysctl_nrxds[8]; 219 struct if_txrx ifc_txrx; 220 #define isc_txd_encap ifc_txrx.ift_txd_encap 221 #define isc_txd_flush ifc_txrx.ift_txd_flush 222 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 223 #define isc_rxd_available ifc_txrx.ift_rxd_available 224 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 225 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 226 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 227 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 228 #define isc_txq_select ifc_txrx.ift_txq_select 229 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 230 231 eventhandler_tag ifc_vlan_attach_event; 232 eventhandler_tag ifc_vlan_detach_event; 233 struct ether_addr ifc_mac; 234 }; 235 236 void * 237 iflib_get_softc(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_softc); 241 } 242 243 device_t 244 iflib_get_dev(if_ctx_t ctx) 245 { 246 247 return (ctx->ifc_dev); 248 } 249 250 if_t 251 iflib_get_ifp(if_ctx_t ctx) 252 { 253 254 return (ctx->ifc_ifp); 255 } 256 257 struct ifmedia * 258 iflib_get_media(if_ctx_t ctx) 259 { 260 261 return (ctx->ifc_mediap); 262 } 263 264 void 265 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 266 { 267 268 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 269 } 270 271 if_softc_ctx_t 272 iflib_get_softc_ctx(if_ctx_t ctx) 273 { 274 275 return (&ctx->ifc_softc_ctx); 276 } 277 278 if_shared_ctx_t 279 iflib_get_sctx(if_ctx_t ctx) 280 { 281 282 return (ctx->ifc_sctx); 283 } 284 285 uint16_t 286 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 287 { 288 289 return (ctx->ifc_sysctl_extra_msix_vectors); 290 } 291 292 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 293 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 294 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 295 296 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 297 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 298 299 typedef struct iflib_sw_rx_desc_array { 300 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 301 struct mbuf **ifsd_m; /* pkthdr mbufs */ 302 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 303 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 304 } iflib_rxsd_array_t; 305 306 typedef struct iflib_sw_tx_desc_array { 307 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 308 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 309 struct mbuf **ifsd_m; /* pkthdr mbufs */ 310 } if_txsd_vec_t; 311 312 /* magic number that should be high enough for any hardware */ 313 #define IFLIB_MAX_TX_SEGS 128 314 #define IFLIB_RX_COPY_THRESH 128 315 #define IFLIB_MAX_RX_REFRESH 32 316 /* The minimum descriptors per second before we start coalescing */ 317 #define IFLIB_MIN_DESC_SEC 16384 318 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 319 #define IFLIB_QUEUE_IDLE 0 320 #define IFLIB_QUEUE_HUNG 1 321 #define IFLIB_QUEUE_WORKING 2 322 /* maximum number of txqs that can share an rx interrupt */ 323 #define IFLIB_MAX_TX_SHARED_INTR 4 324 325 /* this should really scale with ring size - this is a fairly arbitrary value */ 326 #define TX_BATCH_SIZE 32 327 328 #define IFLIB_RESTART_BUDGET 8 329 330 #define IFC_LEGACY 0x001 331 #define IFC_QFLUSH 0x002 332 #define IFC_MULTISEG 0x004 333 #define IFC_SPARE1 0x008 334 #define IFC_SC_ALLOCATED 0x010 335 #define IFC_INIT_DONE 0x020 336 #define IFC_PREFETCH 0x040 337 #define IFC_DO_RESET 0x080 338 #define IFC_DO_WATCHDOG 0x100 339 #define IFC_SPARE0 0x200 340 #define IFC_SPARE2 0x400 341 #define IFC_IN_DETACH 0x800 342 343 #define IFC_NETMAP_TX_IRQ 0x80000000 344 345 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 346 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 347 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 348 349 struct iflib_txq { 350 qidx_t ift_in_use; 351 qidx_t ift_cidx; 352 qidx_t ift_cidx_processed; 353 qidx_t ift_pidx; 354 uint8_t ift_gen; 355 uint8_t ift_br_offset; 356 uint16_t ift_npending; 357 uint16_t ift_db_pending; 358 uint16_t ift_rs_pending; 359 /* implicit pad */ 360 uint8_t ift_txd_size[8]; 361 uint64_t ift_processed; 362 uint64_t ift_cleaned; 363 uint64_t ift_cleaned_prev; 364 #if MEMORY_LOGGING 365 uint64_t ift_enqueued; 366 uint64_t ift_dequeued; 367 #endif 368 uint64_t ift_no_tx_dma_setup; 369 uint64_t ift_no_desc_avail; 370 uint64_t ift_mbuf_defrag_failed; 371 uint64_t ift_mbuf_defrag; 372 uint64_t ift_map_failed; 373 uint64_t ift_txd_encap_efbig; 374 uint64_t ift_pullups; 375 uint64_t ift_last_timer_tick; 376 377 struct mtx ift_mtx; 378 struct mtx ift_db_mtx; 379 380 /* constant values */ 381 if_ctx_t ift_ctx; 382 struct ifmp_ring *ift_br; 383 struct grouptask ift_task; 384 qidx_t ift_size; 385 uint16_t ift_id; 386 struct callout ift_timer; 387 #ifdef DEV_NETMAP 388 struct callout ift_netmap_timer; 389 #endif /* DEV_NETMAP */ 390 391 if_txsd_vec_t ift_sds; 392 uint8_t ift_qstatus; 393 uint8_t ift_closed; 394 uint8_t ift_update_freq; 395 struct iflib_filter_info ift_filter_info; 396 bus_dma_tag_t ift_buf_tag; 397 bus_dma_tag_t ift_tso_buf_tag; 398 iflib_dma_info_t ift_ifdi; 399 #define MTX_NAME_LEN 32 400 char ift_mtx_name[MTX_NAME_LEN]; 401 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 402 #ifdef IFLIB_DIAGNOSTICS 403 uint64_t ift_cpu_exec_count[256]; 404 #endif 405 } __aligned(CACHE_LINE_SIZE); 406 407 struct iflib_fl { 408 qidx_t ifl_cidx; 409 qidx_t ifl_pidx; 410 qidx_t ifl_credits; 411 uint8_t ifl_gen; 412 uint8_t ifl_rxd_size; 413 #if MEMORY_LOGGING 414 uint64_t ifl_m_enqueued; 415 uint64_t ifl_m_dequeued; 416 uint64_t ifl_cl_enqueued; 417 uint64_t ifl_cl_dequeued; 418 #endif 419 /* implicit pad */ 420 bitstr_t *ifl_rx_bitmap; 421 qidx_t ifl_fragidx; 422 /* constant */ 423 qidx_t ifl_size; 424 uint16_t ifl_buf_size; 425 uint16_t ifl_cltype; 426 #ifndef __HAIKU__ 427 uma_zone_t ifl_zone; 428 #endif 429 iflib_rxsd_array_t ifl_sds; 430 iflib_rxq_t ifl_rxq; 431 uint8_t ifl_id; 432 bus_dma_tag_t ifl_buf_tag; 433 iflib_dma_info_t ifl_ifdi; 434 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 435 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 436 } __aligned(CACHE_LINE_SIZE); 437 438 static inline qidx_t 439 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 440 { 441 qidx_t used; 442 443 if (pidx > cidx) 444 used = pidx - cidx; 445 else if (pidx < cidx) 446 used = size - cidx + pidx; 447 else if (gen == 0 && pidx == cidx) 448 used = 0; 449 else if (gen == 1 && pidx == cidx) 450 used = size; 451 else 452 panic("bad state"); 453 454 return (used); 455 } 456 457 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 458 459 #define IDXDIFF(head, tail, wrap) \ 460 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 461 462 struct iflib_rxq { 463 if_ctx_t ifr_ctx; 464 iflib_fl_t ifr_fl; 465 uint64_t ifr_rx_irq; 466 #ifndef __HAIKU__ 467 struct pfil_head *pfil; 468 #else 469 #define PFIL_PASS 0 470 #endif 471 /* 472 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 473 * the completion queue consumer index. Otherwise it's unused. 474 */ 475 qidx_t ifr_cq_cidx; 476 uint16_t ifr_id; 477 uint8_t ifr_nfl; 478 uint8_t ifr_ntxqirq; 479 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 480 uint8_t ifr_fl_offset; 481 #ifndef __HAIKU__ 482 struct lro_ctrl ifr_lc; 483 #endif 484 struct grouptask ifr_task; 485 struct callout ifr_watchdog; 486 struct iflib_filter_info ifr_filter_info; 487 iflib_dma_info_t ifr_ifdi; 488 489 /* dynamically allocate if any drivers need a value substantially larger than this */ 490 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 491 #ifdef IFLIB_DIAGNOSTICS 492 uint64_t ifr_cpu_exec_count[256]; 493 #endif 494 } __aligned(CACHE_LINE_SIZE); 495 496 typedef struct if_rxsd { 497 caddr_t *ifsd_cl; 498 iflib_fl_t ifsd_fl; 499 } *if_rxsd_t; 500 501 /* multiple of word size */ 502 #ifdef __LP64__ 503 #define PKT_INFO_SIZE 6 504 #define RXD_INFO_SIZE 5 505 #define PKT_TYPE uint64_t 506 #else 507 #define PKT_INFO_SIZE 11 508 #define RXD_INFO_SIZE 8 509 #define PKT_TYPE uint32_t 510 #endif 511 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 512 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 513 514 typedef struct if_pkt_info_pad { 515 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 516 } *if_pkt_info_pad_t; 517 typedef struct if_rxd_info_pad { 518 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 519 } *if_rxd_info_pad_t; 520 521 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 522 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 523 524 static inline void 525 pkt_info_zero(if_pkt_info_t pi) 526 { 527 if_pkt_info_pad_t pi_pad; 528 529 pi_pad = (if_pkt_info_pad_t)pi; 530 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 531 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 532 #ifndef __LP64__ 533 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 534 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 535 #endif 536 } 537 538 static inline void 539 rxd_info_zero(if_rxd_info_t ri) 540 { 541 if_rxd_info_pad_t ri_pad; 542 int i; 543 544 ri_pad = (if_rxd_info_pad_t)ri; 545 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 546 ri_pad->rxd_val[i] = 0; 547 ri_pad->rxd_val[i+1] = 0; 548 ri_pad->rxd_val[i+2] = 0; 549 ri_pad->rxd_val[i+3] = 0; 550 } 551 #ifdef __LP64__ 552 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 553 #endif 554 } 555 556 /* 557 * Only allow a single packet to take up most 1/nth of the tx ring 558 */ 559 #define MAX_SINGLE_PACKET_FRACTION 12 560 #define IF_BAD_DMA (bus_addr_t)-1 561 562 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 563 564 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 565 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 566 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 567 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 568 569 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 570 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 571 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 572 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 573 574 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 575 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 576 577 /* Our boot-time initialization hook */ 578 static int iflib_module_event_handler(module_t, int, void *); 579 580 #ifndef __HAIKU__ 581 static moduledata_t iflib_moduledata = { 582 "iflib", 583 iflib_module_event_handler, 584 NULL 585 }; 586 #endif 587 588 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 589 MODULE_VERSION(iflib, 1); 590 591 MODULE_DEPEND(iflib, pci, 1, 1, 1); 592 MODULE_DEPEND(iflib, ether, 1, 1, 1); 593 594 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 595 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 596 597 #ifndef IFLIB_DEBUG_COUNTERS 598 #ifdef INVARIANTS 599 #define IFLIB_DEBUG_COUNTERS 1 600 #else 601 #define IFLIB_DEBUG_COUNTERS 0 602 #endif /* !INVARIANTS */ 603 #endif 604 605 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 606 "iflib driver parameters"); 607 608 /* 609 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 610 */ 611 static int iflib_min_tx_latency = 0; 612 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 613 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 614 static int iflib_no_tx_batch = 0; 615 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 616 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 617 static int iflib_timer_default = 1000; 618 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 619 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 620 621 622 #if IFLIB_DEBUG_COUNTERS 623 624 static int iflib_tx_seen; 625 static int iflib_tx_sent; 626 static int iflib_tx_encap; 627 static int iflib_rx_allocs; 628 static int iflib_fl_refills; 629 static int iflib_fl_refills_large; 630 static int iflib_tx_frees; 631 632 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 633 &iflib_tx_seen, 0, "# TX mbufs seen"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 635 &iflib_tx_sent, 0, "# TX mbufs sent"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 637 &iflib_tx_encap, 0, "# TX mbufs encapped"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 639 &iflib_tx_frees, 0, "# TX frees"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 641 &iflib_rx_allocs, 0, "# RX allocations"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 643 &iflib_fl_refills, 0, "# refills"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 645 &iflib_fl_refills_large, 0, "# large refills"); 646 647 static int iflib_txq_drain_flushing; 648 static int iflib_txq_drain_oactive; 649 static int iflib_txq_drain_notready; 650 651 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 652 &iflib_txq_drain_flushing, 0, "# drain flushes"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 654 &iflib_txq_drain_oactive, 0, "# drain oactives"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 656 &iflib_txq_drain_notready, 0, "# drain notready"); 657 658 static int iflib_encap_load_mbuf_fail; 659 static int iflib_encap_pad_mbuf_fail; 660 static int iflib_encap_txq_avail_fail; 661 static int iflib_encap_txd_encap_fail; 662 663 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 664 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 666 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 668 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 670 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 671 672 static int iflib_task_fn_rxs; 673 static int iflib_rx_intr_enables; 674 static int iflib_fast_intrs; 675 static int iflib_rx_unavail; 676 static int iflib_rx_ctx_inactive; 677 static int iflib_rx_if_input; 678 static int iflib_rxd_flush; 679 680 static int iflib_verbose_debug; 681 682 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 683 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 685 &iflib_rx_intr_enables, 0, "# RX intr enables"); 686 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 687 &iflib_fast_intrs, 0, "# fast_intr calls"); 688 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 689 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 691 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 692 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 693 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 694 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 695 &iflib_rxd_flush, 0, "# times rxd_flush called"); 696 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 697 &iflib_verbose_debug, 0, "enable verbose debugging"); 698 699 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 700 static void 701 iflib_debug_reset(void) 702 { 703 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 704 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 705 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 706 iflib_txq_drain_notready = 707 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 708 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 709 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 710 iflib_rx_unavail = 711 iflib_rx_ctx_inactive = iflib_rx_if_input = 712 iflib_rxd_flush = 0; 713 } 714 715 #else 716 #define DBG_COUNTER_INC(name) 717 static void iflib_debug_reset(void) {} 718 #endif 719 720 #define IFLIB_DEBUG 0 721 722 static void iflib_tx_structures_free(if_ctx_t ctx); 723 static void iflib_rx_structures_free(if_ctx_t ctx); 724 static int iflib_queues_alloc(if_ctx_t ctx); 725 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 726 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 727 static int iflib_qset_structures_setup(if_ctx_t ctx); 728 static int iflib_msix_init(if_ctx_t ctx); 729 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 730 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 731 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 732 #ifdef ALTQ 733 static void iflib_altq_if_start(if_t ifp); 734 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 735 #endif 736 static int iflib_register(if_ctx_t); 737 static void iflib_deregister(if_ctx_t); 738 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 739 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 740 static void iflib_init_locked(if_ctx_t ctx); 741 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 742 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 743 static void iflib_ifmp_purge(iflib_txq_t txq); 744 static void _iflib_pre_assert(if_softc_ctx_t scctx); 745 static void iflib_stop(if_ctx_t ctx); 746 static void iflib_if_init_locked(if_ctx_t ctx); 747 static void iflib_free_intr_mem(if_ctx_t ctx); 748 #ifndef __NO_STRICT_ALIGNMENT 749 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 750 #endif 751 752 #ifndef __HAIKU__ 753 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 754 SLIST_HEAD_INITIALIZER(cpu_offsets); 755 struct cpu_offset { 756 SLIST_ENTRY(cpu_offset) entries; 757 cpuset_t set; 758 unsigned int refcount; 759 uint16_t next_cpuid; 760 }; 761 static struct mtx cpu_offset_mtx; 762 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 763 MTX_DEF); 764 #endif 765 766 DEBUGNET_DEFINE(iflib); 767 768 static int 769 iflib_num_rx_descs(if_ctx_t ctx) 770 { 771 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 772 if_shared_ctx_t sctx = ctx->ifc_sctx; 773 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 774 775 return scctx->isc_nrxd[first_rxq]; 776 } 777 778 static int 779 iflib_num_tx_descs(if_ctx_t ctx) 780 { 781 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 782 if_shared_ctx_t sctx = ctx->ifc_sctx; 783 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 784 785 return scctx->isc_ntxd[first_txq]; 786 } 787 788 #ifdef DEV_NETMAP 789 #include <sys/selinfo.h> 790 #include <net/netmap.h> 791 #include <dev/netmap/netmap_kern.h> 792 793 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 794 795 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 796 static void iflib_netmap_timer(void *arg); 797 798 /* 799 * device-specific sysctl variables: 800 * 801 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 802 * During regular operations the CRC is stripped, but on some 803 * hardware reception of frames not multiple of 64 is slower, 804 * so using crcstrip=0 helps in benchmarks. 805 * 806 * iflib_rx_miss, iflib_rx_miss_bufs: 807 * count packets that might be missed due to lost interrupts. 808 */ 809 SYSCTL_DECL(_dev_netmap); 810 /* 811 * The xl driver by default strips CRCs and we do not override it. 812 */ 813 814 int iflib_crcstrip = 1; 815 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 816 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 817 818 int iflib_rx_miss, iflib_rx_miss_bufs; 819 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 820 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 821 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 822 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 823 824 /* 825 * Register/unregister. We are already under netmap lock. 826 * Only called on the first register or the last unregister. 827 */ 828 static int 829 iflib_netmap_register(struct netmap_adapter *na, int onoff) 830 { 831 if_t ifp = na->ifp; 832 if_ctx_t ctx = if_getsoftc(ifp); 833 int status; 834 835 CTX_LOCK(ctx); 836 if (!CTX_IS_VF(ctx)) 837 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 838 839 iflib_stop(ctx); 840 841 /* 842 * Enable (or disable) netmap flags, and intercept (or restore) 843 * ifp->if_transmit. This is done once the device has been stopped 844 * to prevent race conditions. Also, this must be done after 845 * calling netmap_disable_all_rings() and before calling 846 * netmap_enable_all_rings(), so that these two functions see the 847 * updated state of the NAF_NETMAP_ON bit. 848 */ 849 if (onoff) { 850 nm_set_native_flags(na); 851 } else { 852 nm_clear_native_flags(na); 853 } 854 855 iflib_init_locked(ctx); 856 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 857 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 858 if (status) 859 nm_clear_native_flags(na); 860 CTX_UNLOCK(ctx); 861 return (status); 862 } 863 864 static int 865 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 866 { 867 if_t ifp = na->ifp; 868 if_ctx_t ctx = if_getsoftc(ifp); 869 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 870 iflib_fl_t fl = &rxq->ifr_fl[0]; 871 872 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 873 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 874 info->num_tx_descs = iflib_num_tx_descs(ctx); 875 info->num_rx_descs = iflib_num_rx_descs(ctx); 876 info->rx_buf_maxsize = fl->ifl_buf_size; 877 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 878 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 879 info->num_rx_descs, info->rx_buf_maxsize); 880 881 return 0; 882 } 883 884 static int 885 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 886 { 887 struct netmap_adapter *na = kring->na; 888 u_int const lim = kring->nkr_num_slots - 1; 889 struct netmap_ring *ring = kring->ring; 890 bus_dmamap_t *map; 891 struct if_rxd_update iru; 892 if_ctx_t ctx = rxq->ifr_ctx; 893 iflib_fl_t fl = &rxq->ifr_fl[0]; 894 u_int nic_i_first, nic_i; 895 u_int nm_i; 896 int i, n; 897 #if IFLIB_DEBUG_COUNTERS 898 int rf_count = 0; 899 #endif 900 901 /* 902 * This function is used both at initialization and in rxsync. 903 * At initialization we need to prepare (with isc_rxd_refill()) 904 * all the netmap buffers currently owned by the kernel, in 905 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 906 * (except for kring->nkr_hwofs). These may be less than 907 * kring->nkr_num_slots if netmap_reset() was called while 908 * an application using the kring that still owned some 909 * buffers. 910 * At rxsync time, both indexes point to the next buffer to be 911 * refilled. 912 * In any case we publish (with isc_rxd_flush()) up to 913 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 914 * pointer to overrun the head/cons pointer, although this is 915 * not necessary for some NICs (e.g. vmx). 916 */ 917 if (__predict_false(init)) { 918 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 919 } else { 920 n = kring->rhead - kring->nr_hwcur; 921 if (n == 0) 922 return (0); /* Nothing to do. */ 923 if (n < 0) 924 n += kring->nkr_num_slots; 925 } 926 927 iru_init(&iru, rxq, 0 /* flid */); 928 map = fl->ifl_sds.ifsd_map; 929 nic_i = fl->ifl_pidx; 930 nm_i = netmap_idx_n2k(kring, nic_i); 931 if (__predict_false(init)) { 932 /* 933 * On init/reset, nic_i must be 0, and we must 934 * start to refill from hwtail (see netmap_reset()). 935 */ 936 MPASS(nic_i == 0); 937 MPASS(nm_i == kring->nr_hwtail); 938 } else 939 MPASS(nm_i == kring->nr_hwcur); 940 DBG_COUNTER_INC(fl_refills); 941 while (n > 0) { 942 #if IFLIB_DEBUG_COUNTERS 943 if (++rf_count == 9) 944 DBG_COUNTER_INC(fl_refills_large); 945 #endif 946 nic_i_first = nic_i; 947 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 948 struct netmap_slot *slot = &ring->slot[nm_i]; 949 uint64_t paddr; 950 void *addr = PNMB(na, slot, &paddr); 951 952 MPASS(i < IFLIB_MAX_RX_REFRESH); 953 954 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 955 return netmap_ring_reinit(kring); 956 957 fl->ifl_bus_addrs[i] = paddr + 958 nm_get_offset(kring, slot); 959 fl->ifl_rxd_idxs[i] = nic_i; 960 961 if (__predict_false(init)) { 962 netmap_load_map(na, fl->ifl_buf_tag, 963 map[nic_i], addr); 964 } else if (slot->flags & NS_BUF_CHANGED) { 965 /* buffer has changed, reload map */ 966 netmap_reload_map(na, fl->ifl_buf_tag, 967 map[nic_i], addr); 968 } 969 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 970 BUS_DMASYNC_PREREAD); 971 slot->flags &= ~NS_BUF_CHANGED; 972 973 nm_i = nm_next(nm_i, lim); 974 nic_i = nm_next(nic_i, lim); 975 } 976 977 iru.iru_pidx = nic_i_first; 978 iru.iru_count = i; 979 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 980 } 981 fl->ifl_pidx = nic_i; 982 /* 983 * At the end of the loop we must have refilled everything 984 * we could possibly refill. 985 */ 986 MPASS(nm_i == kring->rhead); 987 kring->nr_hwcur = nm_i; 988 989 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 991 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 992 nm_prev(nic_i, lim)); 993 DBG_COUNTER_INC(rxd_flush); 994 995 return (0); 996 } 997 998 #define NETMAP_TX_TIMER_US 90 999 1000 /* 1001 * Reconcile kernel and user view of the transmit ring. 1002 * 1003 * All information is in the kring. 1004 * Userspace wants to send packets up to the one before kring->rhead, 1005 * kernel knows kring->nr_hwcur is the first unsent packet. 1006 * 1007 * Here we push packets out (as many as possible), and possibly 1008 * reclaim buffers from previously completed transmission. 1009 * 1010 * The caller (netmap) guarantees that there is only one instance 1011 * running at any time. Any interference with other driver 1012 * methods should be handled by the individual drivers. 1013 */ 1014 static int 1015 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 1016 { 1017 struct netmap_adapter *na = kring->na; 1018 if_t ifp = na->ifp; 1019 struct netmap_ring *ring = kring->ring; 1020 u_int nm_i; /* index into the netmap kring */ 1021 u_int nic_i; /* index into the NIC ring */ 1022 u_int const lim = kring->nkr_num_slots - 1; 1023 u_int const head = kring->rhead; 1024 struct if_pkt_info pi; 1025 int tx_pkts = 0, tx_bytes = 0; 1026 1027 /* 1028 * interrupts on every tx packet are expensive so request 1029 * them every half ring, or where NS_REPORT is set 1030 */ 1031 u_int report_frequency = kring->nkr_num_slots >> 1; 1032 /* device-specific */ 1033 if_ctx_t ctx = if_getsoftc(ifp); 1034 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1035 1036 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1038 1039 /* 1040 * First part: process new packets to send. 1041 * nm_i is the current index in the netmap kring, 1042 * nic_i is the corresponding index in the NIC ring. 1043 * 1044 * If we have packets to send (nm_i != head) 1045 * iterate over the netmap ring, fetch length and update 1046 * the corresponding slot in the NIC ring. Some drivers also 1047 * need to update the buffer's physical address in the NIC slot 1048 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1049 * 1050 * The netmap_reload_map() calls is especially expensive, 1051 * even when (as in this case) the tag is 0, so do only 1052 * when the buffer has actually changed. 1053 * 1054 * If possible do not set the report/intr bit on all slots, 1055 * but only a few times per ring or when NS_REPORT is set. 1056 * 1057 * Finally, on 10G and faster drivers, it might be useful 1058 * to prefetch the next slot and txr entry. 1059 */ 1060 1061 nm_i = kring->nr_hwcur; 1062 if (nm_i != head) { /* we have new packets to send */ 1063 uint32_t pkt_len = 0, seg_idx = 0; 1064 int nic_i_start = -1, flags = 0; 1065 pkt_info_zero(&pi); 1066 pi.ipi_segs = txq->ift_segs; 1067 pi.ipi_qsidx = kring->ring_id; 1068 nic_i = netmap_idx_k2n(kring, nm_i); 1069 1070 __builtin_prefetch(&ring->slot[nm_i]); 1071 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1072 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1073 1074 while (nm_i != head) { 1075 struct netmap_slot *slot = &ring->slot[nm_i]; 1076 uint64_t offset = nm_get_offset(kring, slot); 1077 u_int len = slot->len; 1078 uint64_t paddr; 1079 void *addr = PNMB(na, slot, &paddr); 1080 1081 flags |= (slot->flags & NS_REPORT || 1082 nic_i == 0 || nic_i == report_frequency) ? 1083 IPI_TX_INTR : 0; 1084 1085 /* 1086 * If this is the first packet fragment, save the 1087 * index of the first NIC slot for later. 1088 */ 1089 if (nic_i_start < 0) 1090 nic_i_start = nic_i; 1091 1092 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1093 pi.ipi_segs[seg_idx].ds_len = len; 1094 if (len) { 1095 pkt_len += len; 1096 seg_idx++; 1097 } 1098 1099 if (!(slot->flags & NS_MOREFRAG)) { 1100 pi.ipi_len = pkt_len; 1101 pi.ipi_nsegs = seg_idx; 1102 pi.ipi_pidx = nic_i_start; 1103 pi.ipi_ndescs = 0; 1104 pi.ipi_flags = flags; 1105 1106 /* Prepare the NIC TX ring. */ 1107 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1108 DBG_COUNTER_INC(tx_encap); 1109 1110 /* Update transmit counters */ 1111 tx_bytes += pi.ipi_len; 1112 tx_pkts++; 1113 1114 /* Reinit per-packet info for the next one. */ 1115 flags = seg_idx = pkt_len = 0; 1116 nic_i_start = -1; 1117 } 1118 1119 /* prefetch for next round */ 1120 __builtin_prefetch(&ring->slot[nm_i + 1]); 1121 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1122 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1123 1124 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1125 1126 if (slot->flags & NS_BUF_CHANGED) { 1127 /* buffer has changed, reload map */ 1128 netmap_reload_map(na, txq->ift_buf_tag, 1129 txq->ift_sds.ifsd_map[nic_i], addr); 1130 } 1131 /* make sure changes to the buffer are synced */ 1132 bus_dmamap_sync(txq->ift_buf_tag, 1133 txq->ift_sds.ifsd_map[nic_i], 1134 BUS_DMASYNC_PREWRITE); 1135 1136 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1137 nm_i = nm_next(nm_i, lim); 1138 nic_i = nm_next(nic_i, lim); 1139 } 1140 kring->nr_hwcur = nm_i; 1141 1142 /* synchronize the NIC ring */ 1143 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1144 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1145 1146 /* (re)start the tx unit up to slot nic_i (excluded) */ 1147 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1148 } 1149 1150 /* 1151 * Second part: reclaim buffers for completed transmissions. 1152 * 1153 * If there are unclaimed buffers, attempt to reclaim them. 1154 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1155 * trigger a per-tx-queue timer to try again later. 1156 */ 1157 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1158 if (iflib_tx_credits_update(ctx, txq)) { 1159 /* some tx completed, increment avail */ 1160 nic_i = txq->ift_cidx_processed; 1161 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1162 } 1163 } 1164 1165 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1166 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1167 callout_reset_sbt_on(&txq->ift_netmap_timer, 1168 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1169 iflib_netmap_timer, txq, 1170 txq->ift_netmap_timer.c_cpu, 0); 1171 } 1172 1173 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1174 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1175 1176 return (0); 1177 } 1178 1179 /* 1180 * Reconcile kernel and user view of the receive ring. 1181 * Same as for the txsync, this routine must be efficient. 1182 * The caller guarantees a single invocations, but races against 1183 * the rest of the driver should be handled here. 1184 * 1185 * On call, kring->rhead is the first packet that userspace wants 1186 * to keep, and kring->rcur is the wakeup point. 1187 * The kernel has previously reported packets up to kring->rtail. 1188 * 1189 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1190 * of whether or not we received an interrupt. 1191 */ 1192 static int 1193 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1194 { 1195 struct netmap_adapter *na = kring->na; 1196 struct netmap_ring *ring = kring->ring; 1197 if_t ifp = na->ifp; 1198 uint32_t nm_i; /* index into the netmap ring */ 1199 uint32_t nic_i; /* index into the NIC ring */ 1200 u_int n; 1201 u_int const lim = kring->nkr_num_slots - 1; 1202 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1203 int i = 0, rx_bytes = 0, rx_pkts = 0; 1204 1205 if_ctx_t ctx = if_getsoftc(ifp); 1206 if_shared_ctx_t sctx = ctx->ifc_sctx; 1207 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1208 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1209 iflib_fl_t fl = &rxq->ifr_fl[0]; 1210 struct if_rxd_info ri; 1211 qidx_t *cidxp; 1212 1213 /* 1214 * netmap only uses free list 0, to avoid out of order consumption 1215 * of receive buffers 1216 */ 1217 1218 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1219 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1220 1221 /* 1222 * First part: import newly received packets. 1223 * 1224 * nm_i is the index of the next free slot in the netmap ring, 1225 * nic_i is the index of the next received packet in the NIC ring 1226 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1227 * differ in case if_init() has been called while 1228 * in netmap mode. For the receive ring we have 1229 * 1230 * nic_i = fl->ifl_cidx; 1231 * nm_i = kring->nr_hwtail (previous) 1232 * and 1233 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1234 * 1235 * fl->ifl_cidx is set to 0 on a ring reinit 1236 */ 1237 if (netmap_no_pendintr || force_update) { 1238 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1239 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1240 int crclen = iflib_crcstrip ? 0 : 4; 1241 int error, avail; 1242 1243 /* 1244 * For the free list consumer index, we use the same 1245 * logic as in iflib_rxeof(). 1246 */ 1247 if (have_rxcq) 1248 cidxp = &rxq->ifr_cq_cidx; 1249 else 1250 cidxp = &fl->ifl_cidx; 1251 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1252 rxq->ifr_id, *cidxp, USHRT_MAX); 1253 1254 nic_i = fl->ifl_cidx; 1255 nm_i = netmap_idx_n2k(kring, nic_i); 1256 MPASS(nm_i == kring->nr_hwtail); 1257 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1258 rxd_info_zero(&ri); 1259 ri.iri_frags = rxq->ifr_frags; 1260 ri.iri_qsidx = kring->ring_id; 1261 ri.iri_ifp = ctx->ifc_ifp; 1262 ri.iri_cidx = *cidxp; 1263 1264 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1265 for (i = 0; i < ri.iri_nfrags; i++) { 1266 if (error) { 1267 ring->slot[nm_i].len = 0; 1268 ring->slot[nm_i].flags = 0; 1269 } else { 1270 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1271 if (i == (ri.iri_nfrags - 1)) { 1272 ring->slot[nm_i].len -= crclen; 1273 ring->slot[nm_i].flags = 0; 1274 1275 /* Update receive counters */ 1276 rx_bytes += ri.iri_len; 1277 rx_pkts++; 1278 } else 1279 ring->slot[nm_i].flags = NS_MOREFRAG; 1280 } 1281 1282 bus_dmamap_sync(fl->ifl_buf_tag, 1283 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1284 nm_i = nm_next(nm_i, lim); 1285 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1286 } 1287 1288 if (have_rxcq) { 1289 *cidxp = ri.iri_cidx; 1290 while (*cidxp >= scctx->isc_nrxd[0]) 1291 *cidxp -= scctx->isc_nrxd[0]; 1292 } 1293 1294 } 1295 if (n) { /* update the state variables */ 1296 if (netmap_no_pendintr && !force_update) { 1297 /* diagnostics */ 1298 iflib_rx_miss ++; 1299 iflib_rx_miss_bufs += n; 1300 } 1301 kring->nr_hwtail = nm_i; 1302 } 1303 kring->nr_kflags &= ~NKR_PENDINTR; 1304 } 1305 /* 1306 * Second part: skip past packets that userspace has released. 1307 * (kring->nr_hwcur to head excluded), 1308 * and make the buffers available for reception. 1309 * As usual nm_i is the index in the netmap ring, 1310 * nic_i is the index in the NIC ring, and 1311 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1312 */ 1313 netmap_fl_refill(rxq, kring, false); 1314 1315 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1316 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1317 1318 return (0); 1319 } 1320 1321 static void 1322 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1323 { 1324 if_ctx_t ctx = if_getsoftc(na->ifp); 1325 1326 CTX_LOCK(ctx); 1327 if (onoff) { 1328 IFDI_INTR_ENABLE(ctx); 1329 } else { 1330 IFDI_INTR_DISABLE(ctx); 1331 } 1332 CTX_UNLOCK(ctx); 1333 } 1334 1335 static int 1336 iflib_netmap_attach(if_ctx_t ctx) 1337 { 1338 struct netmap_adapter na; 1339 1340 bzero(&na, sizeof(na)); 1341 1342 na.ifp = ctx->ifc_ifp; 1343 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1344 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1345 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1346 1347 na.num_tx_desc = iflib_num_tx_descs(ctx); 1348 na.num_rx_desc = iflib_num_rx_descs(ctx); 1349 na.nm_txsync = iflib_netmap_txsync; 1350 na.nm_rxsync = iflib_netmap_rxsync; 1351 na.nm_register = iflib_netmap_register; 1352 na.nm_intr = iflib_netmap_intr; 1353 na.nm_config = iflib_netmap_config; 1354 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1355 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1356 return (netmap_attach(&na)); 1357 } 1358 1359 static int 1360 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1361 { 1362 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1363 struct netmap_slot *slot; 1364 1365 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1366 if (slot == NULL) 1367 return (0); 1368 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1369 /* 1370 * In netmap mode, set the map for the packet buffer. 1371 * NOTE: Some drivers (not this one) also need to set 1372 * the physical buffer address in the NIC ring. 1373 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1374 * netmap slot index, si 1375 */ 1376 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1377 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1378 NMB(na, slot + si)); 1379 } 1380 return (1); 1381 } 1382 1383 static int 1384 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1385 { 1386 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1387 struct netmap_kring *kring; 1388 struct netmap_slot *slot; 1389 1390 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1391 if (slot == NULL) 1392 return (0); 1393 kring = na->rx_rings[rxq->ifr_id]; 1394 netmap_fl_refill(rxq, kring, true); 1395 return (1); 1396 } 1397 1398 static void 1399 iflib_netmap_timer(void *arg) 1400 { 1401 iflib_txq_t txq = arg; 1402 if_ctx_t ctx = txq->ift_ctx; 1403 1404 /* 1405 * Wake up the netmap application, to give it a chance to 1406 * call txsync and reclaim more completed TX buffers. 1407 */ 1408 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1409 } 1410 1411 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1412 1413 #else 1414 #define iflib_netmap_txq_init(ctx, txq) (0) 1415 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1416 #define iflib_netmap_detach(ifp) 1417 #define netmap_enable_all_rings(ifp) 1418 #define netmap_disable_all_rings(ifp) 1419 1420 #define iflib_netmap_attach(ctx) (0) 1421 #define netmap_rx_irq(ifp, qid, budget) (0) 1422 #endif 1423 1424 #if defined(__i386__) || defined(__amd64__) 1425 static __inline void 1426 prefetch(void *x) 1427 { 1428 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1429 } 1430 1431 static __inline void 1432 prefetch2cachelines(void *x) 1433 { 1434 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1435 #if (CACHE_LINE_SIZE < 128) 1436 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1437 #endif 1438 } 1439 #else 1440 static __inline void 1441 prefetch(void *x) 1442 { 1443 } 1444 1445 static __inline void 1446 prefetch2cachelines(void *x) 1447 { 1448 } 1449 #endif 1450 1451 static void 1452 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1453 { 1454 iflib_fl_t fl; 1455 1456 fl = &rxq->ifr_fl[flid]; 1457 iru->iru_paddrs = fl->ifl_bus_addrs; 1458 iru->iru_idxs = fl->ifl_rxd_idxs; 1459 iru->iru_qsidx = rxq->ifr_id; 1460 iru->iru_buf_size = fl->ifl_buf_size; 1461 iru->iru_flidx = fl->ifl_id; 1462 } 1463 1464 static void 1465 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1466 { 1467 if (err) 1468 return; 1469 *(bus_addr_t *) arg = segs[0].ds_addr; 1470 } 1471 1472 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1473 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1474 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1475 1476 int 1477 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1478 { 1479 int err; 1480 device_t dev = ctx->ifc_dev; 1481 bus_addr_t lowaddr; 1482 1483 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1484 1485 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1486 align, 0, /* alignment, bounds */ 1487 lowaddr, /* lowaddr */ 1488 BUS_SPACE_MAXADDR, /* highaddr */ 1489 NULL, NULL, /* filter, filterarg */ 1490 size, /* maxsize */ 1491 1, /* nsegments */ 1492 size, /* maxsegsize */ 1493 BUS_DMA_ALLOCNOW, /* flags */ 1494 NULL, /* lockfunc */ 1495 NULL, /* lockarg */ 1496 &dma->idi_tag); 1497 if (err) { 1498 device_printf(dev, 1499 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1500 __func__, err, size, align); 1501 goto fail_0; 1502 } 1503 1504 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1505 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1506 if (err) { 1507 device_printf(dev, 1508 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1509 __func__, (uintmax_t)size, err); 1510 goto fail_1; 1511 } 1512 1513 dma->idi_paddr = IF_BAD_DMA; 1514 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1515 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1516 if (err || dma->idi_paddr == IF_BAD_DMA) { 1517 device_printf(dev, 1518 "%s: bus_dmamap_load failed: %d\n", 1519 __func__, err); 1520 goto fail_2; 1521 } 1522 1523 dma->idi_size = size; 1524 return (0); 1525 1526 fail_2: 1527 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1528 fail_1: 1529 bus_dma_tag_destroy(dma->idi_tag); 1530 fail_0: 1531 dma->idi_tag = NULL; 1532 1533 return (err); 1534 } 1535 1536 int 1537 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1538 { 1539 if_shared_ctx_t sctx = ctx->ifc_sctx; 1540 1541 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1542 1543 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1544 } 1545 1546 int 1547 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1548 { 1549 int i, err; 1550 iflib_dma_info_t *dmaiter; 1551 1552 dmaiter = dmalist; 1553 for (i = 0; i < count; i++, dmaiter++) { 1554 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1555 break; 1556 } 1557 if (err) 1558 iflib_dma_free_multi(dmalist, i); 1559 return (err); 1560 } 1561 1562 void 1563 iflib_dma_free(iflib_dma_info_t dma) 1564 { 1565 if (dma->idi_tag == NULL) 1566 return; 1567 if (dma->idi_paddr != IF_BAD_DMA) { 1568 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1569 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1570 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1571 dma->idi_paddr = IF_BAD_DMA; 1572 } 1573 if (dma->idi_vaddr != NULL) { 1574 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1575 dma->idi_vaddr = NULL; 1576 } 1577 bus_dma_tag_destroy(dma->idi_tag); 1578 dma->idi_tag = NULL; 1579 } 1580 1581 void 1582 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1583 { 1584 int i; 1585 iflib_dma_info_t *dmaiter = dmalist; 1586 1587 for (i = 0; i < count; i++, dmaiter++) 1588 iflib_dma_free(*dmaiter); 1589 } 1590 1591 static int 1592 iflib_fast_intr(void *arg) 1593 { 1594 iflib_filter_info_t info = arg; 1595 struct grouptask *gtask = info->ifi_task; 1596 int result; 1597 1598 DBG_COUNTER_INC(fast_intrs); 1599 if (info->ifi_filter != NULL) { 1600 result = info->ifi_filter(info->ifi_filter_arg); 1601 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1602 return (result); 1603 } 1604 1605 GROUPTASK_ENQUEUE(gtask); 1606 return (FILTER_HANDLED); 1607 } 1608 1609 static int 1610 iflib_fast_intr_rxtx(void *arg) 1611 { 1612 iflib_filter_info_t info = arg; 1613 struct grouptask *gtask = info->ifi_task; 1614 if_ctx_t ctx; 1615 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1616 iflib_txq_t txq; 1617 void *sc; 1618 int i, cidx, result; 1619 qidx_t txqid; 1620 bool intr_enable, intr_legacy; 1621 1622 DBG_COUNTER_INC(fast_intrs); 1623 if (info->ifi_filter != NULL) { 1624 result = info->ifi_filter(info->ifi_filter_arg); 1625 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1626 return (result); 1627 } 1628 1629 ctx = rxq->ifr_ctx; 1630 sc = ctx->ifc_softc; 1631 intr_enable = false; 1632 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1633 MPASS(rxq->ifr_ntxqirq); 1634 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1635 txqid = rxq->ifr_txqid[i]; 1636 txq = &ctx->ifc_txqs[txqid]; 1637 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1638 BUS_DMASYNC_POSTREAD); 1639 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1640 if (intr_legacy) 1641 intr_enable = true; 1642 else 1643 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1644 continue; 1645 } 1646 GROUPTASK_ENQUEUE(&txq->ift_task); 1647 } 1648 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1649 cidx = rxq->ifr_cq_cidx; 1650 else 1651 cidx = rxq->ifr_fl[0].ifl_cidx; 1652 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1653 GROUPTASK_ENQUEUE(gtask); 1654 else { 1655 if (intr_legacy) 1656 intr_enable = true; 1657 else 1658 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1659 DBG_COUNTER_INC(rx_intr_enables); 1660 } 1661 if (intr_enable) 1662 IFDI_INTR_ENABLE(ctx); 1663 return (FILTER_HANDLED); 1664 } 1665 1666 static int 1667 iflib_fast_intr_ctx(void *arg) 1668 { 1669 iflib_filter_info_t info = arg; 1670 struct grouptask *gtask = info->ifi_task; 1671 int result; 1672 1673 DBG_COUNTER_INC(fast_intrs); 1674 if (info->ifi_filter != NULL) { 1675 result = info->ifi_filter(info->ifi_filter_arg); 1676 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1677 return (result); 1678 } 1679 1680 if (gtask->gt_taskqueue != NULL) 1681 GROUPTASK_ENQUEUE(gtask); 1682 return (FILTER_HANDLED); 1683 } 1684 1685 static int 1686 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1687 driver_filter_t filter, driver_intr_t handler, void *arg, 1688 const char *name) 1689 { 1690 struct resource *res; 1691 void *tag = NULL; 1692 device_t dev = ctx->ifc_dev; 1693 int flags, i, rc; 1694 1695 flags = RF_ACTIVE; 1696 if (ctx->ifc_flags & IFC_LEGACY) 1697 flags |= RF_SHAREABLE; 1698 MPASS(rid < 512); 1699 i = rid; 1700 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1701 if (res == NULL) { 1702 device_printf(dev, 1703 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1704 return (ENOMEM); 1705 } 1706 irq->ii_res = res; 1707 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1708 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1709 filter, handler, arg, &tag); 1710 if (rc != 0) { 1711 device_printf(dev, 1712 "failed to setup interrupt for rid %d, name %s: %d\n", 1713 rid, name ? name : "unknown", rc); 1714 return (rc); 1715 } else if (name) 1716 bus_describe_intr(dev, res, tag, "%s", name); 1717 1718 irq->ii_tag = tag; 1719 return (0); 1720 } 1721 1722 /********************************************************************* 1723 * 1724 * Allocate DMA resources for TX buffers as well as memory for the TX 1725 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1726 * iflib_sw_tx_desc_array structure, storing all the information that 1727 * is needed to transmit a packet on the wire. This is called only 1728 * once at attach, setup is done every reset. 1729 * 1730 **********************************************************************/ 1731 static int 1732 iflib_txsd_alloc(iflib_txq_t txq) 1733 { 1734 if_ctx_t ctx = txq->ift_ctx; 1735 if_shared_ctx_t sctx = ctx->ifc_sctx; 1736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1737 device_t dev = ctx->ifc_dev; 1738 bus_size_t tsomaxsize; 1739 bus_addr_t lowaddr; 1740 int err, nsegments, ntsosegments; 1741 bool tso; 1742 1743 nsegments = scctx->isc_tx_nsegments; 1744 ntsosegments = scctx->isc_tx_tso_segments_max; 1745 tsomaxsize = scctx->isc_tx_tso_size_max; 1746 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1747 tsomaxsize += sizeof(struct ether_vlan_header); 1748 MPASS(scctx->isc_ntxd[0] > 0); 1749 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1750 MPASS(nsegments > 0); 1751 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1752 MPASS(ntsosegments > 0); 1753 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1754 } 1755 1756 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1757 1758 /* 1759 * Set up DMA tags for TX buffers. 1760 */ 1761 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1762 1, 0, /* alignment, bounds */ 1763 lowaddr, /* lowaddr */ 1764 BUS_SPACE_MAXADDR, /* highaddr */ 1765 NULL, NULL, /* filter, filterarg */ 1766 sctx->isc_tx_maxsize, /* maxsize */ 1767 nsegments, /* nsegments */ 1768 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1769 0, /* flags */ 1770 NULL, /* lockfunc */ 1771 NULL, /* lockfuncarg */ 1772 &txq->ift_buf_tag))) { 1773 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1774 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1775 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1776 goto fail; 1777 } 1778 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1779 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1780 1, 0, /* alignment, bounds */ 1781 lowaddr, /* lowaddr */ 1782 BUS_SPACE_MAXADDR, /* highaddr */ 1783 NULL, NULL, /* filter, filterarg */ 1784 tsomaxsize, /* maxsize */ 1785 ntsosegments, /* nsegments */ 1786 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1787 0, /* flags */ 1788 NULL, /* lockfunc */ 1789 NULL, /* lockfuncarg */ 1790 &txq->ift_tso_buf_tag))) { 1791 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1792 err); 1793 goto fail; 1794 } 1795 1796 /* Allocate memory for the TX mbuf map. */ 1797 if (!(txq->ift_sds.ifsd_m = 1798 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1799 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1800 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1801 err = ENOMEM; 1802 goto fail; 1803 } 1804 1805 /* 1806 * Create the DMA maps for TX buffers. 1807 */ 1808 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1809 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1810 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1811 device_printf(dev, 1812 "Unable to allocate TX buffer DMA map memory\n"); 1813 err = ENOMEM; 1814 goto fail; 1815 } 1816 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1817 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1818 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1819 device_printf(dev, 1820 "Unable to allocate TSO TX buffer map memory\n"); 1821 err = ENOMEM; 1822 goto fail; 1823 } 1824 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1825 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1826 &txq->ift_sds.ifsd_map[i]); 1827 if (err != 0) { 1828 device_printf(dev, "Unable to create TX DMA map\n"); 1829 goto fail; 1830 } 1831 if (!tso) 1832 continue; 1833 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1834 &txq->ift_sds.ifsd_tso_map[i]); 1835 if (err != 0) { 1836 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1837 goto fail; 1838 } 1839 } 1840 return (0); 1841 fail: 1842 /* We free all, it handles case where we are in the middle */ 1843 iflib_tx_structures_free(ctx); 1844 return (err); 1845 } 1846 1847 static void 1848 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1849 { 1850 bus_dmamap_t map; 1851 1852 if (txq->ift_sds.ifsd_map != NULL) { 1853 map = txq->ift_sds.ifsd_map[i]; 1854 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1855 bus_dmamap_unload(txq->ift_buf_tag, map); 1856 bus_dmamap_destroy(txq->ift_buf_tag, map); 1857 txq->ift_sds.ifsd_map[i] = NULL; 1858 } 1859 1860 if (txq->ift_sds.ifsd_tso_map != NULL) { 1861 map = txq->ift_sds.ifsd_tso_map[i]; 1862 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1863 BUS_DMASYNC_POSTWRITE); 1864 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1865 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1866 txq->ift_sds.ifsd_tso_map[i] = NULL; 1867 } 1868 } 1869 1870 static void 1871 iflib_txq_destroy(iflib_txq_t txq) 1872 { 1873 if_ctx_t ctx = txq->ift_ctx; 1874 1875 for (int i = 0; i < txq->ift_size; i++) 1876 iflib_txsd_destroy(ctx, txq, i); 1877 1878 if (txq->ift_br != NULL) { 1879 ifmp_ring_free(txq->ift_br); 1880 txq->ift_br = NULL; 1881 } 1882 1883 mtx_destroy(&txq->ift_mtx); 1884 1885 if (txq->ift_sds.ifsd_map != NULL) { 1886 free(txq->ift_sds.ifsd_map, M_IFLIB); 1887 txq->ift_sds.ifsd_map = NULL; 1888 } 1889 if (txq->ift_sds.ifsd_tso_map != NULL) { 1890 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1891 txq->ift_sds.ifsd_tso_map = NULL; 1892 } 1893 if (txq->ift_sds.ifsd_m != NULL) { 1894 free(txq->ift_sds.ifsd_m, M_IFLIB); 1895 txq->ift_sds.ifsd_m = NULL; 1896 } 1897 if (txq->ift_buf_tag != NULL) { 1898 bus_dma_tag_destroy(txq->ift_buf_tag); 1899 txq->ift_buf_tag = NULL; 1900 } 1901 if (txq->ift_tso_buf_tag != NULL) { 1902 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1903 txq->ift_tso_buf_tag = NULL; 1904 } 1905 if (txq->ift_ifdi != NULL) { 1906 free(txq->ift_ifdi, M_IFLIB); 1907 } 1908 } 1909 1910 static void 1911 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1912 { 1913 struct mbuf **mp; 1914 1915 mp = &txq->ift_sds.ifsd_m[i]; 1916 if (*mp == NULL) 1917 return; 1918 1919 if (txq->ift_sds.ifsd_map != NULL) { 1920 bus_dmamap_sync(txq->ift_buf_tag, 1921 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1922 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1923 } 1924 if (txq->ift_sds.ifsd_tso_map != NULL) { 1925 bus_dmamap_sync(txq->ift_tso_buf_tag, 1926 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1927 bus_dmamap_unload(txq->ift_tso_buf_tag, 1928 txq->ift_sds.ifsd_tso_map[i]); 1929 } 1930 m_freem(*mp); 1931 DBG_COUNTER_INC(tx_frees); 1932 *mp = NULL; 1933 } 1934 1935 static int 1936 iflib_txq_setup(iflib_txq_t txq) 1937 { 1938 if_ctx_t ctx = txq->ift_ctx; 1939 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1940 if_shared_ctx_t sctx = ctx->ifc_sctx; 1941 iflib_dma_info_t di; 1942 int i; 1943 1944 /* Set number of descriptors available */ 1945 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1946 /* XXX make configurable */ 1947 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1948 1949 /* Reset indices */ 1950 txq->ift_cidx_processed = 0; 1951 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1952 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1953 1954 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1955 bzero((void *)di->idi_vaddr, di->idi_size); 1956 1957 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1958 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1959 bus_dmamap_sync(di->idi_tag, di->idi_map, 1960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1961 return (0); 1962 } 1963 1964 /********************************************************************* 1965 * 1966 * Allocate DMA resources for RX buffers as well as memory for the RX 1967 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1968 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1969 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1970 * Since we use use one entry in iflib_sw_rx_desc_array per received 1971 * packet, the maximum number of entries we'll need is equal to the 1972 * number of hardware receive descriptors that we've allocated. 1973 * 1974 **********************************************************************/ 1975 static int 1976 iflib_rxsd_alloc(iflib_rxq_t rxq) 1977 { 1978 if_ctx_t ctx = rxq->ifr_ctx; 1979 if_shared_ctx_t sctx = ctx->ifc_sctx; 1980 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1981 device_t dev = ctx->ifc_dev; 1982 iflib_fl_t fl; 1983 bus_addr_t lowaddr; 1984 int err; 1985 1986 MPASS(scctx->isc_nrxd[0] > 0); 1987 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1988 1989 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1990 1991 fl = rxq->ifr_fl; 1992 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1993 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1994 /* Set up DMA tag for RX buffers. */ 1995 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1996 1, 0, /* alignment, bounds */ 1997 lowaddr, /* lowaddr */ 1998 BUS_SPACE_MAXADDR, /* highaddr */ 1999 NULL, NULL, /* filter, filterarg */ 2000 sctx->isc_rx_maxsize, /* maxsize */ 2001 sctx->isc_rx_nsegments, /* nsegments */ 2002 sctx->isc_rx_maxsegsize, /* maxsegsize */ 2003 0, /* flags */ 2004 NULL, /* lockfunc */ 2005 NULL, /* lockarg */ 2006 &fl->ifl_buf_tag); 2007 if (err) { 2008 device_printf(dev, 2009 "Unable to allocate RX DMA tag: %d\n", err); 2010 goto fail; 2011 } 2012 2013 /* Allocate memory for the RX mbuf map. */ 2014 if (!(fl->ifl_sds.ifsd_m = 2015 (struct mbuf **) malloc(sizeof(struct mbuf *) * 2016 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2017 device_printf(dev, 2018 "Unable to allocate RX mbuf map memory\n"); 2019 err = ENOMEM; 2020 goto fail; 2021 } 2022 2023 /* Allocate memory for the direct RX cluster pointer map. */ 2024 if (!(fl->ifl_sds.ifsd_cl = 2025 (caddr_t *) malloc(sizeof(caddr_t) * 2026 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2027 device_printf(dev, 2028 "Unable to allocate RX cluster map memory\n"); 2029 err = ENOMEM; 2030 goto fail; 2031 } 2032 2033 /* Allocate memory for the RX cluster bus address map. */ 2034 if (!(fl->ifl_sds.ifsd_ba = 2035 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2036 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2037 device_printf(dev, 2038 "Unable to allocate RX bus address map memory\n"); 2039 err = ENOMEM; 2040 goto fail; 2041 } 2042 2043 /* 2044 * Create the DMA maps for RX buffers. 2045 */ 2046 if (!(fl->ifl_sds.ifsd_map = 2047 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2048 device_printf(dev, 2049 "Unable to allocate RX buffer DMA map memory\n"); 2050 err = ENOMEM; 2051 goto fail; 2052 } 2053 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2054 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2055 &fl->ifl_sds.ifsd_map[i]); 2056 if (err != 0) { 2057 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2058 goto fail; 2059 } 2060 } 2061 } 2062 return (0); 2063 2064 fail: 2065 iflib_rx_structures_free(ctx); 2066 return (err); 2067 } 2068 2069 /* 2070 * Internal service routines 2071 */ 2072 2073 struct rxq_refill_cb_arg { 2074 int error; 2075 bus_dma_segment_t seg; 2076 int nseg; 2077 }; 2078 2079 static void 2080 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2081 { 2082 struct rxq_refill_cb_arg *cb_arg = arg; 2083 2084 cb_arg->error = error; 2085 cb_arg->seg = segs[0]; 2086 cb_arg->nseg = nseg; 2087 } 2088 2089 /** 2090 * iflib_fl_refill - refill an rxq free-buffer list 2091 * @ctx: the iflib context 2092 * @fl: the free list to refill 2093 * @count: the number of new buffers to allocate 2094 * 2095 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2096 * The caller must assure that @count does not exceed the queue's capacity 2097 * minus one (since we always leave a descriptor unavailable). 2098 */ 2099 static uint8_t 2100 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2101 { 2102 struct if_rxd_update iru; 2103 struct rxq_refill_cb_arg cb_arg; 2104 struct mbuf *m; 2105 caddr_t cl, *sd_cl; 2106 struct mbuf **sd_m; 2107 bus_dmamap_t *sd_map; 2108 bus_addr_t bus_addr, *sd_ba; 2109 int err, frag_idx, i, idx, n, pidx; 2110 qidx_t credits; 2111 2112 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2113 2114 sd_m = fl->ifl_sds.ifsd_m; 2115 sd_map = fl->ifl_sds.ifsd_map; 2116 sd_cl = fl->ifl_sds.ifsd_cl; 2117 sd_ba = fl->ifl_sds.ifsd_ba; 2118 pidx = fl->ifl_pidx; 2119 idx = pidx; 2120 frag_idx = fl->ifl_fragidx; 2121 credits = fl->ifl_credits; 2122 2123 i = 0; 2124 n = count; 2125 MPASS(n > 0); 2126 MPASS(credits + n <= fl->ifl_size); 2127 2128 if (pidx < fl->ifl_cidx) 2129 MPASS(pidx + n <= fl->ifl_cidx); 2130 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2131 MPASS(fl->ifl_gen == 0); 2132 if (pidx > fl->ifl_cidx) 2133 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2134 2135 DBG_COUNTER_INC(fl_refills); 2136 if (n > 8) 2137 DBG_COUNTER_INC(fl_refills_large); 2138 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2139 while (n-- > 0) { 2140 /* 2141 * We allocate an uninitialized mbuf + cluster, mbuf is 2142 * initialized after rx. 2143 * 2144 * If the cluster is still set then we know a minimum sized 2145 * packet was received 2146 */ 2147 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2148 &frag_idx); 2149 if (frag_idx < 0) 2150 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2151 MPASS(frag_idx >= 0); 2152 if ((cl = sd_cl[frag_idx]) == NULL) { 2153 #ifndef __HAIKU__ 2154 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2155 if (__predict_false(cl == NULL)) 2156 #else 2157 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 2158 #endif 2159 break; 2160 2161 cb_arg.error = 0; 2162 MPASS(sd_map != NULL); 2163 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2164 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2165 BUS_DMA_NOWAIT); 2166 if (__predict_false(err != 0 || cb_arg.error)) { 2167 #ifndef __HAIKU__ 2168 uma_zfree(fl->ifl_zone, cl); 2169 #else 2170 m_free(cl); 2171 #endif 2172 break; 2173 } 2174 2175 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2176 sd_cl[frag_idx] = cl; 2177 #if MEMORY_LOGGING 2178 fl->ifl_cl_enqueued++; 2179 #endif 2180 } else { 2181 bus_addr = sd_ba[frag_idx]; 2182 } 2183 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2184 BUS_DMASYNC_PREREAD); 2185 2186 if (sd_m[frag_idx] == NULL) { 2187 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2188 if (__predict_false(m == NULL)) 2189 break; 2190 sd_m[frag_idx] = m; 2191 } 2192 bit_set(fl->ifl_rx_bitmap, frag_idx); 2193 #if MEMORY_LOGGING 2194 fl->ifl_m_enqueued++; 2195 #endif 2196 2197 DBG_COUNTER_INC(rx_allocs); 2198 fl->ifl_rxd_idxs[i] = frag_idx; 2199 fl->ifl_bus_addrs[i] = bus_addr; 2200 credits++; 2201 i++; 2202 MPASS(credits <= fl->ifl_size); 2203 if (++idx == fl->ifl_size) { 2204 #ifdef INVARIANTS 2205 fl->ifl_gen = 1; 2206 #endif 2207 idx = 0; 2208 } 2209 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2210 iru.iru_pidx = pidx; 2211 iru.iru_count = i; 2212 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2213 fl->ifl_pidx = idx; 2214 fl->ifl_credits = credits; 2215 pidx = idx; 2216 i = 0; 2217 } 2218 } 2219 2220 if (n < count - 1) { 2221 if (i != 0) { 2222 iru.iru_pidx = pidx; 2223 iru.iru_count = i; 2224 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2225 fl->ifl_pidx = idx; 2226 fl->ifl_credits = credits; 2227 } 2228 DBG_COUNTER_INC(rxd_flush); 2229 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2230 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2231 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2232 fl->ifl_id, fl->ifl_pidx); 2233 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2234 fl->ifl_fragidx = frag_idx + 1; 2235 if (fl->ifl_fragidx == fl->ifl_size) 2236 fl->ifl_fragidx = 0; 2237 } else { 2238 fl->ifl_fragidx = frag_idx; 2239 } 2240 } 2241 2242 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2243 } 2244 2245 static inline uint8_t 2246 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2247 { 2248 /* 2249 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2250 * This is important as it confuses most NICs. For instance, 2251 * Intel NICs have (per receive ring) RDH and RDT registers, where 2252 * RDH points to the next receive descriptor to be used by the NIC, 2253 * and RDT for the next receive descriptor to be published by the 2254 * driver to the NIC (RDT - 1 is thus the last valid one). 2255 * The condition RDH == RDT means no descriptors are available to 2256 * the NIC, and thus it would be ambiguous if it also meant that 2257 * all the descriptors are available to the NIC. 2258 */ 2259 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2260 #ifdef INVARIANTS 2261 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2262 #endif 2263 2264 MPASS(fl->ifl_credits <= fl->ifl_size); 2265 MPASS(reclaimable == delta); 2266 2267 if (reclaimable > 0) 2268 return (iflib_fl_refill(ctx, fl, reclaimable)); 2269 return (0); 2270 } 2271 2272 uint8_t 2273 iflib_in_detach(if_ctx_t ctx) 2274 { 2275 bool in_detach; 2276 2277 STATE_LOCK(ctx); 2278 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2279 STATE_UNLOCK(ctx); 2280 return (in_detach); 2281 } 2282 2283 static void 2284 iflib_fl_bufs_free(iflib_fl_t fl) 2285 { 2286 iflib_dma_info_t idi = fl->ifl_ifdi; 2287 bus_dmamap_t sd_map; 2288 uint32_t i; 2289 2290 for (i = 0; i < fl->ifl_size; i++) { 2291 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2292 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2293 2294 if (*sd_cl != NULL) { 2295 sd_map = fl->ifl_sds.ifsd_map[i]; 2296 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2297 BUS_DMASYNC_POSTREAD); 2298 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2299 #ifndef __HAIKU__ 2300 uma_zfree(fl->ifl_zone, *sd_cl); 2301 #else 2302 struct mbuf* mb = m_get(0, MT_DATA); 2303 m_cljset(mb, *sd_cl, fl->ifl_cltype); 2304 m_free(mb); 2305 #endif 2306 *sd_cl = NULL; 2307 if (*sd_m != NULL) { 2308 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2309 #ifndef __HAIKU__ 2310 m_free_raw(*sd_m); 2311 #else 2312 m_free(*sd_m); 2313 #endif 2314 *sd_m = NULL; 2315 } 2316 } else { 2317 MPASS(*sd_m == NULL); 2318 } 2319 #if MEMORY_LOGGING 2320 fl->ifl_m_dequeued++; 2321 fl->ifl_cl_dequeued++; 2322 #endif 2323 } 2324 #ifdef INVARIANTS 2325 for (i = 0; i < fl->ifl_size; i++) { 2326 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2327 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2328 } 2329 #endif 2330 /* 2331 * Reset free list values 2332 */ 2333 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2334 bzero(idi->idi_vaddr, idi->idi_size); 2335 } 2336 2337 /********************************************************************* 2338 * 2339 * Initialize a free list and its buffers. 2340 * 2341 **********************************************************************/ 2342 static int 2343 iflib_fl_setup(iflib_fl_t fl) 2344 { 2345 iflib_rxq_t rxq = fl->ifl_rxq; 2346 if_ctx_t ctx = rxq->ifr_ctx; 2347 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2348 int qidx; 2349 2350 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2351 /* 2352 ** Free current RX buffer structs and their mbufs 2353 */ 2354 iflib_fl_bufs_free(fl); 2355 /* Now replenish the mbufs */ 2356 MPASS(fl->ifl_credits == 0); 2357 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2358 if (scctx->isc_rxd_buf_size[qidx] != 0) 2359 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2360 else 2361 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2362 /* 2363 * ifl_buf_size may be a driver-supplied value, so pull it up 2364 * to the selected mbuf size. 2365 */ 2366 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2367 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2368 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2369 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2370 #ifndef __HAIKU__ 2371 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2372 #endif 2373 2374 /* 2375 * Avoid pre-allocating zillions of clusters to an idle card 2376 * potentially speeding up attach. In any case make sure 2377 * to leave a descriptor unavailable. See the comment in 2378 * iflib_fl_refill_all(). 2379 */ 2380 MPASS(fl->ifl_size > 0); 2381 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2382 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2383 return (ENOBUFS); 2384 /* 2385 * handle failure 2386 */ 2387 MPASS(rxq != NULL); 2388 MPASS(fl->ifl_ifdi != NULL); 2389 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2391 return (0); 2392 } 2393 2394 /********************************************************************* 2395 * 2396 * Free receive ring data structures 2397 * 2398 **********************************************************************/ 2399 static void 2400 iflib_rx_sds_free(iflib_rxq_t rxq) 2401 { 2402 iflib_fl_t fl; 2403 int i, j; 2404 2405 if (rxq->ifr_fl != NULL) { 2406 for (i = 0; i < rxq->ifr_nfl; i++) { 2407 fl = &rxq->ifr_fl[i]; 2408 if (fl->ifl_buf_tag != NULL) { 2409 if (fl->ifl_sds.ifsd_map != NULL) { 2410 for (j = 0; j < fl->ifl_size; j++) { 2411 bus_dmamap_sync( 2412 fl->ifl_buf_tag, 2413 fl->ifl_sds.ifsd_map[j], 2414 BUS_DMASYNC_POSTREAD); 2415 bus_dmamap_unload( 2416 fl->ifl_buf_tag, 2417 fl->ifl_sds.ifsd_map[j]); 2418 bus_dmamap_destroy( 2419 fl->ifl_buf_tag, 2420 fl->ifl_sds.ifsd_map[j]); 2421 } 2422 } 2423 bus_dma_tag_destroy(fl->ifl_buf_tag); 2424 fl->ifl_buf_tag = NULL; 2425 } 2426 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2427 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2428 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2429 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2430 free(fl->ifl_rx_bitmap, M_IFLIB); 2431 fl->ifl_sds.ifsd_m = NULL; 2432 fl->ifl_sds.ifsd_cl = NULL; 2433 fl->ifl_sds.ifsd_ba = NULL; 2434 fl->ifl_sds.ifsd_map = NULL; 2435 fl->ifl_rx_bitmap = NULL; 2436 } 2437 free(rxq->ifr_fl, M_IFLIB); 2438 rxq->ifr_fl = NULL; 2439 free(rxq->ifr_ifdi, M_IFLIB); 2440 rxq->ifr_ifdi = NULL; 2441 rxq->ifr_cq_cidx = 0; 2442 } 2443 } 2444 2445 /* 2446 * Timer routine 2447 */ 2448 static void 2449 iflib_timer(void *arg) 2450 { 2451 iflib_txq_t txq = arg; 2452 if_ctx_t ctx = txq->ift_ctx; 2453 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2454 uint64_t this_tick = ticks; 2455 2456 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2457 return; 2458 2459 /* 2460 ** Check on the state of the TX queue(s), this 2461 ** can be done without the lock because its RO 2462 ** and the HUNG state will be static if set. 2463 */ 2464 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2465 txq->ift_last_timer_tick = this_tick; 2466 IFDI_TIMER(ctx, txq->ift_id); 2467 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2468 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2469 (sctx->isc_pause_frames == 0))) 2470 goto hung; 2471 2472 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2473 ifmp_ring_is_stalled(txq->ift_br)) { 2474 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2475 ("queue can't be marked as hung if interface is down")); 2476 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2477 } 2478 txq->ift_cleaned_prev = txq->ift_cleaned; 2479 } 2480 /* handle any laggards */ 2481 if (txq->ift_db_pending) 2482 GROUPTASK_ENQUEUE(&txq->ift_task); 2483 2484 sctx->isc_pause_frames = 0; 2485 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2486 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2487 txq, txq->ift_timer.c_cpu); 2488 return; 2489 2490 hung: 2491 device_printf(ctx->ifc_dev, 2492 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2493 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2494 STATE_LOCK(ctx); 2495 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2496 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2497 iflib_admin_intr_deferred(ctx); 2498 STATE_UNLOCK(ctx); 2499 } 2500 2501 static uint16_t 2502 iflib_get_mbuf_size_for(unsigned int size) 2503 { 2504 2505 if (size <= MCLBYTES) 2506 return (MCLBYTES); 2507 else 2508 return (MJUMPAGESIZE); 2509 } 2510 2511 static void 2512 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2513 { 2514 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2515 2516 /* 2517 * XXX don't set the max_frame_size to larger 2518 * than the hardware can handle 2519 */ 2520 ctx->ifc_rx_mbuf_sz = 2521 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2522 } 2523 2524 uint32_t 2525 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2526 { 2527 2528 return (ctx->ifc_rx_mbuf_sz); 2529 } 2530 2531 static void 2532 iflib_init_locked(if_ctx_t ctx) 2533 { 2534 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2535 if_t ifp = ctx->ifc_ifp; 2536 iflib_fl_t fl; 2537 iflib_txq_t txq; 2538 iflib_rxq_t rxq; 2539 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2540 2541 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2542 IFDI_INTR_DISABLE(ctx); 2543 2544 /* 2545 * See iflib_stop(). Useful in case iflib_init_locked() is 2546 * called without first calling iflib_stop(). 2547 */ 2548 netmap_disable_all_rings(ifp); 2549 2550 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2551 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2552 /* Set hardware offload abilities */ 2553 if_clearhwassist(ifp); 2554 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2555 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2556 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2557 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2558 if (if_getcapenable(ifp) & IFCAP_TSO4) 2559 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2560 if (if_getcapenable(ifp) & IFCAP_TSO6) 2561 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2562 2563 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2564 CALLOUT_LOCK(txq); 2565 callout_stop(&txq->ift_timer); 2566 #ifdef DEV_NETMAP 2567 callout_stop(&txq->ift_netmap_timer); 2568 #endif /* DEV_NETMAP */ 2569 CALLOUT_UNLOCK(txq); 2570 (void)iflib_netmap_txq_init(ctx, txq); 2571 } 2572 2573 /* 2574 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2575 * that drivers can use the value when setting up the hardware receive 2576 * buffers. 2577 */ 2578 iflib_calc_rx_mbuf_sz(ctx); 2579 2580 #ifdef INVARIANTS 2581 i = if_getdrvflags(ifp); 2582 #endif 2583 IFDI_INIT(ctx); 2584 MPASS(if_getdrvflags(ifp) == i); 2585 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2586 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2587 /* This rxq is in netmap mode. Skip normal init. */ 2588 continue; 2589 } 2590 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2591 if (iflib_fl_setup(fl)) { 2592 device_printf(ctx->ifc_dev, 2593 "setting up free list %d failed - " 2594 "check cluster settings\n", j); 2595 goto done; 2596 } 2597 } 2598 } 2599 done: 2600 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2601 IFDI_INTR_ENABLE(ctx); 2602 txq = ctx->ifc_txqs; 2603 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2604 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2605 txq->ift_timer.c_cpu); 2606 2607 /* Re-enable txsync/rxsync. */ 2608 netmap_enable_all_rings(ifp); 2609 } 2610 2611 static int 2612 iflib_media_change(if_t ifp) 2613 { 2614 if_ctx_t ctx = if_getsoftc(ifp); 2615 int err; 2616 2617 CTX_LOCK(ctx); 2618 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2619 iflib_if_init_locked(ctx); 2620 CTX_UNLOCK(ctx); 2621 return (err); 2622 } 2623 2624 static void 2625 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2626 { 2627 if_ctx_t ctx = if_getsoftc(ifp); 2628 2629 CTX_LOCK(ctx); 2630 IFDI_UPDATE_ADMIN_STATUS(ctx); 2631 IFDI_MEDIA_STATUS(ctx, ifmr); 2632 CTX_UNLOCK(ctx); 2633 } 2634 2635 void 2636 iflib_stop(if_ctx_t ctx) 2637 { 2638 iflib_txq_t txq = ctx->ifc_txqs; 2639 iflib_rxq_t rxq = ctx->ifc_rxqs; 2640 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2641 if_shared_ctx_t sctx = ctx->ifc_sctx; 2642 iflib_dma_info_t di; 2643 iflib_fl_t fl; 2644 int i, j; 2645 2646 /* Tell the stack that the interface is no longer active */ 2647 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2648 2649 IFDI_INTR_DISABLE(ctx); 2650 DELAY(1000); 2651 IFDI_STOP(ctx); 2652 DELAY(1000); 2653 2654 /* 2655 * Stop any pending txsync/rxsync and prevent new ones 2656 * form starting. Processes blocked in poll() will get 2657 * POLLERR. 2658 */ 2659 netmap_disable_all_rings(ctx->ifc_ifp); 2660 2661 iflib_debug_reset(); 2662 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2663 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2664 /* make sure all transmitters have completed before proceeding XXX */ 2665 2666 CALLOUT_LOCK(txq); 2667 callout_stop(&txq->ift_timer); 2668 #ifdef DEV_NETMAP 2669 callout_stop(&txq->ift_netmap_timer); 2670 #endif /* DEV_NETMAP */ 2671 CALLOUT_UNLOCK(txq); 2672 2673 /* clean any enqueued buffers */ 2674 iflib_ifmp_purge(txq); 2675 /* Free any existing tx buffers. */ 2676 for (j = 0; j < txq->ift_size; j++) { 2677 iflib_txsd_free(ctx, txq, j); 2678 } 2679 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2680 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2681 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2682 txq->ift_cidx = txq->ift_pidx; 2683 else 2684 txq->ift_cidx = txq->ift_pidx = 0; 2685 2686 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2687 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2688 txq->ift_pullups = 0; 2689 ifmp_ring_reset_stats(txq->ift_br); 2690 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2691 bzero((void *)di->idi_vaddr, di->idi_size); 2692 } 2693 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2694 if (rxq->ifr_task.gt_taskqueue != NULL) 2695 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2696 &rxq->ifr_task.gt_task); 2697 2698 rxq->ifr_cq_cidx = 0; 2699 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2700 bzero((void *)di->idi_vaddr, di->idi_size); 2701 /* also resets the free lists pidx/cidx */ 2702 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2703 iflib_fl_bufs_free(fl); 2704 } 2705 } 2706 2707 static inline caddr_t 2708 calc_next_rxd(iflib_fl_t fl, int cidx) 2709 { 2710 qidx_t size; 2711 int nrxd; 2712 caddr_t start, end, cur, next; 2713 2714 nrxd = fl->ifl_size; 2715 size = fl->ifl_rxd_size; 2716 start = fl->ifl_ifdi->idi_vaddr; 2717 2718 if (__predict_false(size == 0)) 2719 return (start); 2720 cur = start + size*cidx; 2721 end = start + size*nrxd; 2722 next = CACHE_PTR_NEXT(cur); 2723 return (next < end ? next : start); 2724 } 2725 2726 static inline void 2727 prefetch_pkts(iflib_fl_t fl, int cidx) 2728 { 2729 int nextptr; 2730 int nrxd = fl->ifl_size; 2731 caddr_t next_rxd; 2732 2733 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2734 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2735 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2736 next_rxd = calc_next_rxd(fl, cidx); 2737 prefetch(next_rxd); 2738 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2739 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2740 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2741 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2742 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2743 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2744 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2745 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2746 } 2747 2748 static struct mbuf * 2749 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2750 int *pf_rv, if_rxd_info_t ri) 2751 { 2752 bus_dmamap_t map; 2753 iflib_fl_t fl; 2754 caddr_t payload; 2755 struct mbuf *m; 2756 int flid, cidx, len, next; 2757 2758 map = NULL; 2759 flid = irf->irf_flid; 2760 cidx = irf->irf_idx; 2761 fl = &rxq->ifr_fl[flid]; 2762 sd->ifsd_fl = fl; 2763 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2764 fl->ifl_credits--; 2765 #if MEMORY_LOGGING 2766 fl->ifl_m_dequeued++; 2767 #endif 2768 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2769 prefetch_pkts(fl, cidx); 2770 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2771 prefetch(&fl->ifl_sds.ifsd_map[next]); 2772 map = fl->ifl_sds.ifsd_map[cidx]; 2773 2774 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2775 2776 #ifndef __HAIKU__ 2777 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2778 irf->irf_len != 0) { 2779 payload = *sd->ifsd_cl; 2780 payload += ri->iri_pad; 2781 len = ri->iri_len - ri->iri_pad; 2782 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2783 switch (*pf_rv) { 2784 case PFIL_DROPPED: 2785 case PFIL_CONSUMED: 2786 /* 2787 * The filter ate it. Everything is recycled. 2788 */ 2789 m = NULL; 2790 unload = 0; 2791 break; 2792 case PFIL_REALLOCED: 2793 /* 2794 * The filter copied it. Everything is recycled. 2795 * 'm' points at new mbuf. 2796 */ 2797 unload = 0; 2798 break; 2799 case PFIL_PASS: 2800 /* 2801 * Filter said it was OK, so receive like 2802 * normal 2803 */ 2804 m = fl->ifl_sds.ifsd_m[cidx]; 2805 fl->ifl_sds.ifsd_m[cidx] = NULL; 2806 break; 2807 default: 2808 MPASS(0); 2809 } 2810 } else 2811 #endif 2812 { 2813 m = fl->ifl_sds.ifsd_m[cidx]; 2814 fl->ifl_sds.ifsd_m[cidx] = NULL; 2815 if (pf_rv != NULL) 2816 *pf_rv = PFIL_PASS; 2817 } 2818 2819 if (unload && irf->irf_len != 0) 2820 bus_dmamap_unload(fl->ifl_buf_tag, map); 2821 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2822 if (__predict_false(fl->ifl_cidx == 0)) 2823 fl->ifl_gen = 0; 2824 bit_clear(fl->ifl_rx_bitmap, cidx); 2825 return (m); 2826 } 2827 2828 static struct mbuf * 2829 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2830 { 2831 struct mbuf *m, *mh, *mt; 2832 caddr_t cl; 2833 int *pf_rv_ptr, flags, i, padlen; 2834 bool consumed; 2835 2836 i = 0; 2837 mh = NULL; 2838 consumed = false; 2839 *pf_rv = PFIL_PASS; 2840 pf_rv_ptr = pf_rv; 2841 do { 2842 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2843 pf_rv_ptr, ri); 2844 2845 MPASS(*sd->ifsd_cl != NULL); 2846 2847 /* 2848 * Exclude zero-length frags & frags from 2849 * packets the filter has consumed or dropped 2850 */ 2851 if (ri->iri_frags[i].irf_len == 0 || consumed || 2852 #ifndef __HAIKU__ 2853 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED 2854 #else 2855 0 2856 #endif 2857 ) { 2858 if (mh == NULL) { 2859 /* everything saved here */ 2860 consumed = true; 2861 pf_rv_ptr = NULL; 2862 continue; 2863 } 2864 /* XXX we can save the cluster here, but not the mbuf */ 2865 m_init(m, M_NOWAIT, MT_DATA, 0); 2866 m_free(m); 2867 continue; 2868 } 2869 if (mh == NULL) { 2870 flags = M_PKTHDR|M_EXT; 2871 mh = mt = m; 2872 padlen = ri->iri_pad; 2873 } else { 2874 flags = M_EXT; 2875 mt->m_next = m; 2876 mt = m; 2877 /* assuming padding is only on the first fragment */ 2878 padlen = 0; 2879 } 2880 cl = *sd->ifsd_cl; 2881 *sd->ifsd_cl = NULL; 2882 2883 /* Can these two be made one ? */ 2884 m_init(m, M_NOWAIT, MT_DATA, flags); 2885 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2886 /* 2887 * These must follow m_init and m_cljset 2888 */ 2889 m->m_data += padlen; 2890 ri->iri_len -= padlen; 2891 m->m_len = ri->iri_frags[i].irf_len; 2892 } while (++i < ri->iri_nfrags); 2893 2894 return (mh); 2895 } 2896 2897 /* 2898 * Process one software descriptor 2899 */ 2900 static struct mbuf * 2901 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2902 { 2903 struct if_rxsd sd; 2904 struct mbuf *m; 2905 int pf_rv; 2906 2907 /* should I merge this back in now that the two paths are basically duplicated? */ 2908 if (ri->iri_nfrags == 1 && 2909 ri->iri_frags[0].irf_len != 0 && 2910 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2911 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2912 &pf_rv, ri); 2913 if (pf_rv != PFIL_PASS 2914 #ifndef __HAIKU__ 2915 && pf_rv != PFIL_REALLOCED 2916 #endif 2917 ) 2918 return (m); 2919 if (pf_rv == PFIL_PASS) { 2920 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2921 #ifndef __NO_STRICT_ALIGNMENT 2922 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2923 m->m_data += 2; 2924 #endif 2925 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2926 m->m_len = ri->iri_frags[0].irf_len; 2927 m->m_data += ri->iri_pad; 2928 ri->iri_len -= ri->iri_pad; 2929 } 2930 } else { 2931 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2932 if (m == NULL) 2933 return (NULL); 2934 if (pf_rv != PFIL_PASS 2935 #ifndef __HAIKU__ 2936 && pf_rv != PFIL_REALLOCED 2937 #endif 2938 ) 2939 return (m); 2940 } 2941 m->m_pkthdr.len = ri->iri_len; 2942 m->m_pkthdr.rcvif = ri->iri_ifp; 2943 m->m_flags |= ri->iri_flags; 2944 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2945 m->m_pkthdr.flowid = ri->iri_flowid; 2946 M_HASHTYPE_SET(m, ri->iri_rsstype); 2947 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2948 m->m_pkthdr.csum_data = ri->iri_csum_data; 2949 return (m); 2950 } 2951 2952 #if defined(INET6) || defined(INET) 2953 static void 2954 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2955 { 2956 CURVNET_SET(if_getvnet(lc->ifp)); 2957 #if defined(INET6) 2958 *v6 = V_ip6_forwarding; 2959 #endif 2960 #if defined(INET) 2961 *v4 = V_ipforwarding; 2962 #endif 2963 CURVNET_RESTORE(); 2964 } 2965 2966 /* 2967 * Returns true if it's possible this packet could be LROed. 2968 * if it returns false, it is guaranteed that tcp_lro_rx() 2969 * would not return zero. 2970 */ 2971 static bool 2972 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2973 { 2974 #ifndef __HAIKU__ 2975 struct ether_header *eh; 2976 2977 eh = mtod(m, struct ether_header *); 2978 switch (eh->ether_type) { 2979 #if defined(INET6) 2980 case htons(ETHERTYPE_IPV6): 2981 return (!v6_forwarding); 2982 #endif 2983 #if defined (INET) 2984 case htons(ETHERTYPE_IP): 2985 return (!v4_forwarding); 2986 #endif 2987 } 2988 #endif 2989 2990 return false; 2991 } 2992 #else 2993 static void 2994 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2995 { 2996 } 2997 #endif 2998 2999 static void 3000 _task_fn_rx_watchdog(void *context) 3001 { 3002 iflib_rxq_t rxq = context; 3003 3004 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3005 } 3006 3007 static uint8_t 3008 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 3009 { 3010 if_t ifp; 3011 if_ctx_t ctx = rxq->ifr_ctx; 3012 if_shared_ctx_t sctx = ctx->ifc_sctx; 3013 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 3014 int avail, i; 3015 qidx_t *cidxp; 3016 struct if_rxd_info ri; 3017 int err, budget_left, rx_bytes, rx_pkts; 3018 iflib_fl_t fl; 3019 int lro_enabled; 3020 bool v4_forwarding, v6_forwarding, lro_possible; 3021 uint8_t retval = 0; 3022 3023 /* 3024 * XXX early demux data packets so that if_input processing only handles 3025 * acks in interrupt context 3026 */ 3027 struct mbuf *m, *mh, *mt, *mf; 3028 3029 NET_EPOCH_ASSERT(); 3030 3031 lro_possible = v4_forwarding = v6_forwarding = false; 3032 ifp = ctx->ifc_ifp; 3033 mh = mt = NULL; 3034 MPASS(budget > 0); 3035 rx_pkts = rx_bytes = 0; 3036 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 3037 cidxp = &rxq->ifr_cq_cidx; 3038 else 3039 cidxp = &rxq->ifr_fl[0].ifl_cidx; 3040 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 3041 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3042 retval |= iflib_fl_refill_all(ctx, fl); 3043 DBG_COUNTER_INC(rx_unavail); 3044 return (retval); 3045 } 3046 3047 /* pfil needs the vnet to be set */ 3048 CURVNET_SET_QUIET(if_getvnet(ifp)); 3049 for (budget_left = budget; budget_left > 0 && avail > 0;) { 3050 if (__predict_false(!CTX_ACTIVE(ctx))) { 3051 DBG_COUNTER_INC(rx_ctx_inactive); 3052 break; 3053 } 3054 /* 3055 * Reset client set fields to their default values 3056 */ 3057 rxd_info_zero(&ri); 3058 ri.iri_qsidx = rxq->ifr_id; 3059 ri.iri_cidx = *cidxp; 3060 ri.iri_ifp = ifp; 3061 ri.iri_frags = rxq->ifr_frags; 3062 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 3063 3064 if (err) 3065 goto err; 3066 rx_pkts += 1; 3067 rx_bytes += ri.iri_len; 3068 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3069 *cidxp = ri.iri_cidx; 3070 /* Update our consumer index */ 3071 /* XXX NB: shurd - check if this is still safe */ 3072 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3073 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3074 /* was this only a completion queue message? */ 3075 if (__predict_false(ri.iri_nfrags == 0)) 3076 continue; 3077 } 3078 MPASS(ri.iri_nfrags != 0); 3079 MPASS(ri.iri_len != 0); 3080 3081 /* will advance the cidx on the corresponding free lists */ 3082 m = iflib_rxd_pkt_get(rxq, &ri); 3083 avail--; 3084 budget_left--; 3085 if (avail == 0 && budget_left) 3086 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3087 3088 if (__predict_false(m == NULL)) 3089 continue; 3090 3091 /* imm_pkt: -- cxgb */ 3092 if (mh == NULL) 3093 mh = mt = m; 3094 else { 3095 mt->m_nextpkt = m; 3096 mt = m; 3097 } 3098 } 3099 CURVNET_RESTORE(); 3100 /* make sure that we can refill faster than drain */ 3101 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3102 retval |= iflib_fl_refill_all(ctx, fl); 3103 3104 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3105 #ifndef __HAIKU__ 3106 if (lro_enabled) 3107 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3108 #endif 3109 mt = mf = NULL; 3110 while (mh != NULL) { 3111 m = mh; 3112 mh = mh->m_nextpkt; 3113 m->m_nextpkt = NULL; 3114 #ifndef __NO_STRICT_ALIGNMENT 3115 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3116 continue; 3117 #endif 3118 #ifndef __HAIKU__ 3119 #if defined(INET6) || defined(INET) 3120 if (lro_enabled) { 3121 if (!lro_possible) { 3122 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3123 if (lro_possible && mf != NULL) { 3124 ifp->if_input(ifp, mf); 3125 DBG_COUNTER_INC(rx_if_input); 3126 mt = mf = NULL; 3127 } 3128 } 3129 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3130 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3131 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3132 continue; 3133 } 3134 } 3135 #endif 3136 if (lro_possible) { 3137 if_input(ifp, m); 3138 DBG_COUNTER_INC(rx_if_input); 3139 continue; 3140 } 3141 #endif 3142 3143 if (mf == NULL) 3144 mf = m; 3145 if (mt != NULL) 3146 mt->m_nextpkt = m; 3147 mt = m; 3148 } 3149 if (mf != NULL) { 3150 if_input(ifp, mf); 3151 DBG_COUNTER_INC(rx_if_input); 3152 } 3153 3154 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3155 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3156 3157 /* 3158 * Flush any outstanding LRO work 3159 */ 3160 #if defined(INET6) || defined(INET) 3161 #ifndef __HAIKU__ 3162 tcp_lro_flush_all(&rxq->ifr_lc); 3163 #endif 3164 #endif 3165 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3166 retval |= IFLIB_RXEOF_MORE; 3167 return (retval); 3168 err: 3169 STATE_LOCK(ctx); 3170 ctx->ifc_flags |= IFC_DO_RESET; 3171 iflib_admin_intr_deferred(ctx); 3172 STATE_UNLOCK(ctx); 3173 return (0); 3174 } 3175 3176 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3177 static inline qidx_t 3178 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3179 { 3180 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3181 qidx_t minthresh = txq->ift_size / 8; 3182 if (in_use > 4*minthresh) 3183 return (notify_count); 3184 if (in_use > 2*minthresh) 3185 return (notify_count >> 1); 3186 if (in_use > minthresh) 3187 return (notify_count >> 3); 3188 return (0); 3189 } 3190 3191 static inline qidx_t 3192 txq_max_rs_deferred(iflib_txq_t txq) 3193 { 3194 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3195 qidx_t minthresh = txq->ift_size / 8; 3196 if (txq->ift_in_use > 4*minthresh) 3197 return (notify_count); 3198 if (txq->ift_in_use > 2*minthresh) 3199 return (notify_count >> 1); 3200 if (txq->ift_in_use > minthresh) 3201 return (notify_count >> 2); 3202 return (2); 3203 } 3204 3205 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3206 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3207 3208 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3209 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3210 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3211 3212 /* forward compatibility for cxgb */ 3213 #define FIRST_QSET(ctx) 0 3214 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3215 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3216 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3217 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3218 3219 /* XXX we should be setting this to something other than zero */ 3220 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3221 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3222 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3223 3224 static inline bool 3225 iflib_txd_db_check(iflib_txq_t txq, int ring) 3226 { 3227 if_ctx_t ctx = txq->ift_ctx; 3228 qidx_t dbval, max; 3229 3230 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3231 3232 /* force || threshold exceeded || at the edge of the ring */ 3233 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3234 3235 /* 3236 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3237 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3238 * producer index explicitly (INTC). 3239 */ 3240 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3241 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3242 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3243 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3244 3245 /* 3246 * Absent bugs there are zero packets pending so reset pending counts to zero. 3247 */ 3248 txq->ift_db_pending = txq->ift_npending = 0; 3249 return (true); 3250 } 3251 return (false); 3252 } 3253 3254 #ifdef PKT_DEBUG 3255 static void 3256 print_pkt(if_pkt_info_t pi) 3257 { 3258 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3259 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3260 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3261 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3262 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3263 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3264 } 3265 #endif 3266 3267 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3268 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3269 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3270 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3271 3272 /** 3273 * Parses out ethernet header information in the given mbuf. 3274 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3275 * 3276 * This will account for the VLAN header if present. 3277 * 3278 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3279 * types of packets. 3280 */ 3281 static int 3282 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3283 { 3284 struct ether_vlan_header *eh; 3285 struct mbuf *m; 3286 3287 m = *mp; 3288 if (__predict_false(m->m_len < sizeof(*eh))) { 3289 (*pullups)++; 3290 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3291 return (ENOMEM); 3292 } 3293 eh = mtod(m, struct ether_vlan_header *); 3294 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3295 pi->ipi_etype = ntohs(eh->evl_proto); 3296 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3297 } else { 3298 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3299 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3300 } 3301 *mp = m; 3302 3303 return (0); 3304 } 3305 3306 /** 3307 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3308 * Currently this information includes: IP ToS value, IP header version/presence 3309 * 3310 * This is missing some checks and doesn't edit the packet content as it goes, 3311 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3312 */ 3313 static int 3314 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3315 { 3316 struct mbuf *m; 3317 int err; 3318 3319 *pullups = 0; 3320 m = *mp; 3321 if (!M_WRITABLE(m)) { 3322 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3323 return (ENOMEM); 3324 } else { 3325 m_freem(*mp); 3326 DBG_COUNTER_INC(tx_frees); 3327 *mp = m; 3328 } 3329 } 3330 3331 /* Fills out pi->ipi_etype */ 3332 err = iflib_parse_ether_header(pi, mp, pullups); 3333 if (err) 3334 return (err); 3335 m = *mp; 3336 3337 switch (pi->ipi_etype) { 3338 #ifdef INET 3339 case ETHERTYPE_IP: 3340 { 3341 struct mbuf *n; 3342 struct ip *ip = NULL; 3343 int miniplen; 3344 3345 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3346 if (__predict_false(m->m_len < miniplen)) { 3347 /* 3348 * Check for common case where the first mbuf only contains 3349 * the Ethernet header 3350 */ 3351 if (m->m_len == pi->ipi_ehdrlen) { 3352 n = m->m_next; 3353 MPASS(n); 3354 /* If next mbuf contains at least the minimal IP header, then stop */ 3355 if (n->m_len >= sizeof(*ip)) { 3356 ip = (struct ip *)n->m_data; 3357 } else { 3358 (*pullups)++; 3359 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3360 return (ENOMEM); 3361 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3362 } 3363 } else { 3364 (*pullups)++; 3365 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3366 return (ENOMEM); 3367 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3368 } 3369 } else { 3370 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3371 } 3372 3373 /* Have the IPv4 header w/ no options here */ 3374 pi->ipi_ip_hlen = ip->ip_hl << 2; 3375 pi->ipi_ipproto = ip->ip_p; 3376 pi->ipi_ip_tos = ip->ip_tos; 3377 pi->ipi_flags |= IPI_TX_IPV4; 3378 3379 break; 3380 } 3381 #endif 3382 #ifdef INET6 3383 case ETHERTYPE_IPV6: 3384 { 3385 struct ip6_hdr *ip6; 3386 3387 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3388 (*pullups)++; 3389 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3390 return (ENOMEM); 3391 } 3392 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3393 3394 /* Have the IPv6 fixed header here */ 3395 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3396 pi->ipi_ipproto = ip6->ip6_nxt; 3397 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3398 pi->ipi_flags |= IPI_TX_IPV6; 3399 3400 break; 3401 } 3402 #endif 3403 default: 3404 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3405 pi->ipi_ip_hlen = 0; 3406 break; 3407 } 3408 *mp = m; 3409 3410 return (0); 3411 3412 } 3413 3414 static int 3415 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3416 { 3417 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3418 struct mbuf *m; 3419 int err; 3420 3421 m = *mp; 3422 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3423 M_WRITABLE(m) == 0) { 3424 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3425 return (ENOMEM); 3426 } else { 3427 m_freem(*mp); 3428 DBG_COUNTER_INC(tx_frees); 3429 *mp = m; 3430 } 3431 } 3432 3433 /* Fills out pi->ipi_etype */ 3434 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3435 if (__predict_false(err)) 3436 return (err); 3437 m = *mp; 3438 3439 switch (pi->ipi_etype) { 3440 #ifdef INET 3441 case ETHERTYPE_IP: 3442 { 3443 struct mbuf *n; 3444 struct ip *ip = NULL; 3445 struct tcphdr *th = NULL; 3446 int minthlen; 3447 3448 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3449 if (__predict_false(m->m_len < minthlen)) { 3450 /* 3451 * if this code bloat is causing too much of a hit 3452 * move it to a separate function and mark it noinline 3453 */ 3454 if (m->m_len == pi->ipi_ehdrlen) { 3455 n = m->m_next; 3456 MPASS(n); 3457 if (n->m_len >= sizeof(*ip)) { 3458 ip = (struct ip *)n->m_data; 3459 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3460 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3461 } else { 3462 txq->ift_pullups++; 3463 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3464 return (ENOMEM); 3465 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3466 } 3467 } else { 3468 txq->ift_pullups++; 3469 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3470 return (ENOMEM); 3471 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3472 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3473 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3474 } 3475 } else { 3476 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3477 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3478 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3479 } 3480 pi->ipi_ip_hlen = ip->ip_hl << 2; 3481 pi->ipi_ipproto = ip->ip_p; 3482 pi->ipi_ip_tos = ip->ip_tos; 3483 pi->ipi_flags |= IPI_TX_IPV4; 3484 3485 /* TCP checksum offload may require TCP header length */ 3486 if (IS_TX_OFFLOAD4(pi)) { 3487 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3488 if (__predict_false(th == NULL)) { 3489 txq->ift_pullups++; 3490 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3491 return (ENOMEM); 3492 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3493 } 3494 pi->ipi_tcp_hflags = th->th_flags; 3495 pi->ipi_tcp_hlen = th->th_off << 2; 3496 pi->ipi_tcp_seq = th->th_seq; 3497 } 3498 if (IS_TSO4(pi)) { 3499 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3500 return (ENXIO); 3501 /* 3502 * TSO always requires hardware checksum offload. 3503 */ 3504 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3505 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3506 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3507 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3508 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3509 ip->ip_sum = 0; 3510 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3511 } 3512 } 3513 } 3514 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3515 ip->ip_sum = 0; 3516 3517 break; 3518 } 3519 #endif 3520 #ifdef INET6 3521 case ETHERTYPE_IPV6: 3522 { 3523 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3524 struct tcphdr *th; 3525 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3526 3527 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3528 txq->ift_pullups++; 3529 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3530 return (ENOMEM); 3531 } 3532 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3533 3534 /* XXX-BZ this will go badly in case of ext hdrs. */ 3535 pi->ipi_ipproto = ip6->ip6_nxt; 3536 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3537 pi->ipi_flags |= IPI_TX_IPV6; 3538 3539 /* TCP checksum offload may require TCP header length */ 3540 if (IS_TX_OFFLOAD6(pi)) { 3541 if (pi->ipi_ipproto == IPPROTO_TCP) { 3542 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3543 txq->ift_pullups++; 3544 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3545 return (ENOMEM); 3546 } 3547 pi->ipi_tcp_hflags = th->th_flags; 3548 pi->ipi_tcp_hlen = th->th_off << 2; 3549 pi->ipi_tcp_seq = th->th_seq; 3550 } 3551 if (IS_TSO6(pi)) { 3552 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3553 return (ENXIO); 3554 /* 3555 * TSO always requires hardware checksum offload. 3556 */ 3557 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3558 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3559 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3560 } 3561 } 3562 break; 3563 } 3564 #endif 3565 default: 3566 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3567 pi->ipi_ip_hlen = 0; 3568 break; 3569 } 3570 *mp = m; 3571 3572 return (0); 3573 } 3574 3575 /* 3576 * If dodgy hardware rejects the scatter gather chain we've handed it 3577 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3578 * m_defrag'd mbufs 3579 */ 3580 static __noinline struct mbuf * 3581 iflib_remove_mbuf(iflib_txq_t txq) 3582 { 3583 int ntxd, pidx; 3584 struct mbuf *m, **ifsd_m; 3585 3586 ifsd_m = txq->ift_sds.ifsd_m; 3587 ntxd = txq->ift_size; 3588 pidx = txq->ift_pidx & (ntxd - 1); 3589 ifsd_m = txq->ift_sds.ifsd_m; 3590 m = ifsd_m[pidx]; 3591 ifsd_m[pidx] = NULL; 3592 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3593 if (txq->ift_sds.ifsd_tso_map != NULL) 3594 bus_dmamap_unload(txq->ift_tso_buf_tag, 3595 txq->ift_sds.ifsd_tso_map[pidx]); 3596 #if MEMORY_LOGGING 3597 txq->ift_dequeued++; 3598 #endif 3599 return (m); 3600 } 3601 3602 static inline caddr_t 3603 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3604 { 3605 qidx_t size; 3606 int ntxd; 3607 caddr_t start, end, cur, next; 3608 3609 ntxd = txq->ift_size; 3610 size = txq->ift_txd_size[qid]; 3611 start = txq->ift_ifdi[qid].idi_vaddr; 3612 3613 if (__predict_false(size == 0)) 3614 return (start); 3615 cur = start + size*cidx; 3616 end = start + size*ntxd; 3617 next = CACHE_PTR_NEXT(cur); 3618 return (next < end ? next : start); 3619 } 3620 3621 /* 3622 * Pad an mbuf to ensure a minimum ethernet frame size. 3623 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3624 */ 3625 static __noinline int 3626 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3627 { 3628 /* 3629 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3630 * and ARP message is the smallest common payload I can think of 3631 */ 3632 static char pad[18]; /* just zeros */ 3633 int n; 3634 struct mbuf *new_head; 3635 3636 if (!M_WRITABLE(*m_head)) { 3637 new_head = m_dup(*m_head, M_NOWAIT); 3638 if (new_head == NULL) { 3639 m_freem(*m_head); 3640 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3641 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3642 DBG_COUNTER_INC(tx_frees); 3643 return ENOMEM; 3644 } 3645 m_freem(*m_head); 3646 *m_head = new_head; 3647 } 3648 3649 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3650 n > 0; n -= sizeof(pad)) 3651 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3652 break; 3653 3654 if (n > 0) { 3655 m_freem(*m_head); 3656 device_printf(dev, "cannot pad short frame\n"); 3657 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3658 DBG_COUNTER_INC(tx_frees); 3659 return (ENOBUFS); 3660 } 3661 3662 return 0; 3663 } 3664 3665 static int 3666 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3667 { 3668 if_ctx_t ctx; 3669 if_shared_ctx_t sctx; 3670 if_softc_ctx_t scctx; 3671 bus_dma_tag_t buf_tag; 3672 bus_dma_segment_t *segs; 3673 struct mbuf *m_head, **ifsd_m; 3674 void *next_txd; 3675 bus_dmamap_t map; 3676 struct if_pkt_info pi; 3677 int remap = 0; 3678 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3679 3680 ctx = txq->ift_ctx; 3681 sctx = ctx->ifc_sctx; 3682 scctx = &ctx->ifc_softc_ctx; 3683 segs = txq->ift_segs; 3684 ntxd = txq->ift_size; 3685 m_head = *m_headp; 3686 map = NULL; 3687 3688 /* 3689 * If we're doing TSO the next descriptor to clean may be quite far ahead 3690 */ 3691 cidx = txq->ift_cidx; 3692 pidx = txq->ift_pidx; 3693 if (ctx->ifc_flags & IFC_PREFETCH) { 3694 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3695 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3696 next_txd = calc_next_txd(txq, cidx, 0); 3697 prefetch(next_txd); 3698 } 3699 3700 /* prefetch the next cache line of mbuf pointers and flags */ 3701 prefetch(&txq->ift_sds.ifsd_m[next]); 3702 prefetch(&txq->ift_sds.ifsd_map[next]); 3703 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3704 } 3705 map = txq->ift_sds.ifsd_map[pidx]; 3706 ifsd_m = txq->ift_sds.ifsd_m; 3707 3708 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3709 buf_tag = txq->ift_tso_buf_tag; 3710 max_segs = scctx->isc_tx_tso_segments_max; 3711 map = txq->ift_sds.ifsd_tso_map[pidx]; 3712 MPASS(buf_tag != NULL); 3713 MPASS(max_segs > 0); 3714 } else { 3715 buf_tag = txq->ift_buf_tag; 3716 max_segs = scctx->isc_tx_nsegments; 3717 map = txq->ift_sds.ifsd_map[pidx]; 3718 } 3719 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3720 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3721 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3722 if (err) { 3723 DBG_COUNTER_INC(encap_txd_encap_fail); 3724 return err; 3725 } 3726 } 3727 m_head = *m_headp; 3728 3729 pkt_info_zero(&pi); 3730 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3731 pi.ipi_pidx = pidx; 3732 pi.ipi_qsidx = txq->ift_id; 3733 pi.ipi_len = m_head->m_pkthdr.len; 3734 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3735 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3736 3737 /* deliberate bitwise OR to make one condition */ 3738 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3739 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3740 DBG_COUNTER_INC(encap_txd_encap_fail); 3741 return (err); 3742 } 3743 m_head = *m_headp; 3744 } 3745 3746 retry: 3747 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3748 BUS_DMA_NOWAIT); 3749 defrag: 3750 if (__predict_false(err)) { 3751 switch (err) { 3752 case EFBIG: 3753 /* try collapse once and defrag once */ 3754 if (remap == 0) { 3755 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3756 /* try defrag if collapsing fails */ 3757 if (m_head == NULL) 3758 remap++; 3759 } 3760 if (remap == 1) { 3761 txq->ift_mbuf_defrag++; 3762 m_head = m_defrag(*m_headp, M_NOWAIT); 3763 } 3764 /* 3765 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3766 * failed to map an mbuf that was run through m_defrag 3767 */ 3768 MPASS(remap <= 1); 3769 if (__predict_false(m_head == NULL || remap > 1)) 3770 goto defrag_failed; 3771 remap++; 3772 *m_headp = m_head; 3773 goto retry; 3774 break; 3775 case ENOMEM: 3776 txq->ift_no_tx_dma_setup++; 3777 break; 3778 default: 3779 txq->ift_no_tx_dma_setup++; 3780 m_freem(*m_headp); 3781 DBG_COUNTER_INC(tx_frees); 3782 *m_headp = NULL; 3783 break; 3784 } 3785 txq->ift_map_failed++; 3786 DBG_COUNTER_INC(encap_load_mbuf_fail); 3787 DBG_COUNTER_INC(encap_txd_encap_fail); 3788 return (err); 3789 } 3790 ifsd_m[pidx] = m_head; 3791 /* 3792 * XXX assumes a 1 to 1 relationship between segments and 3793 * descriptors - this does not hold true on all drivers, e.g. 3794 * cxgb 3795 */ 3796 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3797 txq->ift_no_desc_avail++; 3798 bus_dmamap_unload(buf_tag, map); 3799 DBG_COUNTER_INC(encap_txq_avail_fail); 3800 DBG_COUNTER_INC(encap_txd_encap_fail); 3801 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3802 GROUPTASK_ENQUEUE(&txq->ift_task); 3803 return (ENOBUFS); 3804 } 3805 /* 3806 * On Intel cards we can greatly reduce the number of TX interrupts 3807 * we see by only setting report status on every Nth descriptor. 3808 * However, this also means that the driver will need to keep track 3809 * of the descriptors that RS was set on to check them for the DD bit. 3810 */ 3811 txq->ift_rs_pending += nsegs + 1; 3812 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3813 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3814 pi.ipi_flags |= IPI_TX_INTR; 3815 txq->ift_rs_pending = 0; 3816 } 3817 3818 pi.ipi_segs = segs; 3819 pi.ipi_nsegs = nsegs; 3820 3821 MPASS(pidx >= 0 && pidx < txq->ift_size); 3822 #ifdef PKT_DEBUG 3823 print_pkt(&pi); 3824 #endif 3825 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3826 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3827 DBG_COUNTER_INC(tx_encap); 3828 MPASS(pi.ipi_new_pidx < txq->ift_size); 3829 3830 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3831 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3832 ndesc += txq->ift_size; 3833 txq->ift_gen = 1; 3834 } 3835 /* 3836 * drivers can need as many as 3837 * two sentinels 3838 */ 3839 MPASS(ndesc <= pi.ipi_nsegs + 2); 3840 MPASS(pi.ipi_new_pidx != pidx); 3841 MPASS(ndesc > 0); 3842 txq->ift_in_use += ndesc; 3843 txq->ift_db_pending += ndesc; 3844 3845 /* 3846 * We update the last software descriptor again here because there may 3847 * be a sentinel and/or there may be more mbufs than segments 3848 */ 3849 txq->ift_pidx = pi.ipi_new_pidx; 3850 txq->ift_npending += pi.ipi_ndescs; 3851 } else { 3852 *m_headp = m_head = iflib_remove_mbuf(txq); 3853 if (err == EFBIG) { 3854 txq->ift_txd_encap_efbig++; 3855 if (remap < 2) { 3856 remap = 1; 3857 goto defrag; 3858 } 3859 } 3860 goto defrag_failed; 3861 } 3862 /* 3863 * err can't possibly be non-zero here, so we don't neet to test it 3864 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3865 */ 3866 return (err); 3867 3868 defrag_failed: 3869 txq->ift_mbuf_defrag_failed++; 3870 txq->ift_map_failed++; 3871 m_freem(*m_headp); 3872 DBG_COUNTER_INC(tx_frees); 3873 *m_headp = NULL; 3874 DBG_COUNTER_INC(encap_txd_encap_fail); 3875 return (ENOMEM); 3876 } 3877 3878 static void 3879 iflib_tx_desc_free(iflib_txq_t txq, int n) 3880 { 3881 uint32_t qsize, cidx, mask, gen; 3882 struct mbuf *m, **ifsd_m; 3883 bool do_prefetch; 3884 3885 cidx = txq->ift_cidx; 3886 gen = txq->ift_gen; 3887 qsize = txq->ift_size; 3888 mask = qsize-1; 3889 ifsd_m = txq->ift_sds.ifsd_m; 3890 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3891 3892 while (n-- > 0) { 3893 if (do_prefetch) { 3894 prefetch(ifsd_m[(cidx + 3) & mask]); 3895 prefetch(ifsd_m[(cidx + 4) & mask]); 3896 } 3897 if ((m = ifsd_m[cidx]) != NULL) { 3898 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3899 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3900 bus_dmamap_sync(txq->ift_tso_buf_tag, 3901 txq->ift_sds.ifsd_tso_map[cidx], 3902 BUS_DMASYNC_POSTWRITE); 3903 bus_dmamap_unload(txq->ift_tso_buf_tag, 3904 txq->ift_sds.ifsd_tso_map[cidx]); 3905 } else { 3906 bus_dmamap_sync(txq->ift_buf_tag, 3907 txq->ift_sds.ifsd_map[cidx], 3908 BUS_DMASYNC_POSTWRITE); 3909 bus_dmamap_unload(txq->ift_buf_tag, 3910 txq->ift_sds.ifsd_map[cidx]); 3911 } 3912 /* XXX we don't support any drivers that batch packets yet */ 3913 MPASS(m->m_nextpkt == NULL); 3914 m_freem(m); 3915 ifsd_m[cidx] = NULL; 3916 #if MEMORY_LOGGING 3917 txq->ift_dequeued++; 3918 #endif 3919 DBG_COUNTER_INC(tx_frees); 3920 } 3921 if (__predict_false(++cidx == qsize)) { 3922 cidx = 0; 3923 gen = 0; 3924 } 3925 } 3926 txq->ift_cidx = cidx; 3927 txq->ift_gen = gen; 3928 } 3929 3930 static __inline int 3931 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3932 { 3933 int reclaim; 3934 if_ctx_t ctx = txq->ift_ctx; 3935 3936 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3937 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3938 3939 /* 3940 * Need a rate-limiting check so that this isn't called every time 3941 */ 3942 iflib_tx_credits_update(ctx, txq); 3943 reclaim = DESC_RECLAIMABLE(txq); 3944 3945 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3946 #ifdef INVARIANTS 3947 if (iflib_verbose_debug) { 3948 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3949 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3950 reclaim, thresh); 3951 } 3952 #endif 3953 return (0); 3954 } 3955 iflib_tx_desc_free(txq, reclaim); 3956 txq->ift_cleaned += reclaim; 3957 txq->ift_in_use -= reclaim; 3958 3959 return (reclaim); 3960 } 3961 3962 static struct mbuf ** 3963 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3964 { 3965 int next, size; 3966 struct mbuf **items; 3967 3968 size = r->size; 3969 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3970 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3971 3972 prefetch(items[(cidx + offset) & (size-1)]); 3973 if (remaining > 1) { 3974 prefetch2cachelines(&items[next]); 3975 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3976 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3977 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3978 } 3979 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3980 } 3981 3982 static void 3983 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3984 { 3985 3986 ifmp_ring_check_drainage(txq->ift_br, budget); 3987 } 3988 3989 static uint32_t 3990 iflib_txq_can_drain(struct ifmp_ring *r) 3991 { 3992 iflib_txq_t txq = r->cookie; 3993 if_ctx_t ctx = txq->ift_ctx; 3994 3995 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3996 return (1); 3997 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3998 BUS_DMASYNC_POSTREAD); 3999 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 4000 false)); 4001 } 4002 4003 static uint32_t 4004 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4005 { 4006 iflib_txq_t txq = r->cookie; 4007 if_ctx_t ctx = txq->ift_ctx; 4008 if_t ifp = ctx->ifc_ifp; 4009 struct mbuf *m, **mp; 4010 int avail, bytes_sent, skipped, count, err, i; 4011 int mcast_sent, pkt_sent, reclaimed; 4012 bool do_prefetch, rang, ring; 4013 4014 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 4015 !LINK_ACTIVE(ctx))) { 4016 DBG_COUNTER_INC(txq_drain_notready); 4017 return (0); 4018 } 4019 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 4020 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 4021 avail = IDXDIFF(pidx, cidx, r->size); 4022 4023 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 4024 /* 4025 * The driver is unloading so we need to free all pending packets. 4026 */ 4027 DBG_COUNTER_INC(txq_drain_flushing); 4028 for (i = 0; i < avail; i++) { 4029 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 4030 m_freem(r->items[(cidx + i) & (r->size-1)]); 4031 r->items[(cidx + i) & (r->size-1)] = NULL; 4032 } 4033 return (avail); 4034 } 4035 4036 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 4037 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4038 CALLOUT_LOCK(txq); 4039 callout_stop(&txq->ift_timer); 4040 CALLOUT_UNLOCK(txq); 4041 DBG_COUNTER_INC(txq_drain_oactive); 4042 return (0); 4043 } 4044 4045 /* 4046 * If we've reclaimed any packets this queue cannot be hung. 4047 */ 4048 if (reclaimed) 4049 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4050 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 4051 count = MIN(avail, TX_BATCH_SIZE); 4052 #ifdef INVARIANTS 4053 if (iflib_verbose_debug) 4054 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 4055 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 4056 #endif 4057 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 4058 err = 0; 4059 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 4060 int rem = do_prefetch ? count - i : 0; 4061 4062 mp = _ring_peek_one(r, cidx, i, rem); 4063 MPASS(mp != NULL && *mp != NULL); 4064 4065 /* 4066 * Completion interrupts will use the address of the txq 4067 * as a sentinel to enqueue _something_ in order to acquire 4068 * the lock on the mp_ring (there's no direct lock call). 4069 * We obviously whave to check for these sentinel cases 4070 * and skip them. 4071 */ 4072 if (__predict_false(*mp == (struct mbuf *)txq)) { 4073 skipped++; 4074 continue; 4075 } 4076 err = iflib_encap(txq, mp); 4077 if (__predict_false(err)) { 4078 /* no room - bail out */ 4079 if (err == ENOBUFS) 4080 break; 4081 skipped++; 4082 /* we can't send this packet - skip it */ 4083 continue; 4084 } 4085 pkt_sent++; 4086 m = *mp; 4087 DBG_COUNTER_INC(tx_sent); 4088 bytes_sent += m->m_pkthdr.len; 4089 mcast_sent += !!(m->m_flags & M_MCAST); 4090 4091 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4092 break; 4093 ETHER_BPF_MTAP(ifp, m); 4094 rang = iflib_txd_db_check(txq, false); 4095 } 4096 4097 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4098 ring = rang ? false : (iflib_min_tx_latency | err); 4099 iflib_txd_db_check(txq, ring); 4100 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4101 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4102 if (mcast_sent) 4103 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4104 #ifdef INVARIANTS 4105 if (iflib_verbose_debug) 4106 printf("consumed=%d\n", skipped + pkt_sent); 4107 #endif 4108 return (skipped + pkt_sent); 4109 } 4110 4111 static uint32_t 4112 iflib_txq_drain_always(struct ifmp_ring *r) 4113 { 4114 return (1); 4115 } 4116 4117 static uint32_t 4118 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4119 { 4120 int i, avail; 4121 struct mbuf **mp; 4122 iflib_txq_t txq; 4123 4124 txq = r->cookie; 4125 4126 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4127 CALLOUT_LOCK(txq); 4128 callout_stop(&txq->ift_timer); 4129 CALLOUT_UNLOCK(txq); 4130 4131 avail = IDXDIFF(pidx, cidx, r->size); 4132 for (i = 0; i < avail; i++) { 4133 mp = _ring_peek_one(r, cidx, i, avail - i); 4134 if (__predict_false(*mp == (struct mbuf *)txq)) 4135 continue; 4136 m_freem(*mp); 4137 DBG_COUNTER_INC(tx_frees); 4138 } 4139 MPASS(ifmp_ring_is_stalled(r) == 0); 4140 return (avail); 4141 } 4142 4143 static void 4144 iflib_ifmp_purge(iflib_txq_t txq) 4145 { 4146 struct ifmp_ring *r; 4147 4148 r = txq->ift_br; 4149 r->drain = iflib_txq_drain_free; 4150 r->can_drain = iflib_txq_drain_always; 4151 4152 ifmp_ring_check_drainage(r, r->size); 4153 4154 r->drain = iflib_txq_drain; 4155 r->can_drain = iflib_txq_can_drain; 4156 } 4157 4158 static void 4159 _task_fn_tx(void *context) 4160 { 4161 iflib_txq_t txq = context; 4162 if_ctx_t ctx = txq->ift_ctx; 4163 if_t ifp = ctx->ifc_ifp; 4164 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4165 4166 #ifdef IFLIB_DIAGNOSTICS 4167 txq->ift_cpu_exec_count[curcpu]++; 4168 #endif 4169 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4170 return; 4171 #ifdef DEV_NETMAP 4172 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4173 netmap_tx_irq(ifp, txq->ift_id)) 4174 goto skip_ifmp; 4175 #endif 4176 #ifdef ALTQ 4177 if (if_altq_is_enabled(ifp)) 4178 iflib_altq_if_start(ifp); 4179 #endif 4180 if (txq->ift_db_pending) 4181 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4182 else if (!abdicate) 4183 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4184 /* 4185 * When abdicating, we always need to check drainage, not just when we don't enqueue 4186 */ 4187 if (abdicate) 4188 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4189 #ifdef DEV_NETMAP 4190 skip_ifmp: 4191 #endif 4192 if (ctx->ifc_flags & IFC_LEGACY) 4193 IFDI_INTR_ENABLE(ctx); 4194 else 4195 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4196 } 4197 4198 static void 4199 _task_fn_rx(void *context) 4200 { 4201 iflib_rxq_t rxq = context; 4202 if_ctx_t ctx = rxq->ifr_ctx; 4203 uint8_t more; 4204 uint16_t budget; 4205 #ifdef DEV_NETMAP 4206 u_int work = 0; 4207 int nmirq; 4208 #endif 4209 4210 #ifdef IFLIB_DIAGNOSTICS 4211 rxq->ifr_cpu_exec_count[curcpu]++; 4212 #endif 4213 DBG_COUNTER_INC(task_fn_rxs); 4214 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4215 return; 4216 #ifdef DEV_NETMAP 4217 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4218 if (nmirq != NM_IRQ_PASS) { 4219 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4220 goto skip_rxeof; 4221 } 4222 #endif 4223 budget = ctx->ifc_sysctl_rx_budget; 4224 if (budget == 0) 4225 budget = 16; /* XXX */ 4226 more = iflib_rxeof(rxq, budget); 4227 #ifdef DEV_NETMAP 4228 skip_rxeof: 4229 #endif 4230 if ((more & IFLIB_RXEOF_MORE) == 0) { 4231 if (ctx->ifc_flags & IFC_LEGACY) 4232 IFDI_INTR_ENABLE(ctx); 4233 else 4234 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4235 DBG_COUNTER_INC(rx_intr_enables); 4236 } 4237 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4238 return; 4239 4240 if (more & IFLIB_RXEOF_MORE) 4241 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4242 else if (more & IFLIB_RXEOF_EMPTY) 4243 #ifndef __HAIKU__ 4244 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4245 #else 4246 callout_reset(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4247 #endif 4248 } 4249 4250 static void 4251 _task_fn_admin(void *context) 4252 { 4253 if_ctx_t ctx = context; 4254 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4255 iflib_txq_t txq; 4256 int i; 4257 bool oactive, running, do_reset, do_watchdog, in_detach; 4258 4259 STATE_LOCK(ctx); 4260 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4261 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4262 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4263 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4264 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4265 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4266 STATE_UNLOCK(ctx); 4267 4268 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4269 return; 4270 if (in_detach) 4271 return; 4272 4273 CTX_LOCK(ctx); 4274 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4275 CALLOUT_LOCK(txq); 4276 callout_stop(&txq->ift_timer); 4277 CALLOUT_UNLOCK(txq); 4278 } 4279 #ifndef __HAIKU__ 4280 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4281 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4282 #endif 4283 if (do_watchdog) { 4284 ctx->ifc_watchdog_events++; 4285 IFDI_WATCHDOG_RESET(ctx); 4286 } 4287 IFDI_UPDATE_ADMIN_STATUS(ctx); 4288 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4289 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4290 txq->ift_timer.c_cpu); 4291 } 4292 IFDI_LINK_INTR_ENABLE(ctx); 4293 if (do_reset) 4294 iflib_if_init_locked(ctx); 4295 CTX_UNLOCK(ctx); 4296 4297 if (LINK_ACTIVE(ctx) == 0) 4298 return; 4299 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4300 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4301 } 4302 4303 static void 4304 _task_fn_iov(void *context) 4305 { 4306 if_ctx_t ctx = context; 4307 4308 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4309 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4310 return; 4311 4312 CTX_LOCK(ctx); 4313 IFDI_VFLR_HANDLE(ctx); 4314 CTX_UNLOCK(ctx); 4315 } 4316 4317 static int 4318 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4319 { 4320 int err; 4321 if_int_delay_info_t info; 4322 if_ctx_t ctx; 4323 4324 info = (if_int_delay_info_t)arg1; 4325 ctx = info->iidi_ctx; 4326 info->iidi_req = req; 4327 info->iidi_oidp = oidp; 4328 CTX_LOCK(ctx); 4329 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4330 CTX_UNLOCK(ctx); 4331 return (err); 4332 } 4333 4334 /********************************************************************* 4335 * 4336 * IFNET FUNCTIONS 4337 * 4338 **********************************************************************/ 4339 4340 static void 4341 iflib_if_init_locked(if_ctx_t ctx) 4342 { 4343 iflib_stop(ctx); 4344 iflib_init_locked(ctx); 4345 } 4346 4347 static void 4348 iflib_if_init(void *arg) 4349 { 4350 if_ctx_t ctx = arg; 4351 4352 CTX_LOCK(ctx); 4353 iflib_if_init_locked(ctx); 4354 CTX_UNLOCK(ctx); 4355 } 4356 4357 static int 4358 iflib_if_transmit(if_t ifp, struct mbuf *m) 4359 { 4360 if_ctx_t ctx = if_getsoftc(ifp); 4361 iflib_txq_t txq; 4362 int err, qidx; 4363 int abdicate; 4364 4365 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4366 DBG_COUNTER_INC(tx_frees); 4367 m_freem(m); 4368 return (ENETDOWN); 4369 } 4370 4371 MPASS(m->m_nextpkt == NULL); 4372 /* ALTQ-enabled interfaces always use queue 0. */ 4373 qidx = 0; 4374 /* Use driver-supplied queue selection method if it exists */ 4375 if (ctx->isc_txq_select_v2) { 4376 struct if_pkt_info pi; 4377 uint64_t early_pullups = 0; 4378 pkt_info_zero(&pi); 4379 4380 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4381 if (__predict_false(err != 0)) { 4382 /* Assign pullups for bad pkts to default queue */ 4383 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4384 DBG_COUNTER_INC(encap_txd_encap_fail); 4385 return (err); 4386 } 4387 /* Let driver make queueing decision */ 4388 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4389 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4390 } 4391 /* Backwards compatibility w/ simpler queue select */ 4392 else if (ctx->isc_txq_select) 4393 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4394 /* If not, use iflib's standard method */ 4395 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4396 qidx = QIDX(ctx, m); 4397 4398 /* Set TX queue */ 4399 txq = &ctx->ifc_txqs[qidx]; 4400 4401 #ifdef DRIVER_BACKPRESSURE 4402 if (txq->ift_closed) { 4403 while (m != NULL) { 4404 next = m->m_nextpkt; 4405 m->m_nextpkt = NULL; 4406 m_freem(m); 4407 DBG_COUNTER_INC(tx_frees); 4408 m = next; 4409 } 4410 return (ENOBUFS); 4411 } 4412 #endif 4413 #ifdef notyet 4414 qidx = count = 0; 4415 mp = marr; 4416 next = m; 4417 do { 4418 count++; 4419 next = next->m_nextpkt; 4420 } while (next != NULL); 4421 4422 if (count > nitems(marr)) 4423 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4424 /* XXX check nextpkt */ 4425 m_freem(m); 4426 /* XXX simplify for now */ 4427 DBG_COUNTER_INC(tx_frees); 4428 return (ENOBUFS); 4429 } 4430 for (next = m, i = 0; next != NULL; i++) { 4431 mp[i] = next; 4432 next = next->m_nextpkt; 4433 mp[i]->m_nextpkt = NULL; 4434 } 4435 #endif 4436 DBG_COUNTER_INC(tx_seen); 4437 abdicate = ctx->ifc_sysctl_tx_abdicate; 4438 4439 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4440 4441 if (abdicate) 4442 GROUPTASK_ENQUEUE(&txq->ift_task); 4443 if (err) { 4444 if (!abdicate) 4445 GROUPTASK_ENQUEUE(&txq->ift_task); 4446 /* support forthcoming later */ 4447 #ifdef DRIVER_BACKPRESSURE 4448 txq->ift_closed = TRUE; 4449 #endif 4450 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4451 m_freem(m); 4452 DBG_COUNTER_INC(tx_frees); 4453 } 4454 4455 return (err); 4456 } 4457 4458 #ifdef ALTQ 4459 /* 4460 * The overall approach to integrating iflib with ALTQ is to continue to use 4461 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4462 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4463 * is redundant/unnecessary, but doing so minimizes the amount of 4464 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4465 * redundantly queueing to an intermediate mp_ring is swamped by the 4466 * performance limitations inherent in using ALTQ. 4467 * 4468 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4469 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4470 * given interface. If ALTQ is enabled for an interface, then all 4471 * transmitted packets for that interface will be submitted to the ALTQ 4472 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4473 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4474 * update stats that the iflib machinery handles, and which is sensitve to 4475 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4476 * will be installed as the start routine for use by ALTQ facilities that 4477 * need to trigger queue drains on a scheduled basis. 4478 * 4479 */ 4480 static void 4481 iflib_altq_if_start(if_t ifp) 4482 { 4483 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4484 struct mbuf *m; 4485 4486 IFQ_LOCK(ifq); 4487 IFQ_DEQUEUE_NOLOCK(ifq, m); 4488 while (m != NULL) { 4489 iflib_if_transmit(ifp, m); 4490 IFQ_DEQUEUE_NOLOCK(ifq, m); 4491 } 4492 IFQ_UNLOCK(ifq); 4493 } 4494 4495 static int 4496 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4497 { 4498 int err; 4499 4500 if (if_altq_is_enabled(ifp)) { 4501 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4502 if (err == 0) 4503 iflib_altq_if_start(ifp); 4504 } else 4505 err = iflib_if_transmit(ifp, m); 4506 4507 return (err); 4508 } 4509 #endif /* ALTQ */ 4510 4511 static void 4512 iflib_if_qflush(if_t ifp) 4513 { 4514 if_ctx_t ctx = if_getsoftc(ifp); 4515 iflib_txq_t txq = ctx->ifc_txqs; 4516 int i; 4517 4518 STATE_LOCK(ctx); 4519 ctx->ifc_flags |= IFC_QFLUSH; 4520 STATE_UNLOCK(ctx); 4521 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4522 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4523 iflib_txq_check_drain(txq, 0); 4524 STATE_LOCK(ctx); 4525 ctx->ifc_flags &= ~IFC_QFLUSH; 4526 STATE_UNLOCK(ctx); 4527 4528 /* 4529 * When ALTQ is enabled, this will also take care of purging the 4530 * ALTQ queue(s). 4531 */ 4532 #ifdef __HAIKU__ 4533 ifp->if_qflush(ifp); 4534 #else 4535 if_qflush(ifp); 4536 #endif 4537 } 4538 4539 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4540 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4541 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4542 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4543 4544 static int 4545 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4546 { 4547 if_ctx_t ctx = if_getsoftc(ifp); 4548 struct ifreq *ifr = (struct ifreq *)data; 4549 #if defined(INET) || defined(INET6) 4550 struct ifaddr *ifa = (struct ifaddr *)data; 4551 #endif 4552 bool avoid_reset = false; 4553 int err = 0, reinit = 0, bits; 4554 4555 switch (command) { 4556 case SIOCSIFADDR: 4557 #ifdef INET 4558 if (ifa->ifa_addr->sa_family == AF_INET) 4559 avoid_reset = true; 4560 #endif 4561 #ifdef INET6 4562 if (ifa->ifa_addr->sa_family == AF_INET6) 4563 avoid_reset = true; 4564 #endif 4565 /* 4566 ** Calling init results in link renegotiation, 4567 ** so we avoid doing it when possible. 4568 */ 4569 if (avoid_reset) { 4570 if_setflagbits(ifp, IFF_UP,0); 4571 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4572 reinit = 1; 4573 #ifdef INET 4574 if (!(if_getflags(ifp) & IFF_NOARP)) 4575 arp_ifinit(ifp, ifa); 4576 #endif 4577 } else 4578 err = ether_ioctl(ifp, command, data); 4579 break; 4580 case SIOCSIFMTU: 4581 CTX_LOCK(ctx); 4582 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4583 CTX_UNLOCK(ctx); 4584 break; 4585 } 4586 bits = if_getdrvflags(ifp); 4587 /* stop the driver and free any clusters before proceeding */ 4588 iflib_stop(ctx); 4589 4590 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4591 STATE_LOCK(ctx); 4592 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4593 ctx->ifc_flags |= IFC_MULTISEG; 4594 else 4595 ctx->ifc_flags &= ~IFC_MULTISEG; 4596 STATE_UNLOCK(ctx); 4597 err = if_setmtu(ifp, ifr->ifr_mtu); 4598 } 4599 iflib_init_locked(ctx); 4600 STATE_LOCK(ctx); 4601 if_setdrvflags(ifp, bits); 4602 STATE_UNLOCK(ctx); 4603 CTX_UNLOCK(ctx); 4604 break; 4605 case SIOCSIFFLAGS: 4606 CTX_LOCK(ctx); 4607 if (if_getflags(ifp) & IFF_UP) { 4608 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4609 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4610 (IFF_PROMISC | IFF_ALLMULTI)) { 4611 CTX_UNLOCK(ctx); 4612 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4613 CTX_LOCK(ctx); 4614 } 4615 } else 4616 reinit = 1; 4617 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4618 iflib_stop(ctx); 4619 } 4620 ctx->ifc_if_flags = if_getflags(ifp); 4621 CTX_UNLOCK(ctx); 4622 break; 4623 case SIOCADDMULTI: 4624 case SIOCDELMULTI: 4625 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4626 CTX_LOCK(ctx); 4627 IFDI_INTR_DISABLE(ctx); 4628 IFDI_MULTI_SET(ctx); 4629 IFDI_INTR_ENABLE(ctx); 4630 CTX_UNLOCK(ctx); 4631 } 4632 break; 4633 case SIOCSIFMEDIA: 4634 CTX_LOCK(ctx); 4635 IFDI_MEDIA_SET(ctx); 4636 CTX_UNLOCK(ctx); 4637 /* FALLTHROUGH */ 4638 case SIOCGIFMEDIA: 4639 #ifndef __HAIKU__ 4640 case SIOCGIFXMEDIA: 4641 #endif 4642 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4643 break; 4644 #ifndef __HAIKU__ 4645 case SIOCGI2C: 4646 { 4647 struct ifi2creq i2c; 4648 4649 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4650 if (err != 0) 4651 break; 4652 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4653 err = EINVAL; 4654 break; 4655 } 4656 if (i2c.len > sizeof(i2c.data)) { 4657 err = EINVAL; 4658 break; 4659 } 4660 4661 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4662 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4663 sizeof(i2c)); 4664 break; 4665 } 4666 #endif 4667 case SIOCSIFCAP: 4668 { 4669 int mask, setmask, oldmask; 4670 4671 oldmask = if_getcapenable(ifp); 4672 mask = ifr->ifr_reqcap ^ oldmask; 4673 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4674 setmask = 0; 4675 #ifdef TCP_OFFLOAD 4676 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4677 #endif 4678 setmask |= (mask & IFCAP_FLAGS); 4679 setmask |= (mask & IFCAP_WOL); 4680 4681 /* 4682 * If any RX csum has changed, change all the ones that 4683 * are supported by the driver. 4684 */ 4685 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4686 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4687 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4688 } 4689 4690 /* 4691 * want to ensure that traffic has stopped before we change any of the flags 4692 */ 4693 if (setmask) { 4694 CTX_LOCK(ctx); 4695 bits = if_getdrvflags(ifp); 4696 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4697 iflib_stop(ctx); 4698 STATE_LOCK(ctx); 4699 if_togglecapenable(ifp, setmask); 4700 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4701 STATE_UNLOCK(ctx); 4702 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4703 iflib_init_locked(ctx); 4704 STATE_LOCK(ctx); 4705 if_setdrvflags(ifp, bits); 4706 STATE_UNLOCK(ctx); 4707 CTX_UNLOCK(ctx); 4708 } 4709 if_vlancap(ifp); 4710 break; 4711 } 4712 case SIOCGPRIVATE_0: 4713 case SIOCSDRVSPEC: 4714 case SIOCGDRVSPEC: 4715 CTX_LOCK(ctx); 4716 err = IFDI_PRIV_IOCTL(ctx, command, data); 4717 CTX_UNLOCK(ctx); 4718 break; 4719 default: 4720 err = ether_ioctl(ifp, command, data); 4721 break; 4722 } 4723 if (reinit) 4724 iflib_if_init(ctx); 4725 return (err); 4726 } 4727 4728 static uint64_t 4729 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4730 { 4731 if_ctx_t ctx = if_getsoftc(ifp); 4732 4733 return (IFDI_GET_COUNTER(ctx, cnt)); 4734 } 4735 4736 /********************************************************************* 4737 * 4738 * OTHER FUNCTIONS EXPORTED TO THE STACK 4739 * 4740 **********************************************************************/ 4741 4742 static void 4743 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4744 { 4745 if_ctx_t ctx = if_getsoftc(ifp); 4746 4747 if ((void *)ctx != arg) 4748 return; 4749 4750 if ((vtag == 0) || (vtag > 4095)) 4751 return; 4752 4753 if (iflib_in_detach(ctx)) 4754 return; 4755 4756 CTX_LOCK(ctx); 4757 /* Driver may need all untagged packets to be flushed */ 4758 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4759 iflib_stop(ctx); 4760 IFDI_VLAN_REGISTER(ctx, vtag); 4761 /* Re-init to load the changes, if required */ 4762 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4763 iflib_init_locked(ctx); 4764 CTX_UNLOCK(ctx); 4765 } 4766 4767 static void 4768 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4769 { 4770 if_ctx_t ctx = if_getsoftc(ifp); 4771 4772 if ((void *)ctx != arg) 4773 return; 4774 4775 if ((vtag == 0) || (vtag > 4095)) 4776 return; 4777 4778 CTX_LOCK(ctx); 4779 /* Driver may need all tagged packets to be flushed */ 4780 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4781 iflib_stop(ctx); 4782 IFDI_VLAN_UNREGISTER(ctx, vtag); 4783 /* Re-init to load the changes, if required */ 4784 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4785 iflib_init_locked(ctx); 4786 CTX_UNLOCK(ctx); 4787 } 4788 4789 static void 4790 iflib_led_func(void *arg, int onoff) 4791 { 4792 if_ctx_t ctx = arg; 4793 4794 CTX_LOCK(ctx); 4795 IFDI_LED_FUNC(ctx, onoff); 4796 CTX_UNLOCK(ctx); 4797 } 4798 4799 /********************************************************************* 4800 * 4801 * BUS FUNCTION DEFINITIONS 4802 * 4803 **********************************************************************/ 4804 4805 int 4806 iflib_device_probe(device_t dev) 4807 { 4808 const pci_vendor_info_t *ent; 4809 if_shared_ctx_t sctx; 4810 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4811 uint16_t pci_vendor_id; 4812 4813 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4814 return (ENOTSUP); 4815 4816 pci_vendor_id = pci_get_vendor(dev); 4817 pci_device_id = pci_get_device(dev); 4818 pci_subvendor_id = pci_get_subvendor(dev); 4819 pci_subdevice_id = pci_get_subdevice(dev); 4820 pci_rev_id = pci_get_revid(dev); 4821 if (sctx->isc_parse_devinfo != NULL) 4822 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4823 4824 ent = sctx->isc_vendor_info; 4825 while (ent->pvi_vendor_id != 0) { 4826 if (pci_vendor_id != ent->pvi_vendor_id) { 4827 ent++; 4828 continue; 4829 } 4830 if ((pci_device_id == ent->pvi_device_id) && 4831 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4832 (ent->pvi_subvendor_id == 0)) && 4833 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4834 (ent->pvi_subdevice_id == 0)) && 4835 ((pci_rev_id == ent->pvi_rev_id) || 4836 (ent->pvi_rev_id == 0))) { 4837 device_set_desc_copy(dev, ent->pvi_name); 4838 /* this needs to be changed to zero if the bus probing code 4839 * ever stops re-probing on best match because the sctx 4840 * may have its values over written by register calls 4841 * in subsequent probes 4842 */ 4843 return (BUS_PROBE_DEFAULT); 4844 } 4845 ent++; 4846 } 4847 return (ENXIO); 4848 } 4849 4850 int 4851 iflib_device_probe_vendor(device_t dev) 4852 { 4853 int probe; 4854 4855 probe = iflib_device_probe(dev); 4856 #ifndef __HAIKU__ 4857 if (probe == BUS_PROBE_DEFAULT) 4858 return (BUS_PROBE_VENDOR); 4859 else 4860 #endif 4861 return (probe); 4862 } 4863 4864 static void 4865 iflib_reset_qvalues(if_ctx_t ctx) 4866 { 4867 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4868 if_shared_ctx_t sctx = ctx->ifc_sctx; 4869 device_t dev = ctx->ifc_dev; 4870 int i; 4871 4872 if (ctx->ifc_sysctl_ntxqs != 0) 4873 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4874 if (ctx->ifc_sysctl_nrxqs != 0) 4875 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4876 4877 for (i = 0; i < sctx->isc_ntxqs; i++) { 4878 if (ctx->ifc_sysctl_ntxds[i] != 0) 4879 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4880 else 4881 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4882 } 4883 4884 for (i = 0; i < sctx->isc_nrxqs; i++) { 4885 if (ctx->ifc_sysctl_nrxds[i] != 0) 4886 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4887 else 4888 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4889 } 4890 4891 for (i = 0; i < sctx->isc_nrxqs; i++) { 4892 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4893 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4894 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4895 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4896 } 4897 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4898 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4899 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4900 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4901 } 4902 if (!powerof2(scctx->isc_nrxd[i])) { 4903 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4904 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4905 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4906 } 4907 } 4908 4909 for (i = 0; i < sctx->isc_ntxqs; i++) { 4910 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4911 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4912 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4913 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4914 } 4915 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4916 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4917 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4918 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4919 } 4920 if (!powerof2(scctx->isc_ntxd[i])) { 4921 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4922 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4923 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4924 } 4925 } 4926 } 4927 4928 static void 4929 iflib_add_pfil(if_ctx_t ctx) 4930 { 4931 #ifndef __HAIKU__ 4932 struct pfil_head *pfil; 4933 struct pfil_head_args pa; 4934 iflib_rxq_t rxq; 4935 int i; 4936 4937 pa.pa_version = PFIL_VERSION; 4938 pa.pa_flags = PFIL_IN; 4939 pa.pa_type = PFIL_TYPE_ETHERNET; 4940 pa.pa_headname = if_name(ctx->ifc_ifp); 4941 pfil = pfil_head_register(&pa); 4942 4943 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4944 rxq->pfil = pfil; 4945 } 4946 #endif 4947 } 4948 4949 static void 4950 iflib_rem_pfil(if_ctx_t ctx) 4951 { 4952 #ifndef __HAIKU__ 4953 struct pfil_head *pfil; 4954 iflib_rxq_t rxq; 4955 int i; 4956 4957 rxq = ctx->ifc_rxqs; 4958 pfil = rxq->pfil; 4959 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4960 rxq->pfil = NULL; 4961 } 4962 pfil_head_unregister(pfil); 4963 #endif 4964 } 4965 4966 4967 #ifndef __HAIKU__ 4968 /* 4969 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4970 * cpuid and wrapping as necessary. 4971 */ 4972 static unsigned int 4973 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4974 { 4975 unsigned int first_valid; 4976 unsigned int last_valid; 4977 4978 /* cpuid should always be in the valid set */ 4979 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4980 4981 /* valid set should never be empty */ 4982 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4983 4984 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4985 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4986 n = n % CPU_COUNT(&ctx->ifc_cpus); 4987 while (n > 0) { 4988 do { 4989 cpuid++; 4990 if (cpuid > last_valid) 4991 cpuid = first_valid; 4992 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4993 n--; 4994 } 4995 4996 return (cpuid); 4997 } 4998 #endif 4999 5000 #if defined(SMP) && defined(SCHED_ULE) 5001 extern struct cpu_group *cpu_top; /* CPU topology */ 5002 5003 static int 5004 find_child_with_core(int cpu, struct cpu_group *grp) 5005 { 5006 int i; 5007 5008 if (grp->cg_children == 0) 5009 return -1; 5010 5011 MPASS(grp->cg_child); 5012 for (i = 0; i < grp->cg_children; i++) { 5013 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5014 return i; 5015 } 5016 5017 return -1; 5018 } 5019 5020 5021 /* 5022 * Find an L2 neighbor of the given CPU or return -1 if none found. This 5023 * does not distinguish among multiple L2 neighbors if the given CPU has 5024 * more than one (it will always return the same result in that case). 5025 */ 5026 static int 5027 find_l2_neighbor(int cpu) 5028 { 5029 struct cpu_group *grp; 5030 int i; 5031 5032 grp = cpu_top; 5033 if (grp == NULL) 5034 return -1; 5035 5036 /* 5037 * Find the smallest CPU group that contains the given core. 5038 */ 5039 i = 0; 5040 while ((i = find_child_with_core(cpu, grp)) != -1) { 5041 /* 5042 * If the smallest group containing the given CPU has less 5043 * than two members, we conclude the given CPU has no 5044 * L2 neighbor. 5045 */ 5046 if (grp->cg_child[i].cg_count <= 1) 5047 return (-1); 5048 grp = &grp->cg_child[i]; 5049 } 5050 5051 /* Must share L2. */ 5052 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5053 return -1; 5054 5055 /* 5056 * Select the first member of the set that isn't the reference 5057 * CPU, which at this point is guaranteed to exist. 5058 */ 5059 for (i = 0; i < CPU_SETSIZE; i++) { 5060 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 5061 return (i); 5062 } 5063 5064 /* Should never be reached */ 5065 return (-1); 5066 } 5067 5068 #else 5069 static int 5070 find_l2_neighbor(int cpu) 5071 { 5072 5073 return (-1); 5074 } 5075 #endif 5076 5077 #ifndef __HAIKU__ 5078 /* 5079 * CPU mapping behaviors 5080 * --------------------- 5081 * 'separate txrx' refers to the separate_txrx sysctl 5082 * 'use logical' refers to the use_logical_cores sysctl 5083 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 5084 * 5085 * separate use INTR 5086 * txrx logical CPUS result 5087 * ---------- --------- ------ ------------------------------------------------ 5088 * - - X RX and TX queues mapped to consecutive physical 5089 * cores with RX/TX pairs on same core and excess 5090 * of either following 5091 * - X X RX and TX queues mapped to consecutive cores 5092 * of any type with RX/TX pairs on same core and 5093 * excess of either following 5094 * X - X RX and TX queues mapped to consecutive physical 5095 * cores; all RX then all TX 5096 * X X X RX queues mapped to consecutive physical cores 5097 * first, then TX queues mapped to L2 neighbor of 5098 * the corresponding RX queue if one exists, 5099 * otherwise to consecutive physical cores 5100 * - n/a - RX and TX queues mapped to consecutive cores of 5101 * any type with RX/TX pairs on same core and excess 5102 * of either following 5103 * X n/a - RX and TX queues mapped to consecutive cores of 5104 * any type; all RX then all TX 5105 */ 5106 static unsigned int 5107 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5108 bool is_tx) 5109 { 5110 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5111 unsigned int core_index; 5112 5113 if (ctx->ifc_sysctl_separate_txrx) { 5114 /* 5115 * When using separate CPUs for TX and RX, the assignment 5116 * will always be of a consecutive CPU out of the set of 5117 * context CPUs, except for the specific case where the 5118 * context CPUs are phsyical cores, the use of logical cores 5119 * has been enabled, the assignment is for TX, the TX qid 5120 * corresponds to an RX qid, and the CPU assigned to the 5121 * corresponding RX queue has an L2 neighbor. 5122 */ 5123 if (ctx->ifc_sysctl_use_logical_cores && 5124 ctx->ifc_cpus_are_physical_cores && 5125 is_tx && qid < scctx->isc_nrxqsets) { 5126 int l2_neighbor; 5127 unsigned int rx_cpuid; 5128 5129 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5130 l2_neighbor = find_l2_neighbor(rx_cpuid); 5131 if (l2_neighbor != -1) { 5132 return (l2_neighbor); 5133 } 5134 /* 5135 * ... else fall through to the normal 5136 * consecutive-after-RX assignment scheme. 5137 * 5138 * Note that we are assuming that all RX queue CPUs 5139 * have an L2 neighbor, or all do not. If a mixed 5140 * scenario is possible, we will have to keep track 5141 * separately of how many queues prior to this one 5142 * were not able to be assigned to an L2 neighbor. 5143 */ 5144 } 5145 if (is_tx) 5146 core_index = scctx->isc_nrxqsets + qid; 5147 else 5148 core_index = qid; 5149 } else { 5150 core_index = qid; 5151 } 5152 5153 return (cpuid_advance(ctx, base_cpuid, core_index)); 5154 } 5155 #else 5156 #define get_cpuid_for_queue(...) CPU_FIRST() 5157 #endif 5158 5159 static uint16_t 5160 get_ctx_core_offset(if_ctx_t ctx) 5161 { 5162 #ifndef __HAIKU__ 5163 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5164 struct cpu_offset *op; 5165 cpuset_t assigned_cpus; 5166 unsigned int cores_consumed; 5167 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5168 unsigned int first_valid; 5169 unsigned int last_valid; 5170 unsigned int i; 5171 5172 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5173 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5174 5175 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5176 /* 5177 * Align the user-chosen base CPU ID to the next valid CPU 5178 * for this device. If the chosen base CPU ID is smaller 5179 * than the first valid CPU or larger than the last valid 5180 * CPU, we assume the user does not know what the valid 5181 * range is for this device and is thinking in terms of a 5182 * zero-based reference frame, and so we shift the given 5183 * value into the valid range (and wrap accordingly) so the 5184 * intent is translated to the proper frame of reference. 5185 * If the base CPU ID is within the valid first/last, but 5186 * does not correspond to a valid CPU, it is advanced to the 5187 * next valid CPU (wrapping if necessary). 5188 */ 5189 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5190 /* shift from zero-based to first_valid-based */ 5191 base_cpuid += first_valid; 5192 /* wrap to range [first_valid, last_valid] */ 5193 base_cpuid = (base_cpuid - first_valid) % 5194 (last_valid - first_valid + 1); 5195 } 5196 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5197 /* 5198 * base_cpuid is in [first_valid, last_valid], but 5199 * not a member of the valid set. In this case, 5200 * there will always be a member of the valid set 5201 * with a CPU ID that is greater than base_cpuid, 5202 * and we simply advance to it. 5203 */ 5204 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5205 base_cpuid++; 5206 } 5207 return (base_cpuid); 5208 } 5209 5210 /* 5211 * Determine how many cores will be consumed by performing the CPU 5212 * assignments and counting how many of the assigned CPUs correspond 5213 * to CPUs in the set of context CPUs. This is done using the CPU 5214 * ID first_valid as the base CPU ID, as the base CPU must be within 5215 * the set of context CPUs. 5216 * 5217 * Note not all assigned CPUs will be in the set of context CPUs 5218 * when separate CPUs are being allocated to TX and RX queues, 5219 * assignment to logical cores has been enabled, the set of context 5220 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5221 * neighbors of CPUs that RX queues have been mapped to - in this 5222 * case we do only want to count how many CPUs in the set of context 5223 * CPUs have been consumed, as that determines the next CPU in that 5224 * set to start allocating at for the next device for which 5225 * core_offset is not set. 5226 */ 5227 CPU_ZERO(&assigned_cpus); 5228 for (i = 0; i < scctx->isc_ntxqsets; i++) 5229 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5230 &assigned_cpus); 5231 for (i = 0; i < scctx->isc_nrxqsets; i++) 5232 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5233 &assigned_cpus); 5234 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5235 cores_consumed = CPU_COUNT(&assigned_cpus); 5236 5237 mtx_lock(&cpu_offset_mtx); 5238 SLIST_FOREACH(op, &cpu_offsets, entries) { 5239 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5240 base_cpuid = op->next_cpuid; 5241 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5242 cores_consumed); 5243 MPASS(op->refcount < UINT_MAX); 5244 op->refcount++; 5245 break; 5246 } 5247 } 5248 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5249 base_cpuid = first_valid; 5250 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5251 M_NOWAIT | M_ZERO); 5252 if (op == NULL) { 5253 device_printf(ctx->ifc_dev, 5254 "allocation for cpu offset failed.\n"); 5255 } else { 5256 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5257 cores_consumed); 5258 op->refcount = 1; 5259 CPU_COPY(&ctx->ifc_cpus, &op->set); 5260 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5261 } 5262 } 5263 mtx_unlock(&cpu_offset_mtx); 5264 5265 return (base_cpuid); 5266 #else 5267 return 0; 5268 #endif 5269 } 5270 5271 static void 5272 unref_ctx_core_offset(if_ctx_t ctx) 5273 { 5274 #ifndef __HAIKU__ 5275 struct cpu_offset *op, *top; 5276 5277 mtx_lock(&cpu_offset_mtx); 5278 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5279 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5280 MPASS(op->refcount > 0); 5281 op->refcount--; 5282 if (op->refcount == 0) { 5283 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5284 free(op, M_IFLIB); 5285 } 5286 break; 5287 } 5288 } 5289 mtx_unlock(&cpu_offset_mtx); 5290 #endif 5291 } 5292 5293 int 5294 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5295 { 5296 if_ctx_t ctx; 5297 if_t ifp; 5298 if_softc_ctx_t scctx; 5299 kobjop_desc_t kobj_desc; 5300 kobj_method_t *kobj_method; 5301 int err, msix, rid; 5302 int num_txd, num_rxd; 5303 5304 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5305 5306 if (sc == NULL) { 5307 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5308 device_set_softc(dev, ctx); 5309 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5310 } 5311 5312 ctx->ifc_sctx = sctx; 5313 ctx->ifc_dev = dev; 5314 ctx->ifc_softc = sc; 5315 5316 if ((err = iflib_register(ctx)) != 0) { 5317 device_printf(dev, "iflib_register failed %d\n", err); 5318 goto fail_ctx_free; 5319 } 5320 iflib_add_device_sysctl_pre(ctx); 5321 5322 scctx = &ctx->ifc_softc_ctx; 5323 ifp = ctx->ifc_ifp; 5324 5325 iflib_reset_qvalues(ctx); 5326 IFNET_WLOCK(); 5327 CTX_LOCK(ctx); 5328 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5329 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5330 goto fail_unlock; 5331 } 5332 _iflib_pre_assert(scctx); 5333 ctx->ifc_txrx = *scctx->isc_txrx; 5334 5335 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5336 5337 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5338 ctx->ifc_mediap = scctx->isc_media; 5339 5340 #ifdef INVARIANTS 5341 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5342 MPASS(scctx->isc_tx_csum_flags); 5343 #endif 5344 5345 if_setcapabilities(ifp, 5346 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5347 if_setcapenable(ifp, 5348 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5349 5350 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5351 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5352 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5353 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5354 5355 num_txd = iflib_num_tx_descs(ctx); 5356 num_rxd = iflib_num_rx_descs(ctx); 5357 5358 /* XXX change for per-queue sizes */ 5359 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5360 num_txd, num_rxd); 5361 5362 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5363 scctx->isc_tx_nsegments = max(1, num_txd / 5364 MAX_SINGLE_PACKET_FRACTION); 5365 if (scctx->isc_tx_tso_segments_max > num_txd / 5366 MAX_SINGLE_PACKET_FRACTION) 5367 scctx->isc_tx_tso_segments_max = max(1, 5368 num_txd / MAX_SINGLE_PACKET_FRACTION); 5369 5370 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5371 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5372 #ifndef __HAIKU__ 5373 /* 5374 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5375 * but some MACs do. 5376 */ 5377 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5378 IP_MAXPACKET)); 5379 /* 5380 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5381 * into account. In the worst case, each of these calls will 5382 * add another mbuf and, thus, the requirement for another DMA 5383 * segment. So for best performance, it doesn't make sense to 5384 * advertize a maximum of TSO segments that typically will 5385 * require defragmentation in iflib_encap(). 5386 */ 5387 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5388 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5389 #endif 5390 } 5391 if (scctx->isc_rss_table_size == 0) 5392 scctx->isc_rss_table_size = 64; 5393 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5394 5395 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5396 /* XXX format name */ 5397 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5398 NULL, NULL, "admin"); 5399 5400 #ifndef __HAIKU__ 5401 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5402 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5403 device_printf(dev, "Unable to fetch CPU list\n"); 5404 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5405 ctx->ifc_cpus_are_physical_cores = false; 5406 } else 5407 ctx->ifc_cpus_are_physical_cores = true; 5408 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5409 #endif 5410 5411 /* 5412 ** Now set up MSI or MSI-X, should return us the number of supported 5413 ** vectors (will be 1 for a legacy interrupt and MSI). 5414 */ 5415 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5416 msix = scctx->isc_vectors; 5417 } else if (scctx->isc_msix_bar != 0) 5418 /* 5419 * The simple fact that isc_msix_bar is not 0 does not mean we 5420 * we have a good value there that is known to work. 5421 */ 5422 msix = iflib_msix_init(ctx); 5423 else { 5424 scctx->isc_vectors = 1; 5425 scctx->isc_ntxqsets = 1; 5426 scctx->isc_nrxqsets = 1; 5427 scctx->isc_intr = IFLIB_INTR_LEGACY; 5428 msix = 0; 5429 } 5430 /* Get memory for the station queues */ 5431 if ((err = iflib_queues_alloc(ctx))) { 5432 device_printf(dev, "Unable to allocate queue memory\n"); 5433 goto fail_intr_free; 5434 } 5435 5436 if ((err = iflib_qset_structures_setup(ctx))) 5437 goto fail_queues; 5438 5439 /* 5440 * Now that we know how many queues there are, get the core offset. 5441 */ 5442 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5443 5444 if (msix > 1) { 5445 /* 5446 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5447 * aren't the default NULL implementation. 5448 */ 5449 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5450 #ifdef __HAIKU__ 5451 kobj_method = kobj_lookup_method(ctx->ops.cls, NULL, 5452 #else 5453 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5454 #endif 5455 kobj_desc); 5456 if (kobj_method == &kobj_desc->deflt) { 5457 device_printf(dev, 5458 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5459 err = EOPNOTSUPP; 5460 goto fail_queues; 5461 } 5462 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5463 #ifdef __HAIKU__ 5464 kobj_method = kobj_lookup_method(ctx->ops.cls, NULL, 5465 #else 5466 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5467 #endif 5468 kobj_desc); 5469 if (kobj_method == &kobj_desc->deflt) { 5470 device_printf(dev, 5471 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5472 err = EOPNOTSUPP; 5473 goto fail_queues; 5474 } 5475 5476 /* 5477 * Assign the MSI-X vectors. 5478 * Note that the default NULL ifdi_msix_intr_assign method will 5479 * fail here, too. 5480 */ 5481 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5482 if (err != 0) { 5483 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5484 err); 5485 goto fail_queues; 5486 } 5487 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5488 rid = 0; 5489 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5490 MPASS(msix == 1); 5491 rid = 1; 5492 } 5493 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5494 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5495 goto fail_queues; 5496 } 5497 } else { 5498 device_printf(dev, 5499 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5500 err = ENODEV; 5501 goto fail_queues; 5502 } 5503 5504 /* 5505 * It prevents a double-locking panic with iflib_media_status when 5506 * the driver loads. 5507 */ 5508 CTX_UNLOCK(ctx); 5509 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5510 CTX_LOCK(ctx); 5511 5512 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5513 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5514 goto fail_detach; 5515 } 5516 5517 /* 5518 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5519 * This must appear after the call to ether_ifattach() because 5520 * ether_ifattach() sets if_hdrlen to the default value. 5521 */ 5522 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5523 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5524 5525 if ((err = iflib_netmap_attach(ctx))) { 5526 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5527 goto fail_detach; 5528 } 5529 *ctxp = ctx; 5530 5531 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5532 5533 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5534 iflib_add_device_sysctl_post(ctx); 5535 iflib_add_pfil(ctx); 5536 ctx->ifc_flags |= IFC_INIT_DONE; 5537 CTX_UNLOCK(ctx); 5538 IFNET_WUNLOCK(); 5539 5540 return (0); 5541 5542 fail_detach: 5543 ether_ifdetach(ctx->ifc_ifp); 5544 fail_queues: 5545 iflib_tqg_detach(ctx); 5546 iflib_tx_structures_free(ctx); 5547 iflib_rx_structures_free(ctx); 5548 IFDI_DETACH(ctx); 5549 IFDI_QUEUES_FREE(ctx); 5550 fail_intr_free: 5551 iflib_free_intr_mem(ctx); 5552 fail_unlock: 5553 CTX_UNLOCK(ctx); 5554 IFNET_WUNLOCK(); 5555 iflib_deregister(ctx); 5556 fail_ctx_free: 5557 device_set_softc(ctx->ifc_dev, NULL); 5558 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5559 free(ctx->ifc_softc, M_IFLIB); 5560 free(ctx, M_IFLIB); 5561 return (err); 5562 } 5563 5564 int 5565 iflib_device_attach(device_t dev) 5566 { 5567 if_ctx_t ctx; 5568 if_shared_ctx_t sctx; 5569 5570 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5571 return (ENOTSUP); 5572 5573 pci_enable_busmaster(dev); 5574 5575 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5576 } 5577 5578 int 5579 iflib_device_deregister(if_ctx_t ctx) 5580 { 5581 if_t ifp = ctx->ifc_ifp; 5582 device_t dev = ctx->ifc_dev; 5583 5584 /* Make sure VLANS are not using driver */ 5585 if (if_vlantrunkinuse(ifp)) { 5586 device_printf(dev, "Vlan in use, detach first\n"); 5587 return (EBUSY); 5588 } 5589 #ifdef PCI_IOV 5590 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5591 device_printf(dev, "SR-IOV in use; detach first.\n"); 5592 return (EBUSY); 5593 } 5594 #endif 5595 5596 STATE_LOCK(ctx); 5597 ctx->ifc_flags |= IFC_IN_DETACH; 5598 STATE_UNLOCK(ctx); 5599 5600 /* Unregister VLAN handlers before calling iflib_stop() */ 5601 iflib_unregister_vlan_handlers(ctx); 5602 5603 iflib_netmap_detach(ifp); 5604 ether_ifdetach(ifp); 5605 5606 CTX_LOCK(ctx); 5607 iflib_stop(ctx); 5608 CTX_UNLOCK(ctx); 5609 5610 iflib_rem_pfil(ctx); 5611 if (ctx->ifc_led_dev != NULL) 5612 led_destroy(ctx->ifc_led_dev); 5613 5614 iflib_tqg_detach(ctx); 5615 iflib_tx_structures_free(ctx); 5616 iflib_rx_structures_free(ctx); 5617 5618 CTX_LOCK(ctx); 5619 IFDI_DETACH(ctx); 5620 IFDI_QUEUES_FREE(ctx); 5621 CTX_UNLOCK(ctx); 5622 5623 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5624 iflib_free_intr_mem(ctx); 5625 5626 bus_generic_detach(dev); 5627 5628 iflib_deregister(ctx); 5629 5630 device_set_softc(ctx->ifc_dev, NULL); 5631 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5632 free(ctx->ifc_softc, M_IFLIB); 5633 unref_ctx_core_offset(ctx); 5634 free(ctx, M_IFLIB); 5635 return (0); 5636 } 5637 5638 static void 5639 iflib_tqg_detach(if_ctx_t ctx) 5640 { 5641 iflib_txq_t txq; 5642 iflib_rxq_t rxq; 5643 int i; 5644 struct taskqgroup *tqg; 5645 5646 /* XXX drain any dependent tasks */ 5647 tqg = qgroup_if_io_tqg; 5648 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5649 callout_drain(&txq->ift_timer); 5650 #ifdef DEV_NETMAP 5651 callout_drain(&txq->ift_netmap_timer); 5652 #endif /* DEV_NETMAP */ 5653 if (txq->ift_task.gt_uniq != NULL) 5654 taskqgroup_detach(tqg, &txq->ift_task); 5655 } 5656 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5657 if (rxq->ifr_task.gt_uniq != NULL) 5658 taskqgroup_detach(tqg, &rxq->ifr_task); 5659 } 5660 tqg = qgroup_if_config_tqg; 5661 if (ctx->ifc_admin_task.gt_uniq != NULL) 5662 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5663 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5664 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5665 } 5666 5667 static void 5668 iflib_free_intr_mem(if_ctx_t ctx) 5669 { 5670 5671 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5672 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5673 } 5674 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5675 pci_release_msi(ctx->ifc_dev); 5676 } 5677 if (ctx->ifc_msix_mem != NULL) { 5678 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5679 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5680 ctx->ifc_msix_mem = NULL; 5681 } 5682 } 5683 5684 int 5685 iflib_device_detach(device_t dev) 5686 { 5687 if_ctx_t ctx = device_get_softc(dev); 5688 5689 return (iflib_device_deregister(ctx)); 5690 } 5691 5692 int 5693 iflib_device_suspend(device_t dev) 5694 { 5695 if_ctx_t ctx = device_get_softc(dev); 5696 5697 CTX_LOCK(ctx); 5698 IFDI_SUSPEND(ctx); 5699 CTX_UNLOCK(ctx); 5700 5701 return bus_generic_suspend(dev); 5702 } 5703 int 5704 iflib_device_shutdown(device_t dev) 5705 { 5706 if_ctx_t ctx = device_get_softc(dev); 5707 5708 CTX_LOCK(ctx); 5709 IFDI_SHUTDOWN(ctx); 5710 CTX_UNLOCK(ctx); 5711 5712 return bus_generic_suspend(dev); 5713 } 5714 5715 int 5716 iflib_device_resume(device_t dev) 5717 { 5718 if_ctx_t ctx = device_get_softc(dev); 5719 iflib_txq_t txq = ctx->ifc_txqs; 5720 5721 CTX_LOCK(ctx); 5722 IFDI_RESUME(ctx); 5723 iflib_if_init_locked(ctx); 5724 CTX_UNLOCK(ctx); 5725 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5726 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5727 5728 return (bus_generic_resume(dev)); 5729 } 5730 5731 int 5732 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5733 { 5734 int error; 5735 if_ctx_t ctx = device_get_softc(dev); 5736 5737 CTX_LOCK(ctx); 5738 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5739 CTX_UNLOCK(ctx); 5740 5741 return (error); 5742 } 5743 5744 void 5745 iflib_device_iov_uninit(device_t dev) 5746 { 5747 if_ctx_t ctx = device_get_softc(dev); 5748 5749 CTX_LOCK(ctx); 5750 IFDI_IOV_UNINIT(ctx); 5751 CTX_UNLOCK(ctx); 5752 } 5753 5754 int 5755 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5756 { 5757 int error; 5758 if_ctx_t ctx = device_get_softc(dev); 5759 5760 CTX_LOCK(ctx); 5761 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5762 CTX_UNLOCK(ctx); 5763 5764 return (error); 5765 } 5766 5767 /********************************************************************* 5768 * 5769 * MODULE FUNCTION DEFINITIONS 5770 * 5771 **********************************************************************/ 5772 5773 /* 5774 * - Start a fast taskqueue thread for each core 5775 * - Start a taskqueue for control operations 5776 */ 5777 static int 5778 iflib_module_init(void) 5779 { 5780 iflib_timer_default = hz / 2; 5781 return (0); 5782 } 5783 5784 static int 5785 iflib_module_event_handler(module_t mod, int what, void *arg) 5786 { 5787 int err; 5788 5789 switch (what) { 5790 case MOD_LOAD: 5791 if ((err = iflib_module_init()) != 0) 5792 return (err); 5793 break; 5794 case MOD_UNLOAD: 5795 return (EBUSY); 5796 default: 5797 return (EOPNOTSUPP); 5798 } 5799 5800 return (0); 5801 } 5802 5803 /********************************************************************* 5804 * 5805 * PUBLIC FUNCTION DEFINITIONS 5806 * ordered as in iflib.h 5807 * 5808 **********************************************************************/ 5809 5810 static void 5811 _iflib_assert(if_shared_ctx_t sctx) 5812 { 5813 int i; 5814 5815 MPASS(sctx->isc_tx_maxsize); 5816 MPASS(sctx->isc_tx_maxsegsize); 5817 5818 MPASS(sctx->isc_rx_maxsize); 5819 MPASS(sctx->isc_rx_nsegments); 5820 MPASS(sctx->isc_rx_maxsegsize); 5821 5822 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5823 for (i = 0; i < sctx->isc_nrxqs; i++) { 5824 MPASS(sctx->isc_nrxd_min[i]); 5825 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5826 MPASS(sctx->isc_nrxd_max[i]); 5827 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5828 MPASS(sctx->isc_nrxd_default[i]); 5829 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5830 } 5831 5832 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5833 for (i = 0; i < sctx->isc_ntxqs; i++) { 5834 MPASS(sctx->isc_ntxd_min[i]); 5835 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5836 MPASS(sctx->isc_ntxd_max[i]); 5837 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5838 MPASS(sctx->isc_ntxd_default[i]); 5839 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5840 } 5841 } 5842 5843 static void 5844 _iflib_pre_assert(if_softc_ctx_t scctx) 5845 { 5846 5847 MPASS(scctx->isc_txrx->ift_txd_encap); 5848 MPASS(scctx->isc_txrx->ift_txd_flush); 5849 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5850 MPASS(scctx->isc_txrx->ift_rxd_available); 5851 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5852 MPASS(scctx->isc_txrx->ift_rxd_refill); 5853 MPASS(scctx->isc_txrx->ift_rxd_flush); 5854 } 5855 5856 static int 5857 iflib_register(if_ctx_t ctx) 5858 { 5859 if_shared_ctx_t sctx = ctx->ifc_sctx; 5860 driver_t *driver = sctx->isc_driver; 5861 device_t dev = ctx->ifc_dev; 5862 if_t ifp; 5863 5864 _iflib_assert(sctx); 5865 5866 CTX_LOCK_INIT(ctx); 5867 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5868 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5869 if (ifp == NULL) { 5870 device_printf(dev, "can not allocate ifnet structure\n"); 5871 return (ENOMEM); 5872 } 5873 5874 /* 5875 * Initialize our context's device specific methods 5876 */ 5877 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5878 kobj_class_compile((kobj_class_t) driver); 5879 5880 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5881 if_setsoftc(ifp, ctx); 5882 if_setdev(ifp, dev); 5883 if_setinitfn(ifp, iflib_if_init); 5884 if_setioctlfn(ifp, iflib_if_ioctl); 5885 #ifdef ALTQ 5886 if_setstartfn(ifp, iflib_altq_if_start); 5887 if_settransmitfn(ifp, iflib_altq_if_transmit); 5888 if_setsendqready(ifp); 5889 #else 5890 if_settransmitfn(ifp, iflib_if_transmit); 5891 #endif 5892 if_setqflushfn(ifp, iflib_if_qflush); 5893 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5894 ctx->ifc_vlan_attach_event = 5895 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5896 EVENTHANDLER_PRI_FIRST); 5897 ctx->ifc_vlan_detach_event = 5898 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5899 EVENTHANDLER_PRI_FIRST); 5900 5901 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5902 ctx->ifc_mediap = &ctx->ifc_media; 5903 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5904 iflib_media_change, iflib_media_status); 5905 } 5906 return (0); 5907 } 5908 5909 static void 5910 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5911 { 5912 /* Unregister VLAN events */ 5913 if (ctx->ifc_vlan_attach_event != NULL) { 5914 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5915 ctx->ifc_vlan_attach_event = NULL; 5916 } 5917 if (ctx->ifc_vlan_detach_event != NULL) { 5918 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5919 ctx->ifc_vlan_detach_event = NULL; 5920 } 5921 5922 } 5923 5924 static void 5925 iflib_deregister(if_ctx_t ctx) 5926 { 5927 if_t ifp = ctx->ifc_ifp; 5928 5929 /* Remove all media */ 5930 ifmedia_removeall(&ctx->ifc_media); 5931 5932 /* Ensure that VLAN event handlers are unregistered */ 5933 iflib_unregister_vlan_handlers(ctx); 5934 5935 #ifndef __HAIKU__ 5936 /* Release kobject reference */ 5937 kobj_delete((kobj_t) ctx, NULL); 5938 #endif 5939 5940 /* Free the ifnet structure */ 5941 if_free(ifp); 5942 5943 STATE_LOCK_DESTROY(ctx); 5944 5945 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5946 CTX_LOCK_DESTROY(ctx); 5947 } 5948 5949 static int 5950 iflib_queues_alloc(if_ctx_t ctx) 5951 { 5952 if_shared_ctx_t sctx = ctx->ifc_sctx; 5953 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5954 device_t dev = ctx->ifc_dev; 5955 int nrxqsets = scctx->isc_nrxqsets; 5956 int ntxqsets = scctx->isc_ntxqsets; 5957 iflib_txq_t txq; 5958 iflib_rxq_t rxq; 5959 iflib_fl_t fl = NULL; 5960 int i, j, cpu, err, txconf, rxconf; 5961 iflib_dma_info_t ifdip; 5962 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5963 uint32_t *txqsizes = scctx->isc_txqsizes; 5964 uint8_t nrxqs = sctx->isc_nrxqs; 5965 uint8_t ntxqs = sctx->isc_ntxqs; 5966 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5967 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5968 caddr_t *vaddrs; 5969 uint64_t *paddrs; 5970 5971 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5972 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5973 KASSERT(nrxqs >= fl_offset + nfree_lists, 5974 ("there must be at least a rxq for each free list")); 5975 5976 /* Allocate the TX ring struct memory */ 5977 if (!(ctx->ifc_txqs = 5978 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5979 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5980 device_printf(dev, "Unable to allocate TX ring memory\n"); 5981 err = ENOMEM; 5982 goto fail; 5983 } 5984 5985 /* Now allocate the RX */ 5986 if (!(ctx->ifc_rxqs = 5987 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5988 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5989 device_printf(dev, "Unable to allocate RX ring memory\n"); 5990 err = ENOMEM; 5991 goto rx_fail; 5992 } 5993 5994 txq = ctx->ifc_txqs; 5995 rxq = ctx->ifc_rxqs; 5996 5997 /* 5998 * XXX handle allocation failure 5999 */ 6000 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 6001 /* Set up some basics */ 6002 6003 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 6004 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6005 device_printf(dev, 6006 "Unable to allocate TX DMA info memory\n"); 6007 err = ENOMEM; 6008 goto err_tx_desc; 6009 } 6010 txq->ift_ifdi = ifdip; 6011 for (j = 0; j < ntxqs; j++, ifdip++) { 6012 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 6013 device_printf(dev, 6014 "Unable to allocate TX descriptors\n"); 6015 err = ENOMEM; 6016 goto err_tx_desc; 6017 } 6018 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 6019 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 6020 } 6021 txq->ift_ctx = ctx; 6022 txq->ift_id = i; 6023 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 6024 txq->ift_br_offset = 1; 6025 } else { 6026 txq->ift_br_offset = 0; 6027 } 6028 6029 if (iflib_txsd_alloc(txq)) { 6030 device_printf(dev, "Critical Failure setting up TX buffers\n"); 6031 err = ENOMEM; 6032 goto err_tx_desc; 6033 } 6034 6035 /* Initialize the TX lock */ 6036 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6037 device_get_nameunit(dev), txq->ift_id); 6038 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6039 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6040 #ifndef __HAIKU__ 6041 txq->ift_timer.c_cpu = cpu; 6042 #endif 6043 #ifdef DEV_NETMAP 6044 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6045 txq->ift_netmap_timer.c_cpu = cpu; 6046 #endif /* DEV_NETMAP */ 6047 6048 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6049 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6050 if (err) { 6051 /* XXX free any allocated rings */ 6052 device_printf(dev, "Unable to allocate buf_ring\n"); 6053 goto err_tx_desc; 6054 } 6055 } 6056 6057 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6058 /* Set up some basics */ 6059 callout_init(&rxq->ifr_watchdog, 1); 6060 6061 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6062 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6063 device_printf(dev, 6064 "Unable to allocate RX DMA info memory\n"); 6065 err = ENOMEM; 6066 goto err_tx_desc; 6067 } 6068 6069 rxq->ifr_ifdi = ifdip; 6070 /* XXX this needs to be changed if #rx queues != #tx queues */ 6071 rxq->ifr_ntxqirq = 1; 6072 rxq->ifr_txqid[0] = i; 6073 for (j = 0; j < nrxqs; j++, ifdip++) { 6074 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6075 device_printf(dev, 6076 "Unable to allocate RX descriptors\n"); 6077 err = ENOMEM; 6078 goto err_tx_desc; 6079 } 6080 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6081 } 6082 rxq->ifr_ctx = ctx; 6083 rxq->ifr_id = i; 6084 rxq->ifr_fl_offset = fl_offset; 6085 rxq->ifr_nfl = nfree_lists; 6086 if (!(fl = 6087 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6088 device_printf(dev, "Unable to allocate free list memory\n"); 6089 err = ENOMEM; 6090 goto err_tx_desc; 6091 } 6092 rxq->ifr_fl = fl; 6093 for (j = 0; j < nfree_lists; j++) { 6094 fl[j].ifl_rxq = rxq; 6095 fl[j].ifl_id = j; 6096 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6097 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6098 } 6099 /* Allocate receive buffers for the ring */ 6100 if (iflib_rxsd_alloc(rxq)) { 6101 device_printf(dev, 6102 "Critical Failure setting up receive buffers\n"); 6103 err = ENOMEM; 6104 goto err_rx_desc; 6105 } 6106 6107 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6108 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6109 M_WAITOK); 6110 } 6111 6112 /* TXQs */ 6113 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6114 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6115 for (i = 0; i < ntxqsets; i++) { 6116 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6117 6118 for (j = 0; j < ntxqs; j++, di++) { 6119 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6120 paddrs[i*ntxqs + j] = di->idi_paddr; 6121 } 6122 } 6123 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6124 device_printf(ctx->ifc_dev, 6125 "Unable to allocate device TX queue\n"); 6126 iflib_tx_structures_free(ctx); 6127 free(vaddrs, M_IFLIB); 6128 free(paddrs, M_IFLIB); 6129 goto err_rx_desc; 6130 } 6131 free(vaddrs, M_IFLIB); 6132 free(paddrs, M_IFLIB); 6133 6134 /* RXQs */ 6135 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6136 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6137 for (i = 0; i < nrxqsets; i++) { 6138 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6139 6140 for (j = 0; j < nrxqs; j++, di++) { 6141 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6142 paddrs[i*nrxqs + j] = di->idi_paddr; 6143 } 6144 } 6145 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6146 device_printf(ctx->ifc_dev, 6147 "Unable to allocate device RX queue\n"); 6148 iflib_tx_structures_free(ctx); 6149 free(vaddrs, M_IFLIB); 6150 free(paddrs, M_IFLIB); 6151 goto err_rx_desc; 6152 } 6153 free(vaddrs, M_IFLIB); 6154 free(paddrs, M_IFLIB); 6155 6156 return (0); 6157 6158 /* XXX handle allocation failure changes */ 6159 err_rx_desc: 6160 err_tx_desc: 6161 rx_fail: 6162 if (ctx->ifc_rxqs != NULL) 6163 free(ctx->ifc_rxqs, M_IFLIB); 6164 ctx->ifc_rxqs = NULL; 6165 if (ctx->ifc_txqs != NULL) 6166 free(ctx->ifc_txqs, M_IFLIB); 6167 ctx->ifc_txqs = NULL; 6168 fail: 6169 return (err); 6170 } 6171 6172 static int 6173 iflib_tx_structures_setup(if_ctx_t ctx) 6174 { 6175 iflib_txq_t txq = ctx->ifc_txqs; 6176 int i; 6177 6178 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6179 iflib_txq_setup(txq); 6180 6181 return (0); 6182 } 6183 6184 static void 6185 iflib_tx_structures_free(if_ctx_t ctx) 6186 { 6187 iflib_txq_t txq = ctx->ifc_txqs; 6188 if_shared_ctx_t sctx = ctx->ifc_sctx; 6189 int i, j; 6190 6191 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6192 for (j = 0; j < sctx->isc_ntxqs; j++) 6193 iflib_dma_free(&txq->ift_ifdi[j]); 6194 iflib_txq_destroy(txq); 6195 } 6196 free(ctx->ifc_txqs, M_IFLIB); 6197 ctx->ifc_txqs = NULL; 6198 } 6199 6200 /********************************************************************* 6201 * 6202 * Initialize all receive rings. 6203 * 6204 **********************************************************************/ 6205 static int 6206 iflib_rx_structures_setup(if_ctx_t ctx) 6207 { 6208 iflib_rxq_t rxq = ctx->ifc_rxqs; 6209 int q; 6210 #if defined(INET6) || defined(INET) 6211 int err, i; 6212 #endif 6213 6214 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6215 #if defined(INET6) || defined(INET) 6216 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6217 TCP_LRO_ENTRIES, min(1024, 6218 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6219 if (err != 0) { 6220 device_printf(ctx->ifc_dev, 6221 "LRO Initialization failed!\n"); 6222 goto fail; 6223 } 6224 #endif 6225 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6226 } 6227 return (0); 6228 #if defined(INET6) || defined(INET) 6229 fail: 6230 /* 6231 * Free LRO resources allocated so far, we will only handle 6232 * the rings that completed, the failing case will have 6233 * cleaned up for itself. 'q' failed, so its the terminus. 6234 */ 6235 rxq = ctx->ifc_rxqs; 6236 for (i = 0; i < q; ++i, rxq++) { 6237 tcp_lro_free(&rxq->ifr_lc); 6238 } 6239 return (err); 6240 #endif 6241 } 6242 6243 /********************************************************************* 6244 * 6245 * Free all receive rings. 6246 * 6247 **********************************************************************/ 6248 static void 6249 iflib_rx_structures_free(if_ctx_t ctx) 6250 { 6251 iflib_rxq_t rxq = ctx->ifc_rxqs; 6252 if_shared_ctx_t sctx = ctx->ifc_sctx; 6253 int i, j; 6254 6255 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6256 for (j = 0; j < sctx->isc_nrxqs; j++) 6257 iflib_dma_free(&rxq->ifr_ifdi[j]); 6258 iflib_rx_sds_free(rxq); 6259 #if defined(INET6) || defined(INET) 6260 tcp_lro_free(&rxq->ifr_lc); 6261 #endif 6262 } 6263 free(ctx->ifc_rxqs, M_IFLIB); 6264 ctx->ifc_rxqs = NULL; 6265 } 6266 6267 static int 6268 iflib_qset_structures_setup(if_ctx_t ctx) 6269 { 6270 int err; 6271 6272 /* 6273 * It is expected that the caller takes care of freeing queues if this 6274 * fails. 6275 */ 6276 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6277 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6278 return (err); 6279 } 6280 6281 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6282 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6283 6284 return (err); 6285 } 6286 6287 int 6288 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6289 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6290 { 6291 6292 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6293 } 6294 6295 /* Just to avoid copy/paste */ 6296 static inline int 6297 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6298 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6299 const char *name) 6300 { 6301 device_t dev; 6302 unsigned int base_cpuid, cpuid; 6303 int err; 6304 6305 dev = ctx->ifc_dev; 6306 base_cpuid = ctx->ifc_sysctl_core_offset; 6307 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6308 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6309 irq ? irq->ii_res : NULL, name); 6310 if (err) { 6311 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6312 return (err); 6313 } 6314 #ifdef notyet 6315 if (cpuid > ctx->ifc_cpuid_highest) 6316 ctx->ifc_cpuid_highest = cpuid; 6317 #endif 6318 return (0); 6319 } 6320 6321 /* 6322 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6323 * resources. 6324 * 6325 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6326 * only. 6327 * 6328 * XXX: Could be removed if subctx's dev has its intr resource allocation 6329 * methods replaced with custom ones? 6330 */ 6331 int 6332 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6333 int rid, iflib_intr_type_t type, 6334 driver_filter_t *filter, void *filter_arg, 6335 int qid, const char *name) 6336 { 6337 device_t dev, subdev; 6338 struct grouptask *gtask; 6339 struct taskqgroup *tqg; 6340 iflib_filter_info_t info; 6341 gtask_fn_t *fn; 6342 int tqrid, err; 6343 driver_filter_t *intr_fast; 6344 void *q; 6345 6346 MPASS(ctx != NULL); 6347 MPASS(subctx != NULL); 6348 6349 tqrid = rid; 6350 dev = ctx->ifc_dev; 6351 subdev = subctx->ifc_dev; 6352 6353 switch (type) { 6354 case IFLIB_INTR_RXTX: 6355 q = &subctx->ifc_rxqs[qid]; 6356 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6357 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6358 tqg = qgroup_if_io_tqg; 6359 fn = _task_fn_rx; 6360 intr_fast = iflib_fast_intr_rxtx; 6361 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6362 break; 6363 default: 6364 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6365 __func__, device_get_nameunit(subdev), type); 6366 return (EINVAL); 6367 } 6368 6369 info->ifi_filter = filter; 6370 info->ifi_filter_arg = filter_arg; 6371 info->ifi_task = gtask; 6372 info->ifi_ctx = q; 6373 6374 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6375 6376 /* Allocate interrupts from hardware using parent context */ 6377 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6378 if (err != 0) { 6379 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6380 device_get_nameunit(subdev), err); 6381 return (err); 6382 } 6383 6384 if (tqrid != -1) { 6385 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6386 name); 6387 if (err) 6388 return (err); 6389 } else { 6390 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6391 } 6392 6393 return (0); 6394 } 6395 6396 int 6397 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6398 iflib_intr_type_t type, driver_filter_t *filter, 6399 void *filter_arg, int qid, const char *name) 6400 { 6401 device_t dev; 6402 struct grouptask *gtask; 6403 struct taskqgroup *tqg; 6404 iflib_filter_info_t info; 6405 gtask_fn_t *fn; 6406 int tqrid, err; 6407 driver_filter_t *intr_fast; 6408 void *q; 6409 6410 info = &ctx->ifc_filter_info; 6411 tqrid = rid; 6412 6413 switch (type) { 6414 /* XXX merge tx/rx for netmap? */ 6415 case IFLIB_INTR_TX: 6416 q = &ctx->ifc_txqs[qid]; 6417 info = &ctx->ifc_txqs[qid].ift_filter_info; 6418 gtask = &ctx->ifc_txqs[qid].ift_task; 6419 tqg = qgroup_if_io_tqg; 6420 fn = _task_fn_tx; 6421 intr_fast = iflib_fast_intr; 6422 GROUPTASK_INIT(gtask, 0, fn, q); 6423 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6424 break; 6425 case IFLIB_INTR_RX: 6426 q = &ctx->ifc_rxqs[qid]; 6427 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6428 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6429 tqg = qgroup_if_io_tqg; 6430 fn = _task_fn_rx; 6431 intr_fast = iflib_fast_intr; 6432 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6433 break; 6434 case IFLIB_INTR_RXTX: 6435 q = &ctx->ifc_rxqs[qid]; 6436 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6437 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6438 tqg = qgroup_if_io_tqg; 6439 fn = _task_fn_rx; 6440 intr_fast = iflib_fast_intr_rxtx; 6441 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6442 break; 6443 case IFLIB_INTR_ADMIN: 6444 q = ctx; 6445 tqrid = -1; 6446 info = &ctx->ifc_filter_info; 6447 gtask = &ctx->ifc_admin_task; 6448 tqg = qgroup_if_config_tqg; 6449 fn = _task_fn_admin; 6450 intr_fast = iflib_fast_intr_ctx; 6451 break; 6452 default: 6453 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6454 __func__); 6455 return (EINVAL); 6456 } 6457 6458 info->ifi_filter = filter; 6459 info->ifi_filter_arg = filter_arg; 6460 info->ifi_task = gtask; 6461 info->ifi_ctx = q; 6462 6463 dev = ctx->ifc_dev; 6464 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6465 if (err != 0) { 6466 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6467 return (err); 6468 } 6469 if (type == IFLIB_INTR_ADMIN) 6470 return (0); 6471 6472 if (tqrid != -1) { 6473 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6474 name); 6475 if (err) 6476 return (err); 6477 } else { 6478 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6479 } 6480 6481 return (0); 6482 } 6483 6484 void 6485 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6486 void *arg, int qid, const char *name) 6487 { 6488 device_t dev; 6489 struct grouptask *gtask; 6490 struct taskqgroup *tqg; 6491 gtask_fn_t *fn; 6492 void *q; 6493 int err; 6494 6495 switch (type) { 6496 case IFLIB_INTR_TX: 6497 q = &ctx->ifc_txqs[qid]; 6498 gtask = &ctx->ifc_txqs[qid].ift_task; 6499 tqg = qgroup_if_io_tqg; 6500 fn = _task_fn_tx; 6501 GROUPTASK_INIT(gtask, 0, fn, q); 6502 break; 6503 case IFLIB_INTR_RX: 6504 q = &ctx->ifc_rxqs[qid]; 6505 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6506 tqg = qgroup_if_io_tqg; 6507 fn = _task_fn_rx; 6508 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6509 break; 6510 case IFLIB_INTR_IOV: 6511 q = ctx; 6512 gtask = &ctx->ifc_vflr_task; 6513 tqg = qgroup_if_config_tqg; 6514 fn = _task_fn_iov; 6515 GROUPTASK_INIT(gtask, 0, fn, q); 6516 break; 6517 default: 6518 panic("unknown net intr type"); 6519 } 6520 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6521 if (err) { 6522 dev = ctx->ifc_dev; 6523 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6524 name); 6525 } 6526 } 6527 6528 void 6529 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6530 { 6531 #ifdef __HAIKU__ 6532 if (!ctx || !irq) 6533 return; 6534 #endif 6535 6536 if (irq->ii_tag) 6537 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6538 6539 if (irq->ii_res) 6540 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6541 rman_get_rid(irq->ii_res), irq->ii_res); 6542 } 6543 6544 static int 6545 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6546 { 6547 iflib_txq_t txq = ctx->ifc_txqs; 6548 iflib_rxq_t rxq = ctx->ifc_rxqs; 6549 if_irq_t irq = &ctx->ifc_legacy_irq; 6550 iflib_filter_info_t info; 6551 device_t dev; 6552 struct grouptask *gtask; 6553 struct resource *res; 6554 struct taskqgroup *tqg; 6555 void *q; 6556 int err, tqrid; 6557 bool rx_only; 6558 6559 q = &ctx->ifc_rxqs[0]; 6560 info = &rxq[0].ifr_filter_info; 6561 gtask = &rxq[0].ifr_task; 6562 tqg = qgroup_if_io_tqg; 6563 tqrid = *rid; 6564 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6565 6566 ctx->ifc_flags |= IFC_LEGACY; 6567 info->ifi_filter = filter; 6568 info->ifi_filter_arg = filter_arg; 6569 info->ifi_task = gtask; 6570 info->ifi_ctx = rx_only ? ctx : q; 6571 6572 dev = ctx->ifc_dev; 6573 /* We allocate a single interrupt resource */ 6574 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6575 iflib_fast_intr_rxtx, NULL, info, name); 6576 if (err != 0) 6577 return (err); 6578 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6579 res = irq->ii_res; 6580 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6581 6582 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6583 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6584 "tx"); 6585 return (0); 6586 } 6587 6588 void 6589 iflib_led_create(if_ctx_t ctx) 6590 { 6591 6592 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6593 device_get_nameunit(ctx->ifc_dev)); 6594 } 6595 6596 void 6597 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6598 { 6599 6600 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6601 } 6602 6603 void 6604 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6605 { 6606 6607 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6608 } 6609 6610 void 6611 iflib_admin_intr_deferred(if_ctx_t ctx) 6612 { 6613 6614 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6615 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6616 } 6617 6618 void 6619 iflib_iov_intr_deferred(if_ctx_t ctx) 6620 { 6621 6622 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6623 } 6624 6625 void 6626 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6627 { 6628 6629 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6630 name); 6631 } 6632 6633 void 6634 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6635 const char *name) 6636 { 6637 6638 GROUPTASK_INIT(gtask, 0, fn, ctx); 6639 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6640 name); 6641 } 6642 6643 void 6644 iflib_config_gtask_deinit(struct grouptask *gtask) 6645 { 6646 6647 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6648 } 6649 6650 void 6651 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6652 { 6653 if_t ifp = ctx->ifc_ifp; 6654 iflib_txq_t txq = ctx->ifc_txqs; 6655 6656 if_setbaudrate(ifp, baudrate); 6657 if (baudrate >= IF_Gbps(10)) { 6658 STATE_LOCK(ctx); 6659 ctx->ifc_flags |= IFC_PREFETCH; 6660 STATE_UNLOCK(ctx); 6661 } 6662 /* If link down, disable watchdog */ 6663 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6664 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6665 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6666 } 6667 ctx->ifc_link_state = link_state; 6668 if_link_state_change(ifp, link_state); 6669 } 6670 6671 static int 6672 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6673 { 6674 int credits; 6675 #ifdef INVARIANTS 6676 int credits_pre = txq->ift_cidx_processed; 6677 #endif 6678 6679 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6680 BUS_DMASYNC_POSTREAD); 6681 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6682 return (0); 6683 6684 txq->ift_processed += credits; 6685 txq->ift_cidx_processed += credits; 6686 6687 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6688 if (txq->ift_cidx_processed >= txq->ift_size) 6689 txq->ift_cidx_processed -= txq->ift_size; 6690 return (credits); 6691 } 6692 6693 static int 6694 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6695 { 6696 iflib_fl_t fl; 6697 u_int i; 6698 6699 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6700 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6701 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6702 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6703 budget)); 6704 } 6705 6706 void 6707 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6708 const char *description, if_int_delay_info_t info, 6709 int offset, int value) 6710 { 6711 info->iidi_ctx = ctx; 6712 info->iidi_offset = offset; 6713 info->iidi_value = value; 6714 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6715 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6716 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6717 info, 0, iflib_sysctl_int_delay, "I", description); 6718 } 6719 6720 struct sx * 6721 iflib_ctx_lock_get(if_ctx_t ctx) 6722 { 6723 6724 return (&ctx->ifc_ctx_sx); 6725 } 6726 6727 static int 6728 iflib_msix_init(if_ctx_t ctx) 6729 { 6730 device_t dev = ctx->ifc_dev; 6731 if_shared_ctx_t sctx = ctx->ifc_sctx; 6732 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6733 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6734 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6735 6736 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6737 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6738 6739 if (bootverbose) 6740 device_printf(dev, "msix_init qsets capped at %d\n", 6741 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6742 6743 /* Override by tuneable */ 6744 if (scctx->isc_disable_msix) 6745 goto msi; 6746 6747 /* First try MSI-X */ 6748 if ((msgs = pci_msix_count(dev)) == 0) { 6749 if (bootverbose) 6750 device_printf(dev, "MSI-X not supported or disabled\n"); 6751 goto msi; 6752 } 6753 6754 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6755 /* 6756 * bar == -1 => "trust me I know what I'm doing" 6757 * Some drivers are for hardware that is so shoddily 6758 * documented that no one knows which bars are which 6759 * so the developer has to map all bars. This hack 6760 * allows shoddy garbage to use MSI-X in this framework. 6761 */ 6762 if (bar != -1) { 6763 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6764 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6765 if (ctx->ifc_msix_mem == NULL) { 6766 device_printf(dev, "Unable to map MSI-X table\n"); 6767 goto msi; 6768 } 6769 } 6770 6771 admincnt = sctx->isc_admin_intrcnt; 6772 #if IFLIB_DEBUG 6773 /* use only 1 qset in debug mode */ 6774 queuemsgs = min(msgs - admincnt, 1); 6775 #else 6776 queuemsgs = msgs - admincnt; 6777 #endif 6778 #ifdef RSS 6779 queues = imin(queuemsgs, rss_getnumbuckets()); 6780 #else 6781 queues = queuemsgs; 6782 #endif 6783 #ifndef __HAIKU__ 6784 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6785 if (bootverbose) 6786 device_printf(dev, 6787 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6788 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6789 #endif 6790 #ifdef RSS 6791 /* If we're doing RSS, clamp at the number of RSS buckets */ 6792 if (queues > rss_getnumbuckets()) 6793 queues = rss_getnumbuckets(); 6794 #endif 6795 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6796 rx_queues = iflib_num_rx_queues; 6797 else 6798 rx_queues = queues; 6799 6800 if (rx_queues > scctx->isc_nrxqsets) 6801 rx_queues = scctx->isc_nrxqsets; 6802 6803 /* 6804 * We want this to be all logical CPUs by default 6805 */ 6806 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6807 tx_queues = iflib_num_tx_queues; 6808 else 6809 tx_queues = mp_ncpus; 6810 6811 if (tx_queues > scctx->isc_ntxqsets) 6812 tx_queues = scctx->isc_ntxqsets; 6813 6814 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6815 #ifdef INVARIANTS 6816 if (tx_queues != rx_queues) 6817 device_printf(dev, 6818 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6819 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6820 #endif 6821 tx_queues = min(rx_queues, tx_queues); 6822 rx_queues = min(rx_queues, tx_queues); 6823 } 6824 6825 vectors = rx_queues + admincnt; 6826 if (msgs < vectors) { 6827 device_printf(dev, 6828 "insufficient number of MSI-X vectors " 6829 "(supported %d, need %d)\n", msgs, vectors); 6830 goto msi; 6831 } 6832 6833 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6834 tx_queues); 6835 msgs = vectors; 6836 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6837 if (vectors != msgs) { 6838 device_printf(dev, 6839 "Unable to allocate sufficient MSI-X vectors " 6840 "(got %d, need %d)\n", vectors, msgs); 6841 pci_release_msi(dev); 6842 if (bar != -1) { 6843 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6844 ctx->ifc_msix_mem); 6845 ctx->ifc_msix_mem = NULL; 6846 } 6847 goto msi; 6848 } 6849 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6850 vectors); 6851 scctx->isc_vectors = vectors; 6852 scctx->isc_nrxqsets = rx_queues; 6853 scctx->isc_ntxqsets = tx_queues; 6854 scctx->isc_intr = IFLIB_INTR_MSIX; 6855 6856 return (vectors); 6857 } else { 6858 device_printf(dev, 6859 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6860 err); 6861 if (bar != -1) { 6862 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6863 ctx->ifc_msix_mem); 6864 ctx->ifc_msix_mem = NULL; 6865 } 6866 } 6867 6868 msi: 6869 vectors = pci_msi_count(dev); 6870 scctx->isc_nrxqsets = 1; 6871 scctx->isc_ntxqsets = 1; 6872 scctx->isc_vectors = vectors; 6873 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6874 device_printf(dev,"Using an MSI interrupt\n"); 6875 scctx->isc_intr = IFLIB_INTR_MSI; 6876 } else { 6877 scctx->isc_vectors = 1; 6878 device_printf(dev,"Using a Legacy interrupt\n"); 6879 scctx->isc_intr = IFLIB_INTR_LEGACY; 6880 } 6881 6882 return (vectors); 6883 } 6884 6885 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6886 6887 #ifndef __HAIKU__ 6888 static int 6889 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6890 { 6891 int rc; 6892 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6893 struct sbuf *sb; 6894 const char *ring_state = "UNKNOWN"; 6895 6896 /* XXX needed ? */ 6897 rc = sysctl_wire_old_buffer(req, 0); 6898 MPASS(rc == 0); 6899 if (rc != 0) 6900 return (rc); 6901 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6902 MPASS(sb != NULL); 6903 if (sb == NULL) 6904 return (ENOMEM); 6905 if (state[3] <= 3) 6906 ring_state = ring_states[state[3]]; 6907 6908 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6909 state[0], state[1], state[2], ring_state); 6910 rc = sbuf_finish(sb); 6911 sbuf_delete(sb); 6912 return(rc); 6913 } 6914 #endif 6915 6916 enum iflib_ndesc_handler { 6917 IFLIB_NTXD_HANDLER, 6918 IFLIB_NRXD_HANDLER, 6919 }; 6920 6921 static int 6922 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6923 { 6924 if_ctx_t ctx = (void *)arg1; 6925 enum iflib_ndesc_handler type = arg2; 6926 char buf[256] = {0}; 6927 qidx_t *ndesc; 6928 char *p, *next; 6929 int nqs, rc, i; 6930 6931 nqs = 8; 6932 switch(type) { 6933 case IFLIB_NTXD_HANDLER: 6934 ndesc = ctx->ifc_sysctl_ntxds; 6935 if (ctx->ifc_sctx) 6936 nqs = ctx->ifc_sctx->isc_ntxqs; 6937 break; 6938 case IFLIB_NRXD_HANDLER: 6939 ndesc = ctx->ifc_sysctl_nrxds; 6940 if (ctx->ifc_sctx) 6941 nqs = ctx->ifc_sctx->isc_nrxqs; 6942 break; 6943 default: 6944 printf("%s: unhandled type\n", __func__); 6945 return (EINVAL); 6946 } 6947 if (nqs == 0) 6948 nqs = 8; 6949 6950 for (i=0; i<8; i++) { 6951 if (i >= nqs) 6952 break; 6953 if (i) 6954 strcat(buf, ","); 6955 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6956 } 6957 6958 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6959 if (rc || req->newptr == NULL) 6960 return rc; 6961 6962 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6963 i++, p = strsep(&next, " ,")) { 6964 ndesc[i] = strtoul(p, NULL, 10); 6965 } 6966 6967 return(rc); 6968 } 6969 6970 #define NAME_BUFLEN 32 6971 static void 6972 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6973 { 6974 #ifndef __HAIKU__ 6975 device_t dev = iflib_get_dev(ctx); 6976 struct sysctl_oid_list *child, *oid_list; 6977 struct sysctl_ctx_list *ctx_list; 6978 struct sysctl_oid *node; 6979 6980 ctx_list = device_get_sysctl_ctx(dev); 6981 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6982 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6983 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6984 oid_list = SYSCTL_CHILDREN(node); 6985 6986 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6987 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6988 "driver version"); 6989 6990 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6991 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6992 "# of txqs to use, 0 => use default #"); 6993 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6994 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6995 "# of rxqs to use, 0 => use default #"); 6996 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6997 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6998 "permit #txq != #rxq"); 6999 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 7000 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 7001 "disable MSI-X (default 0)"); 7002 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 7003 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 7004 "set the RX budget"); 7005 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 7006 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 7007 "cause TX to abdicate instead of running to completion"); 7008 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 7009 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 7010 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 7011 "offset to start using cores at"); 7012 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 7013 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 7014 "use separate cores for TX and RX"); 7015 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 7016 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 7017 "try to make use of logical cores for TX and RX"); 7018 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "use_extra_msix_vectors", 7019 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 7020 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 7021 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "allocated_msix_vectors", 7022 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 7023 "total # of MSI-X vectors allocated by driver"); 7024 7025 /* XXX change for per-queue sizes */ 7026 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 7027 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7028 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 7029 "list of # of TX descriptors to use, 0 = use default #"); 7030 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 7031 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7032 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 7033 "list of # of RX descriptors to use, 0 = use default #"); 7034 #endif 7035 } 7036 7037 static void 7038 iflib_add_device_sysctl_post(if_ctx_t ctx) 7039 { 7040 #ifndef __HAIKU__ 7041 if_shared_ctx_t sctx = ctx->ifc_sctx; 7042 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7043 device_t dev = iflib_get_dev(ctx); 7044 struct sysctl_oid_list *child; 7045 struct sysctl_ctx_list *ctx_list; 7046 iflib_fl_t fl; 7047 iflib_txq_t txq; 7048 iflib_rxq_t rxq; 7049 int i, j; 7050 char namebuf[NAME_BUFLEN]; 7051 char *qfmt; 7052 struct sysctl_oid *queue_node, *fl_node, *node; 7053 struct sysctl_oid_list *queue_list, *fl_list; 7054 ctx_list = device_get_sysctl_ctx(dev); 7055 7056 node = ctx->ifc_sysctl_node; 7057 child = SYSCTL_CHILDREN(node); 7058 7059 if (scctx->isc_ntxqsets > 100) 7060 qfmt = "txq%03d"; 7061 else if (scctx->isc_ntxqsets > 10) 7062 qfmt = "txq%02d"; 7063 else 7064 qfmt = "txq%d"; 7065 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 7066 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7067 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7068 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7069 queue_list = SYSCTL_CHILDREN(queue_node); 7070 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7071 CTLFLAG_RD, 7072 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 7073 #if MEMORY_LOGGING 7074 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 7075 CTLFLAG_RD, 7076 &txq->ift_dequeued, "total mbufs freed"); 7077 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 7078 CTLFLAG_RD, 7079 &txq->ift_enqueued, "total mbufs enqueued"); 7080 #endif 7081 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 7082 CTLFLAG_RD, 7083 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 7084 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 7085 CTLFLAG_RD, 7086 &txq->ift_pullups, "# of times m_pullup was called"); 7087 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 7088 CTLFLAG_RD, 7089 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 7090 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 7091 CTLFLAG_RD, 7092 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 7093 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 7094 CTLFLAG_RD, 7095 &txq->ift_map_failed, "# of times DMA map failed"); 7096 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 7097 CTLFLAG_RD, 7098 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 7099 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 7100 CTLFLAG_RD, 7101 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 7102 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 7103 CTLFLAG_RD, 7104 &txq->ift_pidx, 1, "Producer Index"); 7105 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 7106 CTLFLAG_RD, 7107 &txq->ift_cidx, 1, "Consumer Index"); 7108 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 7109 CTLFLAG_RD, 7110 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 7111 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 7112 CTLFLAG_RD, 7113 &txq->ift_in_use, 1, "descriptors in use"); 7114 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 7115 CTLFLAG_RD, 7116 &txq->ift_processed, "descriptors procesed for clean"); 7117 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 7118 CTLFLAG_RD, 7119 &txq->ift_cleaned, "total cleaned"); 7120 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 7121 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7122 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7123 mp_ring_state_handler, "A", "soft ring state"); 7124 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 7125 CTLFLAG_RD, &txq->ift_br->enqueues, 7126 "# of enqueues to the mp_ring for this queue"); 7127 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 7128 CTLFLAG_RD, &txq->ift_br->drops, 7129 "# of drops in the mp_ring for this queue"); 7130 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 7131 CTLFLAG_RD, &txq->ift_br->starts, 7132 "# of normal consumer starts in the mp_ring for this queue"); 7133 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 7134 CTLFLAG_RD, &txq->ift_br->stalls, 7135 "# of consumer stalls in the mp_ring for this queue"); 7136 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 7137 CTLFLAG_RD, &txq->ift_br->restarts, 7138 "# of consumer restarts in the mp_ring for this queue"); 7139 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 7140 CTLFLAG_RD, &txq->ift_br->abdications, 7141 "# of consumer abdications in the mp_ring for this queue"); 7142 } 7143 7144 if (scctx->isc_nrxqsets > 100) 7145 qfmt = "rxq%03d"; 7146 else if (scctx->isc_nrxqsets > 10) 7147 qfmt = "rxq%02d"; 7148 else 7149 qfmt = "rxq%d"; 7150 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7151 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7152 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7153 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7154 queue_list = SYSCTL_CHILDREN(queue_node); 7155 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7156 CTLFLAG_RD, 7157 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7158 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7159 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7160 CTLFLAG_RD, 7161 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7162 } 7163 7164 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7165 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7166 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7167 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7168 fl_list = SYSCTL_CHILDREN(fl_node); 7169 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7170 CTLFLAG_RD, 7171 &fl->ifl_pidx, 1, "Producer Index"); 7172 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7173 CTLFLAG_RD, 7174 &fl->ifl_cidx, 1, "Consumer Index"); 7175 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7176 CTLFLAG_RD, 7177 &fl->ifl_credits, 1, "credits available"); 7178 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7179 CTLFLAG_RD, 7180 &fl->ifl_buf_size, 1, "buffer size"); 7181 #if MEMORY_LOGGING 7182 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7183 CTLFLAG_RD, 7184 &fl->ifl_m_enqueued, "mbufs allocated"); 7185 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7186 CTLFLAG_RD, 7187 &fl->ifl_m_dequeued, "mbufs freed"); 7188 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7189 CTLFLAG_RD, 7190 &fl->ifl_cl_enqueued, "clusters allocated"); 7191 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7192 CTLFLAG_RD, 7193 &fl->ifl_cl_dequeued, "clusters freed"); 7194 #endif 7195 } 7196 } 7197 #endif 7198 } 7199 7200 void 7201 iflib_request_reset(if_ctx_t ctx) 7202 { 7203 7204 STATE_LOCK(ctx); 7205 ctx->ifc_flags |= IFC_DO_RESET; 7206 STATE_UNLOCK(ctx); 7207 } 7208 7209 #ifndef __NO_STRICT_ALIGNMENT 7210 static struct mbuf * 7211 iflib_fixup_rx(struct mbuf *m) 7212 { 7213 struct mbuf *n; 7214 7215 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7216 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7217 m->m_data += ETHER_HDR_LEN; 7218 n = m; 7219 } else { 7220 MGETHDR(n, M_NOWAIT, MT_DATA); 7221 if (n == NULL) { 7222 m_freem(m); 7223 return (NULL); 7224 } 7225 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7226 m->m_data += ETHER_HDR_LEN; 7227 m->m_len -= ETHER_HDR_LEN; 7228 n->m_len = ETHER_HDR_LEN; 7229 M_MOVE_PKTHDR(n, m); 7230 n->m_next = m; 7231 } 7232 return (n); 7233 } 7234 #endif 7235 7236 #ifdef DEBUGNET 7237 static void 7238 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7239 { 7240 if_ctx_t ctx; 7241 7242 ctx = if_getsoftc(ifp); 7243 CTX_LOCK(ctx); 7244 *nrxr = NRXQSETS(ctx); 7245 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7246 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7247 CTX_UNLOCK(ctx); 7248 } 7249 7250 static void 7251 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7252 { 7253 if_ctx_t ctx; 7254 if_softc_ctx_t scctx; 7255 iflib_fl_t fl; 7256 iflib_rxq_t rxq; 7257 int i, j; 7258 7259 ctx = if_getsoftc(ifp); 7260 scctx = &ctx->ifc_softc_ctx; 7261 7262 switch (event) { 7263 case DEBUGNET_START: 7264 #ifndef __HAIKU__ 7265 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7266 rxq = &ctx->ifc_rxqs[i]; 7267 for (j = 0; j < rxq->ifr_nfl; j++) { 7268 fl = rxq->ifr_fl; 7269 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7270 } 7271 } 7272 iflib_no_tx_batch = 1; 7273 break; 7274 #endif 7275 default: 7276 break; 7277 } 7278 } 7279 7280 static int 7281 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7282 { 7283 if_ctx_t ctx; 7284 iflib_txq_t txq; 7285 int error; 7286 7287 ctx = if_getsoftc(ifp); 7288 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7289 IFF_DRV_RUNNING) 7290 return (EBUSY); 7291 7292 txq = &ctx->ifc_txqs[0]; 7293 error = iflib_encap(txq, &m); 7294 if (error == 0) 7295 (void)iflib_txd_db_check(txq, true); 7296 return (error); 7297 } 7298 7299 static int 7300 iflib_debugnet_poll(if_t ifp, int count) 7301 { 7302 struct epoch_tracker et; 7303 if_ctx_t ctx; 7304 if_softc_ctx_t scctx; 7305 iflib_txq_t txq; 7306 int i; 7307 7308 ctx = if_getsoftc(ifp); 7309 scctx = &ctx->ifc_softc_ctx; 7310 7311 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7312 IFF_DRV_RUNNING) 7313 return (EBUSY); 7314 7315 txq = &ctx->ifc_txqs[0]; 7316 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7317 7318 NET_EPOCH_ENTER(et); 7319 for (i = 0; i < scctx->isc_nrxqsets; i++) 7320 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7321 NET_EPOCH_EXIT(et); 7322 return (0); 7323 } 7324 #endif /* DEBUGNET */ 7325