1*fce4895dSRene Gollent /* 2*fce4895dSRene Gollent * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 3*fce4895dSRene Gollent * Copyright 2009-2012, Ingo Weinhold, ingo_weinhold@gmx.de. 4*fce4895dSRene Gollent * Copyright 2011-2013, Rene Gollent, rene@gollent.com. 5*fce4895dSRene Gollent * Distributed under the terms of the MIT License. 6*fce4895dSRene Gollent */ 7*fce4895dSRene Gollent #ifndef CPU_STATE_X86_64_H 8*fce4895dSRene Gollent #define CPU_STATE_X86_64_H 9*fce4895dSRene Gollent 10*fce4895dSRene Gollent #include <bitset> 11*fce4895dSRene Gollent 12*fce4895dSRene Gollent #include <debugger.h> 13*fce4895dSRene Gollent 14*fce4895dSRene Gollent #include "CpuState.h" 15*fce4895dSRene Gollent 16*fce4895dSRene Gollent 17*fce4895dSRene Gollent enum { 18*fce4895dSRene Gollent X86_64_REGISTER_RIP = 0, 19*fce4895dSRene Gollent X86_64_REGISTER_RSP, 20*fce4895dSRene Gollent X86_64_REGISTER_RBP, 21*fce4895dSRene Gollent 22*fce4895dSRene Gollent X86_64_REGISTER_RAX, 23*fce4895dSRene Gollent X86_64_REGISTER_RBX, 24*fce4895dSRene Gollent X86_64_REGISTER_RCX, 25*fce4895dSRene Gollent X86_64_REGISTER_RDX, 26*fce4895dSRene Gollent 27*fce4895dSRene Gollent X86_64_REGISTER_RSI, 28*fce4895dSRene Gollent X86_64_REGISTER_RDI, 29*fce4895dSRene Gollent 30*fce4895dSRene Gollent X86_64_REGISTER_R8, 31*fce4895dSRene Gollent X86_64_REGISTER_R9, 32*fce4895dSRene Gollent X86_64_REGISTER_R10, 33*fce4895dSRene Gollent X86_64_REGISTER_R11, 34*fce4895dSRene Gollent X86_64_REGISTER_R12, 35*fce4895dSRene Gollent X86_64_REGISTER_R13, 36*fce4895dSRene Gollent X86_64_REGISTER_R14, 37*fce4895dSRene Gollent X86_64_REGISTER_R15, 38*fce4895dSRene Gollent 39*fce4895dSRene Gollent X86_64_REGISTER_CS, 40*fce4895dSRene Gollent X86_64_REGISTER_DS, 41*fce4895dSRene Gollent X86_64_REGISTER_ES, 42*fce4895dSRene Gollent X86_64_REGISTER_FS, 43*fce4895dSRene Gollent X86_64_REGISTER_GS, 44*fce4895dSRene Gollent X86_64_REGISTER_SS, 45*fce4895dSRene Gollent 46*fce4895dSRene Gollent X86_64_INT_REGISTER_END, 47*fce4895dSRene Gollent 48*fce4895dSRene Gollent X86_64_REGISTER_ST0, 49*fce4895dSRene Gollent X86_64_REGISTER_ST1, 50*fce4895dSRene Gollent X86_64_REGISTER_ST2, 51*fce4895dSRene Gollent X86_64_REGISTER_ST3, 52*fce4895dSRene Gollent X86_64_REGISTER_ST4, 53*fce4895dSRene Gollent X86_64_REGISTER_ST5, 54*fce4895dSRene Gollent X86_64_REGISTER_ST6, 55*fce4895dSRene Gollent X86_64_REGISTER_ST7, 56*fce4895dSRene Gollent 57*fce4895dSRene Gollent X86_64_FP_REGISTER_END, 58*fce4895dSRene Gollent 59*fce4895dSRene Gollent X86_64_REGISTER_MM0, 60*fce4895dSRene Gollent X86_64_REGISTER_MM1, 61*fce4895dSRene Gollent X86_64_REGISTER_MM2, 62*fce4895dSRene Gollent X86_64_REGISTER_MM3, 63*fce4895dSRene Gollent X86_64_REGISTER_MM4, 64*fce4895dSRene Gollent X86_64_REGISTER_MM5, 65*fce4895dSRene Gollent X86_64_REGISTER_MM6, 66*fce4895dSRene Gollent X86_64_REGISTER_MM7, 67*fce4895dSRene Gollent 68*fce4895dSRene Gollent X86_64_MMX_REGISTER_END, 69*fce4895dSRene Gollent 70*fce4895dSRene Gollent X86_64_REGISTER_XMM0, 71*fce4895dSRene Gollent X86_64_REGISTER_XMM1, 72*fce4895dSRene Gollent X86_64_REGISTER_XMM2, 73*fce4895dSRene Gollent X86_64_REGISTER_XMM3, 74*fce4895dSRene Gollent X86_64_REGISTER_XMM4, 75*fce4895dSRene Gollent X86_64_REGISTER_XMM5, 76*fce4895dSRene Gollent X86_64_REGISTER_XMM6, 77*fce4895dSRene Gollent X86_64_REGISTER_XMM7, 78*fce4895dSRene Gollent X86_64_REGISTER_XMM8, 79*fce4895dSRene Gollent X86_64_REGISTER_XMM9, 80*fce4895dSRene Gollent X86_64_REGISTER_XMM10, 81*fce4895dSRene Gollent X86_64_REGISTER_XMM11, 82*fce4895dSRene Gollent X86_64_REGISTER_XMM12, 83*fce4895dSRene Gollent X86_64_REGISTER_XMM13, 84*fce4895dSRene Gollent X86_64_REGISTER_XMM14, 85*fce4895dSRene Gollent X86_64_REGISTER_XMM15, 86*fce4895dSRene Gollent 87*fce4895dSRene Gollent X86_64_XMM_REGISTER_END, 88*fce4895dSRene Gollent 89*fce4895dSRene Gollent X86_64_REGISTER_COUNT 90*fce4895dSRene Gollent }; 91*fce4895dSRene Gollent 92*fce4895dSRene Gollent 93*fce4895dSRene Gollent #define X86_64_INT_REGISTER_COUNT X86_64_INT_REGISTER_END 94*fce4895dSRene Gollent #define X86_64_FP_REGISTER_COUNT (X86_64_FP_REGISTER_END \ 95*fce4895dSRene Gollent - X86_64_INT_REGISTER_END) 96*fce4895dSRene Gollent #define X86_64_MMX_REGISTER_COUNT (X86_64_MMX_REGISTER_END \ 97*fce4895dSRene Gollent - X86_64_FP_REGISTER_END) 98*fce4895dSRene Gollent #define X86_64_XMM_REGISTER_COUNT (X86_64_XMM_REGISTER_END \ 99*fce4895dSRene Gollent - X86_64_MMX_REGISTER_END) 100*fce4895dSRene Gollent 101*fce4895dSRene Gollent 102*fce4895dSRene Gollent class CpuStateX8664 : public CpuState { 103*fce4895dSRene Gollent public: 104*fce4895dSRene Gollent CpuStateX8664(); 105*fce4895dSRene Gollent CpuStateX8664(const x86_64_debug_cpu_state& state); 106*fce4895dSRene Gollent virtual ~CpuStateX8664(); 107*fce4895dSRene Gollent 108*fce4895dSRene Gollent virtual status_t Clone(CpuState*& _clone) const; 109*fce4895dSRene Gollent 110*fce4895dSRene Gollent virtual status_t UpdateDebugState(void* state, size_t size) 111*fce4895dSRene Gollent const; 112*fce4895dSRene Gollent 113*fce4895dSRene Gollent virtual target_addr_t InstructionPointer() const; 114*fce4895dSRene Gollent virtual void SetInstructionPointer(target_addr_t address); 115*fce4895dSRene Gollent 116*fce4895dSRene Gollent virtual target_addr_t StackFramePointer() const; 117*fce4895dSRene Gollent virtual target_addr_t StackPointer() const; 118*fce4895dSRene Gollent virtual bool GetRegisterValue(const Register* reg, 119*fce4895dSRene Gollent BVariant& _value) const; 120*fce4895dSRene Gollent virtual bool SetRegisterValue(const Register* reg, 121*fce4895dSRene Gollent const BVariant& value); 122*fce4895dSRene Gollent 123*fce4895dSRene Gollent uint64 InterruptVector() const 124*fce4895dSRene Gollent { return fInterruptVector; } 125*fce4895dSRene Gollent 126*fce4895dSRene Gollent bool IsRegisterSet(int32 index) const; 127*fce4895dSRene Gollent 128*fce4895dSRene Gollent uint64 IntRegisterValue(int32 index) const; 129*fce4895dSRene Gollent void SetIntRegister(int32 index, uint64 value); 130*fce4895dSRene Gollent 131*fce4895dSRene Gollent double FloatRegisterValue(int32 index) const; 132*fce4895dSRene Gollent void SetFloatRegister(int32 index, double value); 133*fce4895dSRene Gollent 134*fce4895dSRene Gollent const void* MMXRegisterValue(int32 index) const; 135*fce4895dSRene Gollent void SetMMXRegister(int32 index, 136*fce4895dSRene Gollent const uint8* value); 137*fce4895dSRene Gollent 138*fce4895dSRene Gollent const void* XMMRegisterValue(int32 index) const; 139*fce4895dSRene Gollent void SetXMMRegister(int32 index, 140*fce4895dSRene Gollent const uint8* value); 141*fce4895dSRene Gollent 142*fce4895dSRene Gollent void UnsetRegister(int32 index); 143*fce4895dSRene Gollent 144*fce4895dSRene Gollent private: 145*fce4895dSRene Gollent typedef std::bitset<X86_64_REGISTER_COUNT> RegisterBitSet; 146*fce4895dSRene Gollent 147*fce4895dSRene Gollent private: 148*fce4895dSRene Gollent uint64 fIntRegisters[X86_64_INT_REGISTER_COUNT]; 149*fce4895dSRene Gollent double fFloatRegisters[X86_64_FP_REGISTER_COUNT]; 150*fce4895dSRene Gollent x86_64_fp_register fMMXRegisters[X86_64_MMX_REGISTER_COUNT]; 151*fce4895dSRene Gollent x86_64_xmm_register fXMMRegisters[X86_64_XMM_REGISTER_COUNT]; 152*fce4895dSRene Gollent RegisterBitSet fSetRegisters; 153*fce4895dSRene Gollent uint64 fInterruptVector; 154*fce4895dSRene Gollent }; 155*fce4895dSRene Gollent 156*fce4895dSRene Gollent 157*fce4895dSRene Gollent #endif // CPU_STATE_X86_64_H 158