xref: /haiku/src/kits/debugger/arch/x86_64/CpuStateX8664.h (revision 6f3a5c9ab0c2f388ef0ff6efff713732a710cd93)
1fce4895dSRene Gollent /*
2fce4895dSRene Gollent  * Copyright 2012, Alex Smith, alex@alex-smith.me.uk.
3fce4895dSRene Gollent  * Copyright 2009-2012, Ingo Weinhold, ingo_weinhold@gmx.de.
4fce4895dSRene Gollent  * Copyright 2011-2013, Rene Gollent, rene@gollent.com.
5fce4895dSRene Gollent  * Distributed under the terms of the MIT License.
6fce4895dSRene Gollent  */
7fce4895dSRene Gollent #ifndef CPU_STATE_X86_64_H
8fce4895dSRene Gollent #define CPU_STATE_X86_64_H
9fce4895dSRene Gollent 
10fce4895dSRene Gollent #include <bitset>
11fce4895dSRene Gollent 
12fce4895dSRene Gollent #include <debugger.h>
13fce4895dSRene Gollent 
14fce4895dSRene Gollent #include "CpuState.h"
15fce4895dSRene Gollent 
16fce4895dSRene Gollent 
17fce4895dSRene Gollent enum {
18fce4895dSRene Gollent 	X86_64_REGISTER_RIP = 0,
19fce4895dSRene Gollent 	X86_64_REGISTER_RSP,
20fce4895dSRene Gollent 	X86_64_REGISTER_RBP,
21fce4895dSRene Gollent 
22fce4895dSRene Gollent 	X86_64_REGISTER_RAX,
23fce4895dSRene Gollent 	X86_64_REGISTER_RBX,
24fce4895dSRene Gollent 	X86_64_REGISTER_RCX,
25fce4895dSRene Gollent 	X86_64_REGISTER_RDX,
26fce4895dSRene Gollent 
27fce4895dSRene Gollent 	X86_64_REGISTER_RSI,
28fce4895dSRene Gollent 	X86_64_REGISTER_RDI,
29fce4895dSRene Gollent 
30fce4895dSRene Gollent 	X86_64_REGISTER_R8,
31fce4895dSRene Gollent 	X86_64_REGISTER_R9,
32fce4895dSRene Gollent 	X86_64_REGISTER_R10,
33fce4895dSRene Gollent 	X86_64_REGISTER_R11,
34fce4895dSRene Gollent 	X86_64_REGISTER_R12,
35fce4895dSRene Gollent 	X86_64_REGISTER_R13,
36fce4895dSRene Gollent 	X86_64_REGISTER_R14,
37fce4895dSRene Gollent 	X86_64_REGISTER_R15,
38fce4895dSRene Gollent 
39fce4895dSRene Gollent 	X86_64_REGISTER_CS,
40fce4895dSRene Gollent 	X86_64_REGISTER_DS,
41fce4895dSRene Gollent 	X86_64_REGISTER_ES,
42fce4895dSRene Gollent 	X86_64_REGISTER_FS,
43fce4895dSRene Gollent 	X86_64_REGISTER_GS,
44fce4895dSRene Gollent 	X86_64_REGISTER_SS,
45fce4895dSRene Gollent 
46fce4895dSRene Gollent 	X86_64_INT_REGISTER_END,
47fce4895dSRene Gollent 
48fce4895dSRene Gollent 	X86_64_REGISTER_ST0,
49fce4895dSRene Gollent 	X86_64_REGISTER_ST1,
50fce4895dSRene Gollent 	X86_64_REGISTER_ST2,
51fce4895dSRene Gollent 	X86_64_REGISTER_ST3,
52fce4895dSRene Gollent 	X86_64_REGISTER_ST4,
53fce4895dSRene Gollent 	X86_64_REGISTER_ST5,
54fce4895dSRene Gollent 	X86_64_REGISTER_ST6,
55fce4895dSRene Gollent 	X86_64_REGISTER_ST7,
56fce4895dSRene Gollent 
57fce4895dSRene Gollent 	X86_64_FP_REGISTER_END,
58fce4895dSRene Gollent 
59fce4895dSRene Gollent 	X86_64_REGISTER_MM0,
60fce4895dSRene Gollent 	X86_64_REGISTER_MM1,
61fce4895dSRene Gollent 	X86_64_REGISTER_MM2,
62fce4895dSRene Gollent 	X86_64_REGISTER_MM3,
63fce4895dSRene Gollent 	X86_64_REGISTER_MM4,
64fce4895dSRene Gollent 	X86_64_REGISTER_MM5,
65fce4895dSRene Gollent 	X86_64_REGISTER_MM6,
66fce4895dSRene Gollent 	X86_64_REGISTER_MM7,
67fce4895dSRene Gollent 
68fce4895dSRene Gollent 	X86_64_MMX_REGISTER_END,
69fce4895dSRene Gollent 
70fce4895dSRene Gollent 	X86_64_REGISTER_XMM0,
71fce4895dSRene Gollent 	X86_64_REGISTER_XMM1,
72fce4895dSRene Gollent 	X86_64_REGISTER_XMM2,
73fce4895dSRene Gollent 	X86_64_REGISTER_XMM3,
74fce4895dSRene Gollent 	X86_64_REGISTER_XMM4,
75fce4895dSRene Gollent 	X86_64_REGISTER_XMM5,
76fce4895dSRene Gollent 	X86_64_REGISTER_XMM6,
77fce4895dSRene Gollent 	X86_64_REGISTER_XMM7,
78fce4895dSRene Gollent 	X86_64_REGISTER_XMM8,
79fce4895dSRene Gollent 	X86_64_REGISTER_XMM9,
80fce4895dSRene Gollent 	X86_64_REGISTER_XMM10,
81fce4895dSRene Gollent 	X86_64_REGISTER_XMM11,
82fce4895dSRene Gollent 	X86_64_REGISTER_XMM12,
83fce4895dSRene Gollent 	X86_64_REGISTER_XMM13,
84fce4895dSRene Gollent 	X86_64_REGISTER_XMM14,
85fce4895dSRene Gollent 	X86_64_REGISTER_XMM15,
86fce4895dSRene Gollent 
87fce4895dSRene Gollent 	X86_64_XMM_REGISTER_END,
88fce4895dSRene Gollent 
89fce4895dSRene Gollent 	X86_64_REGISTER_COUNT
90fce4895dSRene Gollent };
91fce4895dSRene Gollent 
92fce4895dSRene Gollent 
93fce4895dSRene Gollent #define X86_64_INT_REGISTER_COUNT X86_64_INT_REGISTER_END
94fce4895dSRene Gollent #define X86_64_FP_REGISTER_COUNT (X86_64_FP_REGISTER_END \
95fce4895dSRene Gollent 	- X86_64_INT_REGISTER_END)
96fce4895dSRene Gollent #define X86_64_MMX_REGISTER_COUNT (X86_64_MMX_REGISTER_END \
97fce4895dSRene Gollent 	- X86_64_FP_REGISTER_END)
98fce4895dSRene Gollent #define X86_64_XMM_REGISTER_COUNT (X86_64_XMM_REGISTER_END \
99fce4895dSRene Gollent 	- X86_64_MMX_REGISTER_END)
100fce4895dSRene Gollent 
101fce4895dSRene Gollent 
102*6f3a5c9aSAdrien Destugues struct x86_64_ymm_register {
103*6f3a5c9aSAdrien Destugues 	unsigned long value[4];
104*6f3a5c9aSAdrien Destugues };
105*6f3a5c9aSAdrien Destugues 
106*6f3a5c9aSAdrien Destugues 
107fce4895dSRene Gollent class CpuStateX8664 : public CpuState {
108fce4895dSRene Gollent public:
109fce4895dSRene Gollent 								CpuStateX8664();
110fce4895dSRene Gollent 								CpuStateX8664(const x86_64_debug_cpu_state& state);
111fce4895dSRene Gollent 	virtual						~CpuStateX8664();
112fce4895dSRene Gollent 
113fce4895dSRene Gollent 	virtual	status_t			Clone(CpuState*& _clone) const;
114fce4895dSRene Gollent 
115fce4895dSRene Gollent 	virtual	status_t			UpdateDebugState(void* state, size_t size)
116fce4895dSRene Gollent 									const;
117fce4895dSRene Gollent 
118fce4895dSRene Gollent 	virtual	target_addr_t		InstructionPointer() const;
119fce4895dSRene Gollent 	virtual void				SetInstructionPointer(target_addr_t address);
120fce4895dSRene Gollent 
121fce4895dSRene Gollent 	virtual	target_addr_t		StackFramePointer() const;
122fce4895dSRene Gollent 	virtual	target_addr_t		StackPointer() const;
123fce4895dSRene Gollent 	virtual	bool				GetRegisterValue(const Register* reg,
124fce4895dSRene Gollent 									BVariant& _value) const;
125fce4895dSRene Gollent 	virtual	bool				SetRegisterValue(const Register* reg,
126fce4895dSRene Gollent 									const BVariant& value);
127fce4895dSRene Gollent 
InterruptVector()128fce4895dSRene Gollent 			uint64				InterruptVector() const
129fce4895dSRene Gollent 									{ return fInterruptVector; }
130fce4895dSRene Gollent 
131fce4895dSRene Gollent 			bool				IsRegisterSet(int32 index) const;
132fce4895dSRene Gollent 
133fce4895dSRene Gollent 			uint64				IntRegisterValue(int32 index) const;
134fce4895dSRene Gollent 			void				SetIntRegister(int32 index, uint64 value);
135fce4895dSRene Gollent 
136*6f3a5c9aSAdrien Destugues private:
137fce4895dSRene Gollent 			double				FloatRegisterValue(int32 index) const;
138fce4895dSRene Gollent 			void				SetFloatRegister(int32 index, double value);
139fce4895dSRene Gollent 
140fce4895dSRene Gollent 			const void*			MMXRegisterValue(int32 index) const;
141fce4895dSRene Gollent 			void				SetMMXRegister(int32 index,
142fce4895dSRene Gollent 									const uint8* value);
143fce4895dSRene Gollent 
144fce4895dSRene Gollent 			const void*			XMMRegisterValue(int32 index) const;
145fce4895dSRene Gollent 			void				SetXMMRegister(int32 index,
146*6f3a5c9aSAdrien Destugues 									const uint8* highValue, const uint8* lowValue);
147fce4895dSRene Gollent 
148fce4895dSRene Gollent 			void				UnsetRegister(int32 index);
149fce4895dSRene Gollent 
150fce4895dSRene Gollent private:
151fce4895dSRene Gollent 	typedef std::bitset<X86_64_REGISTER_COUNT> RegisterBitSet;
152fce4895dSRene Gollent 
153fce4895dSRene Gollent private:
154fce4895dSRene Gollent 			uint64				fIntRegisters[X86_64_INT_REGISTER_COUNT];
155fce4895dSRene Gollent 			double				fFloatRegisters[X86_64_FP_REGISTER_COUNT];
156fce4895dSRene Gollent 			x86_64_fp_register	fMMXRegisters[X86_64_MMX_REGISTER_COUNT];
157*6f3a5c9aSAdrien Destugues 			x86_64_ymm_register	fXMMRegisters[X86_64_XMM_REGISTER_COUNT];
158fce4895dSRene Gollent 			RegisterBitSet		fSetRegisters;
159fce4895dSRene Gollent 			uint64				fInterruptVector;
160fce4895dSRene Gollent };
161fce4895dSRene Gollent 
162fce4895dSRene Gollent 
163fce4895dSRene Gollent #endif	// CPU_STATE_X86_64_H
164