1*fce4895dSRene Gollent /* 2*fce4895dSRene Gollent * Copyright 2009-2012, Ingo Weinhold, ingo_weinhold@gmx.de. 3*fce4895dSRene Gollent * Copyright 2011-2014, Rene Gollent, rene@gollent.com. 4*fce4895dSRene Gollent * Distributed under the terms of the MIT License. 5*fce4895dSRene Gollent */ 6*fce4895dSRene Gollent #ifndef CPU_STATE_X86_H 7*fce4895dSRene Gollent #define CPU_STATE_X86_H 8*fce4895dSRene Gollent 9*fce4895dSRene Gollent #include <bitset> 10*fce4895dSRene Gollent 11*fce4895dSRene Gollent #include <debugger.h> 12*fce4895dSRene Gollent 13*fce4895dSRene Gollent #include "CpuState.h" 14*fce4895dSRene Gollent 15*fce4895dSRene Gollent 16*fce4895dSRene Gollent enum { 17*fce4895dSRene Gollent X86_REGISTER_EIP = 0, 18*fce4895dSRene Gollent X86_REGISTER_ESP, 19*fce4895dSRene Gollent X86_REGISTER_EBP, 20*fce4895dSRene Gollent 21*fce4895dSRene Gollent X86_REGISTER_EAX, 22*fce4895dSRene Gollent X86_REGISTER_EBX, 23*fce4895dSRene Gollent X86_REGISTER_ECX, 24*fce4895dSRene Gollent X86_REGISTER_EDX, 25*fce4895dSRene Gollent 26*fce4895dSRene Gollent X86_REGISTER_ESI, 27*fce4895dSRene Gollent X86_REGISTER_EDI, 28*fce4895dSRene Gollent 29*fce4895dSRene Gollent X86_REGISTER_CS, 30*fce4895dSRene Gollent X86_REGISTER_DS, 31*fce4895dSRene Gollent X86_REGISTER_ES, 32*fce4895dSRene Gollent X86_REGISTER_FS, 33*fce4895dSRene Gollent X86_REGISTER_GS, 34*fce4895dSRene Gollent X86_REGISTER_SS, 35*fce4895dSRene Gollent 36*fce4895dSRene Gollent X86_INT_REGISTER_END, 37*fce4895dSRene Gollent 38*fce4895dSRene Gollent X86_REGISTER_ST0, 39*fce4895dSRene Gollent X86_REGISTER_ST1, 40*fce4895dSRene Gollent X86_REGISTER_ST2, 41*fce4895dSRene Gollent X86_REGISTER_ST3, 42*fce4895dSRene Gollent X86_REGISTER_ST4, 43*fce4895dSRene Gollent X86_REGISTER_ST5, 44*fce4895dSRene Gollent X86_REGISTER_ST6, 45*fce4895dSRene Gollent X86_REGISTER_ST7, 46*fce4895dSRene Gollent 47*fce4895dSRene Gollent X86_FP_REGISTER_END, 48*fce4895dSRene Gollent 49*fce4895dSRene Gollent X86_REGISTER_MM0, 50*fce4895dSRene Gollent X86_REGISTER_MM1, 51*fce4895dSRene Gollent X86_REGISTER_MM2, 52*fce4895dSRene Gollent X86_REGISTER_MM3, 53*fce4895dSRene Gollent X86_REGISTER_MM4, 54*fce4895dSRene Gollent X86_REGISTER_MM5, 55*fce4895dSRene Gollent X86_REGISTER_MM6, 56*fce4895dSRene Gollent X86_REGISTER_MM7, 57*fce4895dSRene Gollent 58*fce4895dSRene Gollent X86_MMX_REGISTER_END, 59*fce4895dSRene Gollent 60*fce4895dSRene Gollent X86_REGISTER_XMM0, 61*fce4895dSRene Gollent X86_REGISTER_XMM1, 62*fce4895dSRene Gollent X86_REGISTER_XMM2, 63*fce4895dSRene Gollent X86_REGISTER_XMM3, 64*fce4895dSRene Gollent X86_REGISTER_XMM4, 65*fce4895dSRene Gollent X86_REGISTER_XMM5, 66*fce4895dSRene Gollent X86_REGISTER_XMM6, 67*fce4895dSRene Gollent X86_REGISTER_XMM7, 68*fce4895dSRene Gollent 69*fce4895dSRene Gollent X86_XMM_REGISTER_END, 70*fce4895dSRene Gollent 71*fce4895dSRene Gollent X86_REGISTER_COUNT 72*fce4895dSRene Gollent }; 73*fce4895dSRene Gollent 74*fce4895dSRene Gollent 75*fce4895dSRene Gollent #define X86_INT_REGISTER_COUNT X86_INT_REGISTER_END 76*fce4895dSRene Gollent #define X86_FP_REGISTER_COUNT (X86_FP_REGISTER_END - X86_INT_REGISTER_END) 77*fce4895dSRene Gollent #define X86_MMX_REGISTER_COUNT (X86_MMX_REGISTER_END - X86_FP_REGISTER_END) 78*fce4895dSRene Gollent #define X86_XMM_REGISTER_COUNT (X86_XMM_REGISTER_END - X86_MMX_REGISTER_END) 79*fce4895dSRene Gollent 80*fce4895dSRene Gollent 81*fce4895dSRene Gollent class CpuStateX86 : public CpuState { 82*fce4895dSRene Gollent public: 83*fce4895dSRene Gollent CpuStateX86(); 84*fce4895dSRene Gollent CpuStateX86(const x86_debug_cpu_state& state); 85*fce4895dSRene Gollent virtual ~CpuStateX86(); 86*fce4895dSRene Gollent 87*fce4895dSRene Gollent virtual status_t Clone(CpuState*& _clone) const; 88*fce4895dSRene Gollent 89*fce4895dSRene Gollent virtual status_t UpdateDebugState(void* state, size_t size) 90*fce4895dSRene Gollent const; 91*fce4895dSRene Gollent 92*fce4895dSRene Gollent virtual target_addr_t InstructionPointer() const; 93*fce4895dSRene Gollent virtual void SetInstructionPointer(target_addr_t address); 94*fce4895dSRene Gollent 95*fce4895dSRene Gollent virtual target_addr_t StackFramePointer() const; 96*fce4895dSRene Gollent virtual target_addr_t StackPointer() const; 97*fce4895dSRene Gollent virtual bool GetRegisterValue(const Register* reg, 98*fce4895dSRene Gollent BVariant& _value) const; 99*fce4895dSRene Gollent virtual bool SetRegisterValue(const Register* reg, 100*fce4895dSRene Gollent const BVariant& value); 101*fce4895dSRene Gollent InterruptVector()102*fce4895dSRene Gollent uint32 InterruptVector() const 103*fce4895dSRene Gollent { return fInterruptVector; } 104*fce4895dSRene Gollent 105*fce4895dSRene Gollent bool IsRegisterSet(int32 index) const; 106*fce4895dSRene Gollent 107*fce4895dSRene Gollent uint32 IntRegisterValue(int32 index) const; 108*fce4895dSRene Gollent void SetIntRegister(int32 index, uint32 value); 109*fce4895dSRene Gollent 110*fce4895dSRene Gollent double FloatRegisterValue(int32 index) const; 111*fce4895dSRene Gollent void SetFloatRegister(int32 index, double value); 112*fce4895dSRene Gollent 113*fce4895dSRene Gollent const void* MMXRegisterValue(int32 index) const; 114*fce4895dSRene Gollent void SetMMXRegister(int32 index, 115*fce4895dSRene Gollent const uint8* value); 116*fce4895dSRene Gollent 117*fce4895dSRene Gollent const void* XMMRegisterValue(int32 index) const; 118*fce4895dSRene Gollent void SetXMMRegister(int32 index, 119*fce4895dSRene Gollent const uint8* value); 120*fce4895dSRene Gollent 121*fce4895dSRene Gollent void UnsetRegister(int32 index); 122*fce4895dSRene Gollent 123*fce4895dSRene Gollent private: 124*fce4895dSRene Gollent typedef std::bitset<X86_REGISTER_COUNT> RegisterBitSet; 125*fce4895dSRene Gollent 126*fce4895dSRene Gollent private: 127*fce4895dSRene Gollent uint32 fIntRegisters[X86_INT_REGISTER_COUNT]; 128*fce4895dSRene Gollent double fFloatRegisters[X86_FP_REGISTER_COUNT]; 129*fce4895dSRene Gollent x86_fp_register fMMXRegisters[X86_MMX_REGISTER_COUNT]; 130*fce4895dSRene Gollent x86_xmm_register fXMMRegisters[X86_XMM_REGISTER_COUNT]; 131*fce4895dSRene Gollent 132*fce4895dSRene Gollent RegisterBitSet fSetRegisters; 133*fce4895dSRene Gollent uint32 fInterruptVector; 134*fce4895dSRene Gollent }; 135*fce4895dSRene Gollent 136*fce4895dSRene Gollent 137*fce4895dSRene Gollent #endif // CPU_STATE_X86_H 138