1 /****************************************************************************** 2 / 3 / File: Theater.cpp 4 / 5 / Description: ATI Rage Theater Video Decoder interface. 6 / 7 / Copyright 2001, Carlos Hasan 8 / 9 *******************************************************************************/ 10 11 #ifndef _THEATRE_REG_H 12 #define _THEATRE_REG_H 13 14 enum theater_register { 15 // TVOut Front End Datapath 16 VIP_RGB_CNTL = 0x0048, 17 RGB_IS_888_PACK = BITS(0:0), // Select 24/16 bit (888/565) RGB mode 18 UV_DITHER_EN = BITS(3:2), // Select dithering mode for U/V data 19 SWITCH_TO_BLUE = BITS(4:4), // Replace input video with blue screen 20 21 VIP_TVO_SYNC_PAT_ACCUM = 0x0108, 22 H_PATTERN_ACCUM = BITS(10:0), 23 SCAN_REF_OFFSET = BITS(15:11), 24 BYTE0 = BITS(23:16), 25 BYTE1 = BITS(31:24), 26 27 VIP_TV0_SYNC_THRESHOLD = 0x010c, 28 MAX_H_PATTERNS = BITS(10:0), 29 MIN_H_PATTERNS = BITS(27:16), 30 31 VIP_TVO_SYNC_PAT_EXPECT = 0x0110, 32 SYNC_PAT_EXPECT_W0 = BITS(15:0), 33 SYNC_PAT_EXPECT_W1 = BITS(23:16), 34 35 VIP_DELAY_ONE_MAP_A = 0x0114, 36 DELAY_ONE_MAP_W0 = BITS(15:0), 37 DELAY_ONE_MAP_W1 = BITS(31:16), 38 39 VIP_DELAY_ONE_MAP_B = 0x0118, 40 DELAY_ONE_MAP_W2 = BITS(15:0), 41 42 VIP_DELAY_ZERO_MAP_A = 0x011c, 43 DELAY_ZERO_MAP_W0 = BITS(15:0), 44 DELAY_ZERO_MAP_W1 = BITS(31:16), 45 46 VIP_DELAY_ZERO_MAP_B = 0x0120, 47 DELAY_ZERO_MAP_W2 = BITS(15:0), 48 49 VIP_TVO_DATA_DELAY_A = 0x0140, 50 TVO_DATA0_DELAY = BITS(5:0), 51 TVO_DATA1_DELAY = BITS(13:8), 52 TVO_DATA2_DELAY = BITS(21:16), 53 TVO_DATA3_DELAY = BITS(29:24), 54 55 VIP_TVO_DATA_DELAY_B = 0x0144, 56 TVO_DATA4_DELAY = BITS(5:0), 57 TVO_DATA5_DELAY = BITS(13:8), 58 TVO_DATA6_DELAY = BITS(21:16), 59 TVO_DATA7_DELAY = BITS(29:24), 60 61 VIP_VSCALER_CNTL1 = 0x01c0, 62 UV_INC = BITS(15:0), // Vertical scaling of CRTC UV data 63 UV_THINNER = BITS(22:16), // Number of lines in the UV data that 64 // are not blended to create a line on TV 65 Y_W_EN = BITS(24:24), 66 Y_DEL_W_SIG = BITS(27:26), 67 68 VIP_VSCALER_CNTL2 = 0x01c8, 69 DITHER_MODE = BITS(0:0), // Select dithering mode 70 Y_OUTPUT_DITHER_EN = BITS(1:1), 71 UV_OUTPUT_DITHER_EN = BITS(2:2), 72 UV_TO_BUF_DITHER_EN = BITS(3:3), 73 UV_ACCUM_INIT = BITS(31:24), 74 75 VIP_Y_FALL_CNTL = 0x01cc, 76 Y_FALL_ACCUM_INIT = BITS(15:0), 77 Y_FALL_PING_PONG = BITS(16:16), 78 Y_COEF_EN = BITS(17:17), 79 Y_COEF_VALUE = BITS(31:24), 80 81 VIP_Y_RISE_CNTL = 0x01d0, 82 Y_RISE_ACCUM_INIT = BITS(15:0), 83 Y_RISE_PING_PONG = BITS(16:16), 84 85 VIP_Y_SAW_TOOTH_CNTL = 0x01d4, 86 Y_SAW_TOOTH_MAP = BITS(15:0), 87 Y_SAW_TOOTH_SLOPE = BITS(31:16), 88 89 // TVOut Shadow CRTC 90 VIP_HTOTAL = 0x0080, 91 D_HTOTAL = BITS(10:0), // Number of clocks per line (-1) 92 93 VIP_HDISP = 0x0084, 94 D_HDISP = BITS(9:0), // Number of active pixels per line (-1) 95 96 VIP_HSIZE = 0x0088, 97 D_HSIZE = BITS(9:0), // Unused in Rage Theater A21 and later 98 99 VIP_HSTART = 0x008c, 100 D_HSTART = BITS(10:0), 101 102 VIP_HCOUNT = 0x0090, // Current horizontal CRT pixel within 103 D_HCOUNT = BITS(10:0), // a line being processed 104 105 VIP_VTOTAL = 0x0094, // Number of lines per frame (-1) 106 D_VTOTAL = BITS(9:0), 107 108 VIP_VDISP = 0x0098, // Number of active lines (-1) 109 D_VDISP = BITS(9:0), 110 111 VIP_VCOUNT = 0x009c, // Current vertical CRT line being processed 112 D_VCOUNT = BITS(9:0), 113 114 VIP_VFTOTAL = 0x00a0, // Number of CRT frames that occur during 115 D_FTOTAL = BITS(3:0), // one complete cycle of the TV timing (-1) 116 117 VIP_DFCOUNT = 0x00a4, // Current CRT frame count, equivalent to the 118 D_FCOUNT = BITS(3:0), // field number in a complete TV cycle 119 120 VIP_DFRESTART = 0x00a8, // The frame/field during which a restart 121 D_FRESTART = BITS(3:0), // will be generated when TV_MASTER is 0 122 123 VIP_DHRESTART = 0x00ac, // Horizontal pixel during which a restart 124 D_HRESTART = BITS(10:0), // will be generated when TV_MASTER is 0 125 126 VIP_DVRESTART = 0x00b0, // Vertical line during which a restart 127 D_VRESTART = BITS(9:0), // will be generated when TV_MASTER is 0 128 129 VIP_SYNC_SIZE = 0x00b4, // Number of pixels expected in the 130 D_SYNC_SIZE = BITS(9:0), // synchronization line 131 132 VIP_FRAME_LOCK_CNTL = 0x0100, 133 MAX_LOCK_STR = BITS(3:0), 134 FIELD_SYNC_EN = BITS(4:4), 135 FIELD_SYNC_TRIGGER = BITS(5:5), 136 ACTUAL_LOCK_STR = BITS(11:8), 137 AVG_MISSED_SYNC = BITS(15:12), 138 139 VIP_SYNC_LOCK_CNTL = 0x0104, 140 PRI_TVO_DATA_LINE_SEL = BITS(2:0), 141 SEC_SYNC_CHECK_DEL = BITS(13:8), 142 MPP_ACTIVE_AS_MASK = BITS(14:14), 143 MPP_ACTIVE_DS_MASK = BITS(15:15), 144 SYNC_COMMAND = BITS(18:16), 145 SYNC_LOCK_TRIGGER = BITS(21:21), 146 DETECT_EN = BITS(24:24), 147 SELF_LOCK_EN = BITS(25:25), 148 MAN_LOCK_EN = BITS(26:26), 149 MAX_REF_OFFSET = BITS(31:27), 150 151 // TVOut Up Sampling Filter 152 VIP_UPSAMP_COEFF0_0 = 0x0340, 153 COEFF0_0 = BITS(5:0), 154 COEFF0_1 = BITS(14:8), 155 COEFF0_2 = BITS(22:16), 156 COEFF0_3 = BITS(29:24), 157 158 VIP_UPSAMP_COEFF0_1 = 0x0344, 159 COEFF0_4 = BITS(7:0), 160 COEFF0_5 = BITS(15:8), 161 COEFF0_6 = BITS(21:16), 162 COEFF0_7 = BITS(30:24), 163 164 VIP_UPSAMP_COEFF0_2 = 0x0348, 165 COEFF0_8 = BITS(6:0), 166 COEFF0_9 = BITS(13:8), 167 168 VIP_UPSAMP_COEFF1_0 = 0x034c, 169 COEFF1_0 = BITS(5:0), 170 COEFF1_1 = BITS(14:8), 171 COEFF1_2 = BITS(22:16), 172 COEFF1_3 = BITS(29:24), 173 174 VIP_UPSAMP_COEFF1_1 = 0x0350, 175 COEFF1_4 = BITS(7:0), 176 COEFF1_5 = BITS(15:8), 177 COEFF1_6 = BITS(21:16), 178 COEFF1_7 = BITS(30:24), 179 180 VIP_UPSAMP_COEFF1_2 = 0x0354, 181 COEFF1_8 = BITS(6:0), 182 COEFF1_9 = BITS(13:8), 183 184 VIP_UPSAMP_COEFF2_0 = 0x0358, 185 COEFF2_0 = BITS(5:0), 186 COEFF2_1 = BITS(14:8), 187 COEFF2_2 = BITS(22:16), 188 COEFF2_3 = BITS(29:24), 189 190 VIP_UPSAMP_COEFF2_1 = 0x035c, 191 COEFF2_4 = BITS(7:0), 192 COEFF2_5 = BITS(15:8), 193 COEFF2_6 = BITS(21:16), 194 COEFF2_7 = BITS(30:24), 195 196 VIP_UPSAMP_COEFF2_2 = 0x0360, 197 COEFF2_8 = BITS(6:0), 198 COEFF2_9 = BITS(13:8), 199 200 VIP_UPSAMP_COEFF3_0 = 0x0364, 201 COEFF3_0 = BITS(5:0), 202 COEFF3_1 = BITS(14:8), 203 COEFF3_2 = BITS(22:16), 204 COEFF3_3 = BITS(29:24), 205 206 VIP_UPSAMP_COEFF3_1 = 0x0368, 207 COEFF3_4 = BITS(7:0), 208 COEFF3_5 = BITS(15:8), 209 COEFF3_6 = BITS(21:16), 210 COEFF3_7 = BITS(30:24), 211 212 VIP_UPSAMP_COEFF3_2 = 0x036c, 213 COEFF3_8 = BITS(6:0), 214 COEFF3_9 = BITS(13:8), 215 216 VIP_UPSAMP_COEFF4_0 = 0x0370, 217 COEFF4_0 = BITS(5:0), 218 COEFF4_1 = BITS(14:8), 219 COEFF4_2 = BITS(22:16), 220 COEFF4_3 = BITS(29:24), 221 222 VIP_UPSAMP_COEFF4_1 = 0x0374, 223 COEFF4_4 = BITS(7:0), 224 COEFF4_5 = BITS(15:8), 225 COEFF4_6 = BITS(21:16), 226 COEFF4_7 = BITS(30:24), 227 228 VIP_UPSAMP_COEFF4_2 = 0x0378, 229 COEFF4_8 = BITS(6:0), 230 COEFF4_9 = BITS(13:8), 231 232 // TVOut Encoder 233 VIP_SYNC_CNTL = 0x0050, 234 SYNC_OE = BITS(0:0), // Sync output enable 235 SYNC_OUT = BITS(1:1), // Sync output data 236 SYNC_IN = BITS(2:2), // Sync input data 237 SYNC_PUB = BITS(3:3), // Sync pull-up enable 238 SYNC_PD = BITS(4:4), // Sync pull-down enable 239 SYNC_DRV = BITS(5:5), // Sync drive select 240 SYNC_MX = BITS(11:8), // Sync mux 241 242 VIP_HOST_READ_DATA = 0x0180, 243 HOST_RD_DATA_W0 = BITS(15:0), 244 HOST_RD_DATA_W1 = BITS(27:16), 245 246 VIP_HOST_WRITE_DATA = 0x0184, 247 HOST_WR_DATA_W0 = BITS(15:0), 248 HOST_WR_DATA_W1 = BITS(27:16), 249 250 VIP_HOST_RD_WT_CNTL = 0x0188, 251 HOST_ADR = BITS(8:0), 252 HOST_FIFO_RD = BITS(12:12), 253 HOST_FIFO_RD_ACK = BITS(13:13), 254 HOST_FIFO_WT = BITS(14:14), 255 HOST_FIFO_WT_ACK = BITS(15:15), 256 257 VIP_TIMING_CNTL = 0x01c4, 258 H_INC = BITS(11:0), // Horizontal scaling of the TV image 259 REQ_DELAY = BITS(18:16), 260 REQ_Y_FIRST = BITS(19:19), 261 FORCE_BURST_ALWAYS = BITS(21:21), 262 UV_POST_SCALE_BYPASS = BITS(23:23), 263 UV_OUTPUT_POST_SCALE = BITS(31:24), 264 265 VIP_UPSAMP_AND_GAIN_CNTL = 0x01e0, 266 YUPSAMP_EN = BITS(0:0), // Enable Y upsampling filter 267 YUPSAMP_FLAT = BITS(1:1), // Force Y upsampling to use centre tap 268 UVUPSAMP_EN = BITS(2:2), // Enable U/V upsampling filters 269 UVUPSAMP_FLAT = BITS(3:3), // Force U/V upsampling to use centre tap 270 Y_BREAK_EN = BITS(8:8), // Enable Y break point 271 UV_BREAK_EN = BITS(10:10), // Enable U/V break point 272 273 VIP_GAIN_LIMIT_SETTINGS = 0x01e4, 274 Y_GAIN_LIMIT = BITS(10:0), // Gain limit for the luminance (Y) 275 UV_GAIN_LIMIT = BITS(24:16), // Gain limit for the chrominance (U/V) 276 277 VIP_LINEAR_GAIN_SETTINGS = 0x01e8, 278 Y_GAIN = BITS(8:0), // Gain for the luminance (1.8 fixed point) 279 UV_GAIN = BITS(24:16), // Gain for the chrominance (1.8 fixed point) 280 281 VIP_MODULATOR_CNTL1 = 0x0200, 282 YFLT_EN = BITS(2:2), // Enable Composite/SVideo Y filter 283 UVFLT_EN = BITS(3:3), // Enable U/V filters 284 ALT_PHASE_EN = BITS(6:6), // Phase alternating line (0=NTSC, 1=PAL) 285 SYNC_TIP_LEVEL = BITS(7:7), // Composite Y sync tip level 286 SET_UP_LEVEL = BITS(14:8), // Video setup level 287 BLANK_LEVEL = BITS(22:16), // Video blank level 288 SLEW_RATE_LIMIT = BITS(23:23), 289 FORCE_BLACK_WHITE = BITS(24:24), // Force B&W video 290 Y_FILT_BLEND = BITS(31:28), // Sharpness of Y filters 291 292 VIP_MODULATOR_CNTL2 = 0x0204, 293 U_BURST_LEVEL = BITS(8:0), 294 V_BUST_LEVEL = BITS(24:16), 295 296 VIP_PRE_DAC_MUX_CNTL = 0x0240, 297 Y_RED_EN = BITS(0:0), 298 C_GRN_EN = BITS(1:1), 299 CMP_BLU_EN = BITS(2:2), 300 DAC_DITHER_EN = BITS(3:3), 301 RED_MX = BITS(7:4), 302 GRN_MX = BITS(11:8), 303 BLU_MX = BITS(15:12), 304 FORCE_DAC_DATA = BITS(25:16), 305 YUPFILT_DISABLE = BITS(26:26), 306 CVUPFILT_DISABLE = BITS(27:27), 307 UUPFILT_DISABLE = BITS(28:28), 308 309 VIP_TV_DAC_CNTL = 0x0280, 310 NBLANK = BITS(0:0), 311 NHOLD = BITS(1:1), 312 PEDESTAL = BITS(2:2), 313 DASLEEP = BITS(3:3), 314 DETECT = BITS(4:4), 315 CMPOUT = BITS(5:5), 316 BGSLEEP = BITS(6:6), 317 STD = BITS(9:8), 318 MON = BITS(15:12), 319 320 VIP_CRC_CNTL = 0x02c0, 321 V_COMP_DATA_EN = BITS(1:0), 322 V_COMP_GATE = BITS(2:2), 323 V_COMP_EN = BITS(3:3), 324 RST_SUBC_ONRSTRT = BITS(4:4), 325 CRC_TV_RSTRT_SEL = BITS(5:5), 326 327 VIP_VIDEO_PORT_SIG = 0x02c4, 328 CRC_SIG = BITS(29:0), 329 330 VIP_UV_ADR = 0x0300, 331 MAX_UV_ADDR = BITS(7:0), 332 TABLE1_BOT_ADR = BITS(15:8), 333 TABLE3_TOP_ADR = BITS(23:16), 334 HCODE_TABLE_SEL = BITS(26:25), 335 VCODE_TABLE_SEL = BITS(28:27), 336 SWITCH_TABLE_REQ = BITS(31:31), 337 338 // TVOut VBI Control 339 VIP_VBI_CC_CNTL = 0x02c8, 340 VBI_CC_DATA = BITS(15:0), // VBI data for CC 341 VBI_CC_WT = BITS(24:24), // Initiates a write cycle using VBI_CC_DATA 342 VBI_CC_WT_ACK = BITS(25:25), 343 VBI_CC_HOLD = BITS(26:26), 344 VBI_DECODE_EN = BITS(31:31), 345 346 VIP_VBI_EDS_CNTL = 0x02cc, 347 VBI_EDS_DATA = BITS(15:0), 348 VBI_EDS_WT = BITS(24:24), 349 VBI_EDS_WT_ACK = BITS(25:25), 350 VBI_EDS_HOLD = BITS(26:26), 351 352 VIP_VBI_20BIT_CNTL = 0x02d0, 353 VBI_20BIT_DATA0 = BITS(15:0), 354 VBI_20BIT_DATA1 = BITS(19:16), 355 VBI_20BIT_WT = BITS(24:24), 356 VBI_20BIT_WT_ACK = BITS(25:25), 357 VBI_20BIT_HOLD = BITS(26:26), 358 359 VIP_VBI_DTO_CNTL = 0x02d4, 360 VBI_CC_DTO_P = BITS(15:0), 361 VBI_20BIT_DTO_P = BITS(31:16), 362 363 VIP_VBI_LEVEL_CNTL = 0x02d8, 364 VBI_CC_LEVEL = BITS(6:0), 365 VBI_20BIT_LEVEL = BITS(14:8), 366 VBI_CLK_RUNIN_GAIN = BITS(24:16), 367 368 // Video Decoder Horizontal Sync PLL Control 369 VIP_HS_PLINE = 0x0480, // Pixels per line (910) 370 HS_LINE_TOTAL = BITS(10:0), 371 372 VIP_HS_DTOINC = 0x0484, // ??? 373 HS_DTO_INC = BITS(19:0), 374 375 VIP_HS_PLLGAIN = 0x0488, 376 HS_PLL_SGAIN = BITS(3:0), 377 HS_PLL_FGAIN = BITS(7:4), 378 379 VIP_HS_MINMAXWIDTH = 0x048c, 380 MIN_PULSE_WIDTH = BITS(7:0), 381 MAX_PULSE_WIDTH = BITS(15:8), 382 383 VIP_HS_GENLOCKDELAY = 0x0490, 384 GEN_LOCK_DELAY = BITS(7:0), 385 386 VIP_HS_WINDOW_LIMIT = 0x0494, 387 WIN_CLOSE_LIMIT = BITS(10:0), 388 WIN_OPEN_LIMIT = BITS(26:16), 389 390 VIP_HS_WINDOW_OC_SPEED = 0x0498, 391 WIN_CLOSE_SPEED = BITS(3:0), 392 WIN_OPEN_SPEED = BITS(7:4), 393 394 VIP_HS_PULSE_WIDTH = 0x049c, 395 H_SYNC_PULSE_WIDTH = BITS(7:0), 396 HS_GENLOCKED = BITS(8:8), // HPLL is locked? 397 HS_SYNC_IN_WIN = BITS(9:9), // Sync in Hwindow? 398 399 VIP_HS_PLL_ERROR = 0x04a0, 400 HS_PLL_ERROR = BITS(14:0), 401 402 VIP_HS_PLL_FS_PATH = 0x04a4, 403 HS_PLL_FAST_PATH = BITS(14:0), 404 HS_PLL_SLOW_PATH = BITS(30:16), 405 406 // Video Decoder Comb Filter 407 VIP_COMB_CNTL0 = 0x0440, 408 COMB_HCK = BITS(7:0), 409 COMB_VCK = BITS(15:8), 410 COMB_FILTER_EN = BITS(16:16), // 0=fast AGC, CLAMP, and Chroma AGC loops (A41 ASIC only) 411 COMB_ADAPTIVE_EN = BITS(17:17), 412 COMB_BPFMUXSEL = BITS(20:18), 413 COMB_COUTSEL = BITS(22:21), 414 COMB_SUMDIFF0SEL = BITS(23:23), 415 COMB_SUMDIFF1SEL = BITS(25:24), 416 COMB_YVLPFSEL = BITS(26:26), 417 COMB_DLYLINESEL = BITS(28:27), 418 COMB_YDLYINSEL = BITS(30:29), 419 COMB_YSUBBW = BITS(31:31), 420 421 VIP_COMB_CNTL1 = 0x0444, 422 COMB_YDLYOUTSEL = BITS(1:0), 423 COMB_CORESIZE = BITS(3:2), 424 COMB_YSUBEN = BITS(4:4), 425 COMB_YOUTSEL = BITS(5:5), 426 COMB_SYNCLPFSEL = BITS(7:6), 427 COMB_SYNCLPFRST = BITS(8:8), 428 COMB_DEBUG = BITS(9:9), 429 430 VIP_COMB_CNTL2 = 0x0448, 431 COMB_HYK0 = BITS(7:0), 432 COMB_VYK0 = BITS(15:8), 433 COMB_HYK1 = BITS(23:16), 434 COMB_VYK1 = BITS(31:24), 435 436 VIP_COMB_LINE_LENGTH = 0x044c, 437 COMB_TAP0LENGTH = BITS(10:0), 438 COMB_TAP1LENGTH = BITS(27:16), 439 440 VIP_NOISE_CNTL0 = 0x0450, 441 NR_EN = BITS(0:0), 442 NR_GAIN_CNTL = BITS(3:1), 443 NR_BW_TRESH = BITS(9:4), 444 NR_GC_TRESH = BITS(14:10), 445 NR_COEF_DESPEC_IMODE = BITS(15:15), 446 447 // Video Decoder ADC Control 448 VIP_ADC_CNTL = 0x0400, 449 INPUT_SELECT = BITS(2:0), // Video input mux select 450 INPUT_SELECT_COMP0 = 0 << 0, // Tuner 451 INPUT_SELECT_COMP1 = 1 << 0, // Front Comp1 452 INPUT_SELECT_COMP2 = 2 << 0, // Rear Comp1 453 INPUT_SELECT_YF_COMP3 = 3 << 0, // Front Comp2 454 INPUT_SELECT_YR_COMP4 = 4 << 0, // Rear Comp2 455 INPUT_SELECT_YCF_COMP3 = 5 << 0, // Front YC 456 INPUT_SELECT_YCR_COMP4 = 6 << 0, // Rear YC 457 I_CLAMP_SEL = BITS(4:3), // Clamp charge-pump current select 458 I_CLAMP_SEL_0_3 = 0 << 3, // 0.3 uA 459 I_CLAMP_SEL_7 = 1 << 3, // 7.0 uA 460 I_CLAMP_SEL_15 = 2 << 3, // 15.0 uA 461 I_CLAMP_SEL_22 = 3 << 3, // 22.0 uA 462 I_AGC_SEL = BITS(6:5), // AGC charge-pump current select 463 I_AGC_SEL_0_3 = 0 << 5, // 0.3 uA 464 I_AGC_SEL_7 = 1 << 5, // 7.0 uA 465 I_AGC_SEL_15 = 2 << 5, // 15.0 uA 466 I_AGC_SEL_22 = 3 << 5, // 22.0 uA 467 ADC_PDWN = BITS(7:7), // AGC power-down select 468 ADC_PDWN_UP = 0 << 7, // Power up (for capture mode) 469 ADC_PDWN_DOWN = 1 << 7, // Power down 470 EXT_CLAMP_CAP = BITS(8:8), // Clamp charge cap select 471 EXT_CLAMP_CAP_INTERNAL = 0 << 8, // Use internal Clamp Cap. 472 EXT_CLAMP_CAP_EXTERNAL = 1 << 8, // Use external Clamp Cap. 473 EXT_AGC_CAP = BITS(9:9), // AGC charge Cap. select 474 EXT_AGC_CAP_INTERNAL = 0 << 9, // Use internal AGC Cap. 475 EXT_AGC_CAP_EXTERNAL = 1 << 9, // Use external AGC Cap. 476 ADC_DECI_BYPASS = BITS(10:10), // ADC video data decimation filter select 477 ADC_DECI_WITH_FILTER = 0 << 10, // Decimate ADC data with filtering 478 ADC_DECI_WITHOUT_FILTER = 1 << 10, // Decimate ADC data with no filtering 479 VBI_DECI_BYPASS = BITS(11:11), // ADC VBI data decimation filter select 480 VBI_DECI_WITH_FILTER = 0 << 11, // Decimate VBI data from ADC with filtering 481 VBI_DECI_WITHOUT_FILTER = 1 << 11, // Decimate VBI data from ADC with no filtering 482 DECI_DITHER_EN = BITS(12:12), // Decimation filter output dither enable 483 ADC_CLK_SEL = BITS(13:13), // ADC clock select 484 ADC_CLK_SEL_4X = 0 << 13, // Run ADC at 4x Fsc 485 ADC_CLK_SEL_8X = 1 << 13, // Run ADC at 8x Fsc 486 ADC_BYPASS = BITS(15:14), // ADC data path select 487 ADC_BYPASS_INTERNAL = 0 << 14, // Use internal ADC 488 ADC_BYPASS_EXTERNAL = 1 << 14, // Use external ADC 489 ADC_BYPASS_SINGLE = 2 << 14, // Use single step data 490 ADC_CH_GAIN_SEL = BITS(17:16), // Analog Chroma gain select 491 ADC_CH_GAIN_SEL_NTSC = 0 << 16, // Set chroma gain for NTSC 492 ADC_CH_GAIN_SEL_PAL = 1 << 16, // Set chroma gain for PAL 493 ADC_PAICM = BITS(19:18), // AMP common mode voltage select 494 ADC_PDCBIAS = BITS(21:20), // DC 1.5V bias programmable select 495 ADC_PREFHI = BITS(23:22), // ADC voltage reference high 496 ADC_PREFHI_2_7 = 0 << 22, // 2.7V (recommended) 497 ADC_PREFHI_2_6 = 1 << 22, // 2.6V 498 ADC_PREFHI_2_5 = 2 << 22, // 2.5V 499 ADC_PREFHI_2_4 = 3 << 22, // 2.4V 500 ADC_PREFLO = BITS(25:24), // ADC voltage reference low 501 ADC_PREFLO_1_8 = 0 << 24, // 1.8V 502 ADC_PREFLO_1_7 = 1 << 24, // 1.7V 503 ADC_PREFLO_1_6 = 2 << 24, // 1.6V 504 ADC_PREFLO_1_5 = 3 << 24, // 1.5V (recommended) 505 ADC_IMUXOFF = BITS(26:26), 506 ADC_CPRESET = BITS(27:27), // AGC charge pump reset 507 508 VIP_ADC_DEBUG = 0x0404, 509 ADC_PTST = BITS(0:0), // AGC test mode enable 510 ADC_PYPDN = BITS(1:1), 511 ADC_PCPDN = BITS(2:2), // Chroma AGC path power down mode 512 ADC_PTSTA0 = BITS(3:3), // AGC test mux A select bit 0 513 ADC_PTSTA1 = BITS(4:4), // AGC test mux A select bit 1 514 ADC_PTSTB0 = BITS(5:5), // AGC test mux B select bit 0 515 ADC_PTSTB1 = BITS(6:6), // AGC test mux B select bit 1 516 ADC_TSTADC = BITS(7:7), // Luma & Chroma ADC test mode 517 ADC_TSTPROBEY = BITS(8:8), // Luma AGC/ADC test mode 518 ADC_TSTPROBEC = BITS(9:9), // Chroma AGC/ADC test mode 519 ADC_TSTPROBEADC = BITS(10:10), // Chroma ADC test structure probe mode 520 ADC_TSTADCBIAS = BITS(11:11), // Chroma ADC bias node probe mode 521 ADC_TSTADCREFM = BITS(12:12), // Middle reference point for Luma & Chroma ADC probe 522 ADC_TSTADCFBP = BITS(13:13), // Chroma ADC folding block positive output probe mode 523 ADC_TSTADCFBN = BITS(14:14), // Chroma ADC folding block negative output probe mode 524 ADC_TSTADCCMP1 = BITS(15:15), // Chroma ADC comparator #1 output probe mode 525 ADC_TSTADCCMP9 = BITS(16:16), // Chroma ADC comparator #9 output probe mode 526 ADC_TSTADCCMP17 = BITS(17:17), // Chroma ADC comparator #19 output probe mode 527 ADC_TSTADCLATCH = BITS(18:18), // Dummy latch test mode 528 ADC_TSTADCCOMP = BITS(19:19), // Dummy comparator test mode 529 530 VIP_THERMO2BIN_STATUS = 0x040c, 531 YOVERFLOW = BITS(0:0), 532 YUNDERFLOW = BITS(1:1), 533 YMSB_LOW_BY_ONE = BITS(2:2), 534 YMSB_HI_BY_ONE = BITS(3:3), 535 COVERFLOW = BITS(4:4), 536 CUNDERFLOW = BITS(5:5), 537 CMSB_LOW_BY_ONE = BITS(6:6), 538 CMSB_HI_BY_ONE = BITS(7:7), 539 540 // Video Decoder Sync Generator 541 VIP_SG_BLACK_GATE = 0x04c0, // horizontal blank 542 BLANK_INT_START = BITS(7:0), // start of horizontal blank (49) 543 BLANK_INT_LENGTH = BITS(11:8), 544 545 VIP_SG_SYNCTIP_GATE = 0x04c4, // synctip pulse 546 SYNC_TIP_START = BITS(10:0), // start of sync pulse (882) 547 SYNC_TIP_LENGTH = BITS(15:12), 548 549 VIP_SG_UVGATE_GATE = 0x04c8, // chroma burst 550 UV_INT_START = BITS(7:0), // start of chroma burst (59) 551 U_INT_LENGTH = BITS(11:8), 552 V_INT_LENGTH = BITS(15:12), 553 554 // Video Decoder Luminance Processor 555 VIP_LP_AGC_CLAMP_CNTL0 = 0x0500, // Luma AGC Clamp control 556 SYNCTIP_REF0 = BITS(7:0), // 40 IRE reference 557 SYNCTIP_REF1 = BITS(15:8), 558 CLAMP_REF = BITS(23:16), 559 AGC_PEAKWHITE = BITS(31:24), 560 561 VIP_LP_AGC_CLAMP_CNTL1 = 0x0504, // Luma AGC Clamp control 562 VBI_PEAKWHITE = BITS(7:0), // 563 CLAMPLOOP_EN = BITS(24:24), // Run Clamp loop 564 CLAMPLOOP_INV = BITS(25:25), // Negative Clamp Loop 565 AGCLOOP_EN = BITS(26:26), // Run AGC loop 566 AGCLOOP_INV = BITS(27:27), // Negative AGC loop 567 568 VIP_LP_BRIGHTNESS = 0x0508, // Luma Brightness control 569 BRIGHTNESS = BITS(13:0), // Brightness level 570 LUMAFLT_SEL = BITS(15:15), // Select flat filter 571 572 VIP_LP_CONTRAST = 0x050c, // Luma Contrast level 573 CONTRAST = BITS(7:0), // Contrast level 574 DITHER_SEL = BITS(9:8), // Dither selection 575 DITHER_SEL_TRUNC = 0 << 8, // Truncation 576 DITHER_SEL_ROUND = 1 << 8, // Round 577 DITHER_SEL_4BIT = 2 << 8, // 4 bit error 578 DITHER_SEL_9BIT = 3 << 9, // 9 bit error 579 580 VIP_LP_SLICE_LIMIT = 0x0510, 581 SLICE_LIMIT_HI = BITS(7:0), 582 SLICE_LIMIT_LO = BITS(15:8), 583 SLICE_LIMIT = BITS(23:16), 584 585 VIP_LP_WPA_CNTL0 = 0x0514, 586 WPA_THRESHOLD = BITS(10:0), 587 588 VIP_LP_WPA_CNTL1 = 0x0518, 589 WPA_TRIGGER_LO = BITS(9:0), 590 WPA_TRIGGER_HI = BITS(25:16), 591 592 VIP_LP_BLACK_LEVEL = 0x051c, 593 BLACK_LEVEL = BITS(12:0), 594 595 VIP_LP_SLICE_LEVEL = 0x0520, 596 SLICE_LEVEL = BITS(7:0), 597 598 VIP_LP_SYNCTIP_LEVEL = 0x0524, 599 SYNCTIP_LEVEL = BITS(12:0), 600 601 VIP_LP_VERT_LOCKOUT = 0x0528, 602 LP_LOCKOUT_START = BITS(9:0), 603 LP_LOCKOUT_END = BITS(25:16), 604 605 // Video Decoder Vertical Sync Detector/Counter 606 VIP_VS_DETECTOR_CNTL = 0x0540, 607 VSYNC_INT_TRIGGER = BITS(10:0), 608 VSYNC_INT_HOLD = BITS(26:16), 609 610 VIP_VS_BLANKING_CNTL = 0x0544, 611 VS_FIELD_BLANK_START = BITS(9:0), 612 VS_FIELD_BLANK_END = BITS(25:16), 613 614 VIP_VS_FIELD_ID_CNTL = 0x0548, 615 VS_FIELD_ID_LOCATION = BITS(8:0), 616 617 VIP_VS_COUNTER_CNTL = 0x054c, // Vertical Sync Counter control 618 FIELD_DETECT_MODE = BITS(1:0), // Field detection mode 619 FIELD_DETECT_ARTIFICIAL = 0 << 0, // Use artificial field 620 FIELD_DETECT_DETECTED = 1 << 0, // Use detected field 621 FIELD_DETECT_AUTO = 2 << 0, // Auto switch to Artificial if interlace is lost 622 FIELD_DETECT_FORCE = 3 << 0, // Use field force bit 623 FIELD_FLIP_EN = BITS(2:2), // Flip the fields 624 FIELD_FORCE_EN = BITS(3:3), // Force field number 625 VSYNC_WINDOW_EN = BITS(4:4), // Enable VSYNC window 626 627 VIP_VS_FRAME_TOTAL = 0x0550, 628 VS_FRAME_TOTAL = BITS(9:0), // number of lines per frame 629 630 VIP_VS_LINE_COUNT = 0x0554, 631 VS_LINE_COUNT = BITS(9:0), // current line counter 632 VS_ITU656_VB = BITS(13:13), 633 VS_ITU656_FID = BITS(14:14), 634 VS_INTERLACE_DETECTED = BITS(15:15), 635 VS_DETECTED_LINES = BITS(25:16), // detected number of lines per frame 636 CURRENT_FIELD = BITS(27:27), // current field number (odd or even) 637 PREVIOUS_FIELD = BITS(28:28), // previous field number (odd or even) 638 ARTIFICIAL_FIELD = BITS(29:29), 639 VS_WINDOW_COUNT = BITS(31:30), 640 641 // Video Decoder Chroma Processor 642 VIP_CP_PLL_CNTL0 = 0x0580, 643 CH_DTO_INC = BITS(23:0), 644 CH_PLL_SGAIN = BITS(27:24), 645 CH_PLL_FGAIN = BITS(31:28), 646 647 VIP_CP_PLL_CNTL1 = 0x0584, 648 VFIR = BITS(0:0), // 0=disable, 1=enable phase filter FIR 649 PFLIP = BITS(1:1), // 0=Use PAL/SECAM Vswitch as detected 650 // 1=Flip detected PAL/SECAM Vswitch 651 PFILT = BITS(2:2), // 0=Use sign bit of phase error for PAL Vswitch 652 // 1=Use PAL Vswitch filter 653 654 VIP_CP_HUE_CNTL = 0x0588, 655 HUE_ADJ = BITS(7:0), // Hue adjustment 656 657 VIP_CP_BURST_GAIN = 0x058c, 658 CR_BURST_GAIN = BITS(8:0), 659 CB_BURST_GAIN = BITS(24:16), 660 661 VIP_CP_AGC_CNTL = 0x0590, 662 CH_HEIGHT = BITS(7:0), 663 CH_KILL_LEVEL = BITS(15:8), 664 CH_AGC_ERROR_LIM = BITS(17:16), // Force error to 0, 1, 2 or 3 665 CH_AGC_FILTER_EN = BITS(18:18), // 0=disable, 1=enable filter 666 CH_AGC_LOOP_SPEED = BITS(19:19), // 0=slow, 1=fast 667 668 VIP_CP_ACTIVE_GAIN = 0x0594, 669 CRDR_ACTIVE_GAIN = BITS(9:0), // Saturation adjustment 670 CBDB_ACTIVE_GAIN = BITS(25:16), 671 672 VIP_CP_PLL_STATUS0 = 0x0598, 673 CH_GAIN_ACC0 = BITS(13:0), 674 CH_GAIN_ACC1 = BITS(29:16), 675 676 VIP_CP_PLL_STATUS1 = 0x059c, 677 CH_VINT_OUT = BITS(18:0), 678 679 VIP_CP_PLL_STATUS2 = 0x05a0, 680 CH_UINT_OUT = BITS(12:0), 681 CH_VSWITCH = BITS(16:16), 682 CH_SECAM_SWITCH = BITS(17:17), 683 CH_PAL_SWITCH = BITS(18:18), 684 CH_PAL_FLT_STAT = BITS(21:19), 685 CH_COLOR_KILL = BITS(22:22), 686 687 VIP_CP_PLL_STATUS3 = 0x05a4, 688 CH_ERROR_INT0 = BITS(20:0), 689 690 VIP_CP_PLL_STATUS4 = 0x05a8, 691 CH_ERROR_INT1 = BITS(20:0), 692 693 VIP_CP_PLL_STATUS5 = 0x05ac, 694 CH_FAST_PATH = BITS(24:0), 695 696 VIP_CP_PLL_STATUS6 = 0x05b0, 697 CH_SLOW_PATH = BITS(24:0), 698 699 VIP_CP_PLL_STATUS7 = 0x05b4, 700 FIELD_BPHASE_COUNT = BITS(5:0), 701 BPHASE_BURST_COUNT = BITS(13:8), 702 703 VIP_CP_DEBUG_FORCE = 0x05b8, 704 GAIN_FORCE_DATA = BITS(11:0), 705 GAIN_FORCE_EN = BITS(12:12), // 0=disable, 1==enable force chroma gain 706 707 VIP_CP_VERT_LOCKOUT = 0x05bc, 708 CP_LOCKOUT_START = BITS(9:0), 709 CP_LOCKOUT_END = BITS(25:16), 710 711 // Video Decoder Clip Engine and VBI Control 712 VIP_H_ACTIVE_WINDOW = 0x05c0, 713 H_ACTIVE_START = BITS(10:0), // Horizotal active window 714 H_ACTIVE_END = BITS(26:16), 715 716 VIP_V_ACTIVE_WINDOW = 0x05c4, 717 V_ACTIVE_START = BITS(9:0), // Vertical active window 718 V_ACTIVE_END = BITS(25:16), 719 720 VIP_H_VBI_WINDOW = 0x05c8, 721 H_VBI_WIND_START = BITS(10:0), // Horizontal VBI window 722 H_VBI_WIND_END = BITS(26:16), 723 724 VIP_V_VBI_WINDOW = 0x05cc, 725 V_VBI_WIND_START = BITS(9:0), // Vertical VBI window 726 V_VBI_WIND_END = BITS(25:16), 727 728 VIP_VBI_CONTROL = 0x05d0, 729 VBI_CAPTURE_ENABLE = BITS(1:0), // Select VBI capture 730 VBI_CAPTURE_DIS = 0 << 0, // Disable VBI capture 731 VBI_CAPTURE_EN = 1 << 0, // Enable VBI capture 732 VBI_CAPTURE_RAW = 2 << 0, // Enable Raw Video capture 733 734 735 // Video Decoder Standard 736 VIP_STANDARD_SELECT = 0x0408, 737 STANDARD_SEL = BITS(1:0), // Select video standard 738 STANDARD_NTSC = 0 << 0, // NTSC 739 STANDARD_PAL = 1 << 0, // PAL 740 STANDARD_SECAM = 2 << 0, // SECAM 741 YC_MODE = BITS(2:2), // Select YC video mode 742 YC_MODE_COMPOSITE = 0 << 2, // Composite 743 YC_MODE_SVIDEO = 1 << 2, // SVideo 744 745 // Video In Scaler and DVS Port 746 VIP_SCALER_IN_WINDOW = 0x0618, // Scaler In Window 747 H_IN_WIND_START = BITS(10:0), // Horizontal start 748 V_IN_WIND_START = BITS(25:16), // Vertical start 749 750 VIP_SCALER_OUT_WINDOW = 0x061c, // Scaler Out Window 751 H_OUT_WIND_WIDTH = BITS(9:0), // Horizontal output window width 752 V_OUT_WIND_HEIGHT = BITS(24:16), // Vertical output window height 753 754 VIP_H_SCALER_CONTROL = 0x0600, // Horizontal Scaler control 755 H_SCALE_RATIO = BITS(20:0), // Horizontal scale ratio (5.16 fixed point) 756 H_SHARPNESS = BITS(28:25), // Sharpness control (15=6dB high frequency boost) 757 H_BYPASS = BITS(30:30), // Horizontal bypass enable 758 759 VIP_V_SCALER_CONTROL = 0x0604, // Vertical Scaler control 760 V_SCALE_RATIO = BITS(11:0), // Vertical scaling ratio (1.11 fixed point) 761 V_DEINTERLACE_ON = BITS(12:12), // Enable deinterlacing 762 V_FIELD_FLIP = BITS(13:13), // Invert field flag 763 V_BYPASS = BITS(14:14), // Enable vertical bypass 764 V_DITHER_ON = BITS(15:15), // Vertical path dither enable 765 766 VIP_V_DEINTERLACE_CONTROL = 0x0608, // Deinterlace control 767 EVENF_OFFSET = BITS(10:0), // Even Field offset 768 ODDF_OFFSET = BITS(21:11), // Odd Field offset 769 770 VIP_VBI_SCALER_CONTROL = 0x060c, // VBI Scaler control 771 VBI_SCALING_RATIO = BITS(16:0), // Scaling ratio for VBI data (1.16 fixed point) 772 VBI_ALIGNER_ENABLE = BITS(17:17), // VBI/Raw data aligner enable 773 774 VIP_DVS_PORT_CTRL = 0x0610, // DVS Port control 775 DVS_DIRECTION = BITS(0:0), // DVS direction 776 DVS_DIRECTION_INPUT = 0 << 0, // Input mode 777 DVS_DIRECTION_OUTPUT = 1 << 0, // Output mode 778 DVS_VBI_BYTE_SWAP = BITS(1:1), // Output video stream type 779 DVS_VBI_BYTE_SEQUENTIAL = 0 << 1, // Sequential 780 DVS_VBI_BYTE_SWAPPED = 1 << 1, // Byte swapped 781 DVS_CLK_SELECT = BITS(2:2), // DVS output clock select 782 DVS_CLK_SELECT_8X = 0 << 2, // 8x Fsc 783 DVS_CLK_SELECT_27MHz = 1 << 2, // 27 MHz 784 CONTINUOUS_STREAM = BITS(3:3), // Enable continuous stream mode 785 DVSOUT_CLK_DRV = BITS(4:4), // 0=high, 1=low DVS port output clock buffer drive strength 786 DVSOUT_DATA_DRV = BITS(5:5), // 0=high, 1=low DVS port output data buffers driver strength 787 788 VIP_DVS_PORT_READBACK = 0x0614, // DVS Port readback 789 DVS_OUTPUT_READBACK = BITS(7:0), // Data from DVS port fifo 790 791 // Clock and Reset Control 792 VIP_CLKOUT_GPIO_CNTL = 0x0038, 793 CLKOUT0_SEL = BITS(2:0), // Select output to CLKOUT0_GPIO0 pin 794 CLKOUT0_SEL_REF_CLK = 0 << 0, // Reference Clock 795 CLKOUT0_SEL_L54_CLK = 1 << 0, // Lockable 54 MHz Clock 796 CLKOUT0_SEL_AUD_CLK = 2 << 0, // Audio Source Clock 797 CLKOUT0_SEL_DIV_AUD_CLK = 3 << 0, // Divided Audio Source Clock 798 CLKOUT0_SEL_BYTE_CLK = 4 << 0, // Byte Clock 799 CLKOUT0_SEL_PIXEL_CLK = 5 << 0, // Pixel Clock 800 CLKOUT0_SEL_TEST_MUX = 6 << 0, // Clock Test Mux Output 801 CLKOUT0_SEL_GPIO0_OUT = 7 << 0, // GPIO0_OUT 802 CLKOUT0_DRV = BITS(3:3), // Set drive strength for CLKOUT0_GPIO0 pin 803 CLKOUT0_DRV_8mA = 0 << 3, // 8 mA 804 CLKOUT0_DRV_4mA = 1 << 3, // 4 mA 805 CLKOUT1_SEL = BITS(6:4), // Select output to CLKOUT1_GPIO1 pin 806 CLKOUT1_SEL_REF_CLK = 0 << 4, // Reference Clock 807 CLKOUT1_SEL_L54_CLK = 1 << 4, // Lockable 54 MHz Clock 808 CLKOUT1_SEL_AUD_CLK = 2 << 4, // Audio Source Clock 809 CLKOUT1_SEL_DIV_AUD_CLK = 3 << 4, // Divided Audio Source Clock 810 CLKOUT1_SEL_PIXEL_CLK = 4 << 4, // Pixel Clock 811 CLKOUT1_SEL_SPDIF_CLK = 5 << 4, // SPDIF Clock 812 CLKOUT1_SEL_REG_CLK = 6 << 4, // Register Clock 813 CLKOUT1_SEL_GPIO1_OUT = 7 << 4, // GPIO1_OUT 814 CLKOUT1_DRV = BITS(7:7), // Set drive strength for CLKOUT1_GPIO1 pin 815 CLKOUT1_DRV_8mA = 0 << 7, // 8 mA 816 CLKOUT1_DRV_4mA = 1 << 7, // 4 mA 817 CLKOUT2_SEL = BITS(10:8), // Select output to CLKOUT2_GPIO2 pin 818 CLKOUT2_SEL_REF_CLK = 0 << 0, // Reference Clock 819 CLKOUT2_SEL_L54_CLK = 1 << 0, // Lockable 54 MHz Clock 820 CLKOUT2_SEL_AUD_CLK = 2 << 0, // Audio Source Clock 821 CLKOUT2_SEL_DIV_AUD_CLK = 3 << 0, // Divided Audio Source Clock 822 CLKOUT2_SEL_VIN_CLK = 4 << 0, // Video In Clock 823 CLKOUT2_SEL_VIN_SC_CLK = 5 << 0, // Video In Scaler Clock 824 CLKOUT2_SEL_TV_CLK = 6 << 0, // TV Clock 825 CLKOUT2_SEL_GPIO2_OUT = 7 << 0, // GPIO2_OUT 826 CLKOUT2_DRV = BITS(11:11), // Set drive strength for CLKOUT2_GPIO2 pin 827 CLKOUT2_DRV_8mA = 0 << 11, // 8 mA 828 CLKOUT2_DRV_4mA = 1 << 11, // 4 mA 829 CLKOUT1_DIV = BITS(23:16), // Postdivider for CLKOUT1 830 CLKOUT2_DIV = BITS(31:24), // Postdivider for CLKOUT2 831 832 VIP_MASTER_CNTL = 0x0040, // Master control 833 TV_ASYNC_RST = BITS(0:0), // Reset several blocks that use the TV Clock 834 CRT_ASYNC_RST = BITS(1:1), // Reset several blocks that use the CRT Clock 835 RESTART_PHASE_FIX = BITS(3:3), // 836 TV_FIFO_ASYNC_RST = BITS(4:4), // 837 VIN_ASYNC_RST = BITS(5:5), // Reset several blocks that use the VIN, ADC or SIN Clock 838 AUD_ASYNC_RST = BITS(6:6), // Reset several blocks that use the SPDIF or I2S Clock 839 DVS_ASYNC_RST = BITS(7:7), // Reset several blocks that use the DVSOUT Clock 840 CLKOUT_CLK_SEL = BITS(8:8), // External BYTE clock 841 CRT_FIFO_CE_EN = BITS(9:9), // 842 TV_FIFO_CE_EN = BITS(10:10), 843 844 VIP_CLKOUT_CNTL = 0x004c, 845 CLKOUT_OE = BITS(0:0), 846 CLKOUT_PUB = BITS(3:3), 847 CLKOUT_PD = BITS(4:4), 848 CLKOUT_DRV = BITS(5:5), 849 850 VIP_TV_PLL_CNTL = 0x00c0, 851 TV_M0_LO = BITS(7:0), 852 TV_N0_LO = BITS(16:8), 853 TV_M0_HI = BITS(20:18), 854 TV_N0_HI = BITS(22:21), 855 TV_SLIP_EN = BITS(23:23), 856 TV_P = BITS(27:24), 857 TV_DTO_EN = BITS(28:28), 858 TV_DTO_TYPE = BITS(29:29), 859 TV_REF_CLK_SEL = BITS(31:30), 860 861 VIP_CRT_PLL_CNTL = 0x00c4, 862 CRT_M0_LO = BITS(7:0), 863 CRT_N0_LO = BITS(16:8), 864 CRT_M0_HI = BITS(20:18), 865 CRT_N0_HI = BITS(22:21), 866 CRTCLK_USE_CLKBY2 = BITS(25:25), 867 CRT_MNFLIP_EN = BITS(26:26), 868 CRT_SLIP_EN = BITS(27:27), 869 CRT_DTO_EN = BITS(28:28), 870 CRT_DTO_TYPE = BITS(29:29), 871 CRT_REF_CLK_SEL = BITS(31:30), 872 873 VIP_PLL_CNTL0 = 0x00c8, 874 TVRST = BITS(1:1), 875 CRTRST = BITS(2:2), 876 TVSLEEPB = BITS(3:3), 877 CRTSLEEPB = BITS(4:4), 878 TVPCP = BITS(10:8), 879 TVPVG = BITS(12:11), 880 TVPDC = BITS(15:13), 881 CRTPCP = BITS(18:16), 882 CRTPVG = BITS(20:19), 883 CRTPDC = BITS(23:21), 884 CKMONEN = BITS(24:24), 885 886 VIP_PLL_TEST_CNTL = 0x00cc, 887 PLL_TEST = BITS(0:0), 888 PLL_TST_RST = BITS(1:1), 889 PLL_TST_DIV = BITS(2:2), 890 PLL_TST_CNT_RST = BITS(3:3), 891 STOP_REF_CLK = BITS(7:7), 892 PLL_TST_SEL = BITS(13:8), 893 PLL_TEST_COUNT = BITS(31:16), 894 895 VIP_CLOCK_SEL_CNTL = 0x00d0, 896 TV_CLK_SEL = BITS(0:0), 897 CRT_CLK_SEL = BITS(1:1), 898 BYT_CLK_SEL = BITS(3:2), 899 PIX_CLK_SEL = BITS(4:4), 900 REG_CLK_SEL = BITS(5:5), 901 TST_CLK_SEL = BITS(6:6), 902 VIN_CLK_SEL = BITS(7:7), // Select VIN clock 903 VIN_CLK_SEL_REF_CLK = 0 << 7, // Select reference clock 904 VIN_CLK_SEL_VIPLL_CLK = 1 << 7, // Select VIN PLL clock 905 BYT_CLK_DEL = BITS(10:8), 906 AUD_CLK_SEL = BITS(11:11), 907 L54_CLK_SEL = BITS(12:12), 908 MV_ZONE_1_PHASE = BITS(13:13), 909 MV_ZONE_2_PHASE = BITS(14:14), 910 MV_ZONE_3_PHASE = BITS(15:15), 911 912 VIP_VIN_PLL_CNTL = 0x00d4, // VIN PLL control 913 VIN_M0 = BITS(10:0), // Reference divider 914 VIN_N0 = BITS(21:11), // Feedback divider 915 VIN_MNFLIP_EN = BITS(22:22), // M/N flip enable 916 VIN_P = BITS(27:24), // Post divider 917 VIN_REF_CLK_SEL = BITS(31:30), // VIN reference source select 918 VIN_REF_CLK = 0 << 30, // Reference clock 919 VIN_SEC_REF_CLK = 1 << 30, // Secondary Reference Clock 920 VIN_L54_CLK = 2 << 30, // L54 PLL Clock 921 VIN_SLIP_L54_CLK = 3 << 30, // Slippable L54 PLL Clock 922 923 VIP_VIN_PLL_FINE_CNTL = 0x00d8, 924 VIN_M1 = BITS(10:0), 925 VIN_N1 = BITS(21:11), 926 VIN_DIVIDER_SEL = BITS(22:22), 927 VIN_MNFLIP_REQ = BITS(23:23), 928 VIN_MNFLIP_DONE = BITS(24:24), 929 TV_LOCK_TO_VIN = BITS(27:27), 930 TV_P_FOR_VINCLK = BITS(31:28), 931 932 VIP_AUD_PLL_CNTL = 0x00e0, 933 AUD_M0 = BITS(10:0), 934 AUD_N0 = BITS(21:11), 935 AUD_MNFLIP_EN = BITS(22:22), 936 AUD_SLIP_EN = BITS(23:23), 937 AUD_P = BITS(27:24), 938 AUD_DTO_EN = BITS(28:28), 939 AUD_DTO_TYPE = BITS(29:29), 940 AUD_REF_CLK_SEL = BITS(31:30), 941 942 VIP_AUD_PLL_FINE_CNTL = 0x00e4, 943 AUD_M1 = BITS(10:0), 944 AUD_N1 = BITS(21:11), 945 AUD_DIVIDER_SEL = BITS(22:22), 946 AUD_MNFLIP_REQ = BITS(23:23), 947 AUD_MNFLIP_DONE = BITS(24:24), 948 AUD_SLIP_REQ = BITS(25:25), 949 AID_SLIP_DONE = BITS(26:26), 950 AUD_SLIP_COUNT = BITS(31:28), 951 952 VIP_AUD_CLK_DIVIDERS = 0x00e8, 953 SPDIF_P = BITS(3:0), 954 I2S_P = BITS(7:4), 955 DIV_AUD_P = BITS(11:8), 956 957 VIP_AUD_DTO_INCREMENTS = 0x00ec, 958 AUD_DTO_INC0 = BITS(15:0), 959 AUD_DTO_INC1 = BITS(31:16), 960 961 VIP_L54_PLL_CNTL = 0x00f0, 962 L54_M0 = BITS(7:0), 963 L54_N0 = BITS(21:11), 964 L54_MNFLIP_EN = BITS(22:22), 965 L54_SLIP_EN = BITS(23:23), 966 L54_P = BITS(27:24), 967 L54_DTO_EN = BITS(28:28), 968 L54_DTO_TYPE = BITS(29:29), 969 L54_REF_CLK_SEL = BITS(30:30), 970 971 VIP_L54_PLL_FINE_CNTL = 0x00f4, 972 L54_M1 = BITS(7:0), 973 L54_N1 = BITS(21:11), 974 L54_DIVIDER_SEL = BITS(22:22), 975 L54_MNFLIP_REQ = BITS(23:23), 976 L54_MNFLIP_DONE = BITS(24:24), 977 L54_SLIP_REQ = BITS(25:25), 978 L54_SLIP_DONE = BITS(26:26), 979 L54_SLIP_COUNT = BITS(31:28), 980 981 VIP_L54_DTO_INCREMENTS = 0x00f8, 982 L54_DTO_INC0 = BITS(15:0), 983 L54_DTO_INC1 = BITS(31:16), 984 985 VIP_PLL_CNTL1 = 0x00fc, 986 VINRST = BITS(1:1), // 0=active, 1=reset 987 AUDRST = BITS(2:2), 988 L54RST = BITS(3:3), 989 VINSLEEPB = BITS(4:4), 990 AUDSLEEPB = BITS(5:5), 991 L54SLEEPB = BITS(6:6), 992 VINPCP = BITS(10:8), 993 VINPVG = BITS(12:11), 994 VINPDC = BITS(15:13), 995 AUDPCP = BITS(18:16), 996 AUDPVG = BITS(20:19), 997 L54PCP = BITS(26:24), 998 L54PVG = BITS(28:27), 999 L54PDC = BITS(31:29), 1000 1001 // Audio Interfaces 1002 VIP_FIFOA_CONFIG = 0x0800, 1003 ENT_FIFOA = BITS(8:0), 1004 START_FIFOA = BITS(17:16), 1005 START_FIFOA_ADDR_0 = 0 << 16, 1006 START_FIFOA_ADDR_64 = 1 << 16, 1007 START_FIFOA_ADDR_128 = 2 << 16, 1008 START_FIFOA_ADDR_192 = 3 << 16, 1009 END_FIFOA = BITS(19:18), 1010 END_FIFOA_ADDR_63 = 0 << 18, 1011 END_FIFOA_ADDR_127 = 1 << 18, 1012 END_FIFOA_ADDR_191 = 2 << 18, 1013 END_FIFOA_ADDR_255 = 3 << 18, 1014 TEST_EN_FIFOA = BITS(20:20), 1015 RST_FIFOA = BITS(21:21), 1016 WT_FIFOA_FULL = BITS(22:22), 1017 EMPTY_FIFOA = BITS(23:23), 1018 1019 VIP_FIFOB_CONFIG = 0x0804, 1020 ENT_FIFOB = BITS(8:0), 1021 START_FIFOB = BITS(17:16), 1022 END_FIFOB = BITS(19:18), 1023 TEST_EN_FIFOB = BITS(20:20), 1024 RST_FIFOB = BITS(21:21), 1025 WT_FIFOB_FULL = BITS(22:22), 1026 EMPTY_FIFOB = BITS(23:23), 1027 1028 VIP_FIFOC_CONFIG = 0x0808, 1029 ENT_FIFOC = BITS(8:0), 1030 START_FIFOC = BITS(17:16), 1031 END_FIFOC = BITS(19:18), 1032 TEST_EN_FIFOC = BITS(20:20), 1033 RST_FIFOC = BITS(21:21), 1034 WT_FIFOC_FULL = BITS(22:22), 1035 EMPTY_FIFOC = BITS(23:23), 1036 1037 VIP_SPDIF_PORT_CNTL = 0x080c, 1038 SPDIF_PORT_EN = BITS(0:0), 1039 AC3_BURST_TRIGGER = BITS(1:1), 1040 AC3_BURST_ACTIVE = BITS(2:2), 1041 AC3_STREAM_MODE = BITS(3:3), 1042 SWAP_AC3_ORDER = BITS(4:4), 1043 TX_ON_NOT_EMPTY = BITS(5:5), 1044 SPDIF_UNDERFLOW_CLEAR = BITS(6:6), 1045 SPDIF_UNDERFLOW = BITS(7:7), 1046 SPDIF_UNDERFLOW_CNT = BITS(15:8), 1047 SPDIF_OE = BITS(16:16), 1048 SPDIF_DRV = BITS(19:19), 1049 PREAMBLE_AND_IDLE_SW = BITS(24:24), 1050 1051 VIP_SPDIF_CHANNEL_STAT = 0x0810, 1052 SPDIF_STATUS_BLOCK = BITS(0:0), 1053 SPDIF_DATA_TYPE = BITS(1:1), 1054 SPDIF_DIGITAL_COPY = BITS(2:2), 1055 SPDIF_PREEMPHASIS = BITS(5:3), 1056 SPDIF_MODE = BITS(7:6), 1057 SPDIF_CATEGORY = BITS(15:8), 1058 SPDIF_SRC_NUM = BITS(19:16), 1059 SPDIF_NUM_CHANNELS = BITS(23:20), 1060 SPDIF_SAMP_FREQ = BITS(27:24), 1061 SPDIF_CLOCK_ACC = BITS(29:28), 1062 1063 VIP_SPDIF_AC3_PREAMBLE = 0x0814, 1064 AC3_DATA_TYPE = BITS(4:0), 1065 AC3_ERR_FLAG = BITS(7:7), 1066 AC3_DATA_DEPEN = BITS(12:8), 1067 AC3_STREAM_NUM = BITS(15:13), 1068 AC3_LENGTH_CODE = BITS(31:16), 1069 1070 VIP_I2S_TRANSMIT_CNTL = 0x0818, 1071 IISTX_PORT_EN = BITS(0:0), 1072 IISTX_UNDERFLOW_CLEAR = BITS(6:6), 1073 IISTX_UNDERFLOW = BITS(7:7), 1074 IISTX_UNDERFLOW_FRAMES = BITS(15:8), 1075 IIS_BITS_PER_CHAN = BITS(21:16), 1076 IIS_SLAVE_EN = BITS(24:24), 1077 IIS_LOOPBACK_EN = BITS(25:25), 1078 ADO_OE = BITS(26:26), 1079 ADIO_OE = BITS(29:29), 1080 WS_OE = BITS(30:30), 1081 BITCLK_OE = BITS(31:31), 1082 1083 VIP_I2S_RECEIVE_CNTL = 0x081c, 1084 IISRX_PORT_EN = BITS(0:0), 1085 LOOPBACK_NO_UNDERFLOW = BITS(5:5), 1086 IISRX_OVERFLOW_CLEAR = BITS(6:6), 1087 IISRX_OVERFLOW = BITS(7:7), 1088 IISRX_OVERFLOW_FRAMES = BITS(15:8), 1089 1090 VIP_SPDIF_TX_CNT_REG = 0x0820, 1091 SPDIF_TX_CNT = BITS(23:0), 1092 SPDIF_TX_CNT_CLR = BITS(24:24), 1093 1094 VIP_IIS_TX_CNT_REG = 0x0824, 1095 IIS_TX_CNT = BITS(23:0), 1096 IIS_TX_CNT_CLR = BITS(24:24), 1097 1098 // Miscellaneous Registers 1099 VIP_HW_DEBUG = 0x0010, 1100 HW_DEBUG_TBD = BITS(15:0), 1101 1102 VIP_SW_SCRATCH = 0x0014, 1103 SW_SCRATCH_TBD = BITS(15:0), 1104 1105 VIP_I2C_CNTL_0 = 0x0020, 1106 I2C_DONE = BITS(0:0), 1107 I2C_NACK = BITS(1:1), 1108 I2C_HALT = BITS(2:2), 1109 I2C_SOFT_RST = BITS(5:5), 1110 SDA_DRIVE_EN = BITS(6:6), 1111 I2C_DRIVE_SEL = BITS(7:7), 1112 I2C_START = BITS(8:8), 1113 I2C_STOP = BITS(9:9), 1114 I2C_RECEIVE = BITS(10:10), 1115 I2C_ABORT = BITS(11:11), 1116 I2C_GO = BITS(12:12), 1117 I2C_PRESCALE = BITS(31:16), 1118 1119 VIP_I2C_CNTL_1 = 0x0024, 1120 I2C_DATA_COUNT = BITS(3:0), 1121 I2C_ADDR_COUNT = BITS(10:8), 1122 SCL_DRIVE_EN = BITS(16:16), 1123 I2C_SEL = BITS(17:17), 1124 I2C_TIME_LIMIT = BITS(31:24), 1125 1126 VIP_I2C_DATA = 0x0028, 1127 I2C_DATA = BITS(7:0), 1128 1129 VIP_INT_CNTL = 0x002c, 1130 I2C_INT_EN = BITS(0:0), 1131 SPDIF_UF_INT_EN = BITS(1:1), 1132 IISTX_UF_INT_EN = BITS(2:2), 1133 IISTX_OF_INT_EN = BITS(3:3), 1134 VIN_VSYNC_INT_EN = BITS(4:4), 1135 VIN_VACTIVE_END_INT_EN = BITS(5:5), 1136 VSYNC_DIFF_OVER_LIMIT_INT_EN= BITS(6:6), 1137 I2C_INT_AK = BITS(16:16), 1138 I2C_INT = BITS(16:16), 1139 SPDIF_UF_INT_AK = BITS(17:17), 1140 SPDIF_UF_INT = BITS(17:17), 1141 IISTX_UF_INT_AK = BITS(18:18), 1142 IISTX_UF_INT = BITS(18:18), 1143 IISRX_OF_INT_AK = BITS(19:19), 1144 IISRX_OF_INT = BITS(19:19), 1145 VIN_VSYNC_INT_AK = BITS(20:20), 1146 VIN_VSYNC_INT = BITS(20:20), 1147 VIN_VACTIVE_END_INT_AK = BITS(21:21), 1148 VIN_VACTIVE_END_INT = BITS(21:21), 1149 VSYNC_DIFF_OVER_LIMIT_INT_AK= BITS(22:22), 1150 VSYNC_DIFF_OVER_LIMIT_INT = BITS(22:22), 1151 1152 VIP_GPIO_INOUT = 0x0030, 1153 CLKOUT0_GPIO0_OUT = BITS(0:0), 1154 CLKOUT0_GPIO1_OUT = BITS(1:1), 1155 CLKOUT0_GPIO2_OUT = BITS(2:2), 1156 GPIO_6TO3_OUT = BITS(6:3), 1157 SPDIF_GPIO_OUT = BITS(7:7), 1158 ADO_GPIO_OUT = BITS(8:8), 1159 ADIO_GPIO_OUT = BITS(9:9), 1160 WS_GPIO_OUT = BITS(10:10), 1161 BITCLK_GPIO_OUT = BITS(11:11), 1162 HAD_GPIO_OUT = BITS(13:12), 1163 CLKOUT0_GPIO0_IN = BITS(16:16), 1164 CLKOUT0_GPIO1_IN = BITS(17:17), 1165 CLKOUT0_GPIO2_IN = BITS(18:18), 1166 GPIO_6TO3_IN = BITS(22:19), 1167 SPDIF_GPIO_IN = BITS(23:23), 1168 ADO_GPIO_IN = BITS(24:24), 1169 ADIO_GPIO_IN = BITS(25:25), 1170 WS_GPIO_IN = BITS(26:26), 1171 BITCLK_GPIO_IN = BITS(27:27), 1172 HAD_GPIO_IN = BITS(29:28), 1173 1174 VIP_GPIO_CNTL = 0x0034, 1175 CLKOUT0_GPIO0_OE = BITS(0:0), 1176 CLKOUT1_GPIO1_OE = BITS(1:1), 1177 CLKOUT2_GPIO2_OE = BITS(2:2), 1178 GPIO_6TO3_OE = BITS(6:3), 1179 SPDIF_GPIO_OE = BITS(7:7), 1180 ADO_GPIO_OE = BITS(8:8), 1181 ADIO_GPIO_OE = BITS(9:9), 1182 WS_GPIO_OE = BITS(10:10), 1183 BITCLK_GPIO_OE = BITS(11:11), 1184 HAD_GPIO_OE = BITS(13:12), 1185 GPIO_6TO1_STRAPS = BITS(22:17), 1186 1187 VIP_RIPINTF_PORT_CNTL = 0x003c, 1188 MPP_DATA_DRV = BITS(2:2), 1189 HAD_DRV = BITS(3:3), 1190 HCTL_DRV = BITS(4:4), 1191 SRDY_IRQb_DRV = BITS(5:5), 1192 SUB_SYS_ID_EN = BITS(16:16), 1193 1194 VIP_DECODER_DEBUG_CNTL = 0x05d4, 1195 CHIP_DEBUG_SEL = BITS(7:0), 1196 CHIP_DEBUG_EN = BITS(8:8), 1197 DECODER_DEBUG_SEL = BITS(15:12), 1198 1199 VIP_SINGLE_STEP_DATA = 0x05d8, 1200 SS_C = BITS(7:0), 1201 SS_Y = BITS(15:8), 1202 1203 VIP_I2C_CNTL = 0x0054, 1204 I2C_CLK_OE = BITS(0:0), 1205 I2C_CLK_OUT = BITS(1:1), 1206 I2C_CLK_IN = BITS(2:2), 1207 I2C_DAT_OE = BITS(4:4), 1208 I2C_DAT_OUT = BITS(5:5), 1209 I2C_DAT_IN = BITS(6:6), 1210 I2C_CLK_PUB = BITS(8:8), 1211 I2C_CLK_PD = BITS(9:9), 1212 I2C_CLK_DRV = BITS(10:10), 1213 I2C_DAT_PUB = BITS(12:12), 1214 I2C_DAT_PD = BITS(13:13), 1215 I2C_DAT_DRV = BITS(14:14), 1216 I2C_CLK_MX = BITS(19:16), 1217 I2C_DAT_MX = BITS(23:20), 1218 DELAY_TEST_MODE = BITS(25:24), 1219 1220 // Undocumented Registers 1221 VIP_TV_PLL_FINE_CNTL = 0x00b8, 1222 VIP_CRT_PLL_FINE_CNTL = 0x00bc, 1223 VIP_MV_MODE_CNTL = 0x0208, 1224 VIP_MV_STRIPE_CNTL = 0x020c, 1225 VIP_MV_LEVEL_CNTL1 = 0x0210, 1226 VIP_MV_LEVEL_CNTL2 = 0x0214, 1227 VIP_MV_STATUS = 0x0330, 1228 VIP_TV_DTO_INCREMENTS = 0x0390, 1229 VIP_CRT_DTO_INCREMENTS = 0x0394, 1230 VIP_VSYNC_DIFF_CNTL = 0x03a0, 1231 VIP_VSYNC_DIFF_LIMITS = 0x03a4, 1232 VIP_VSYNC_DIFF_RD_DATA = 0x03a8, 1233 1234 DSP_OK = 0x21, 1235 DSP_INVALID_PARAMETER = 0x22, 1236 DSP_MISSING_PARAMETER = 0x23, 1237 DSP_UNKNOWN_COMMAND = 0x24, 1238 DSP_UNSUCCESS = 0x25, 1239 DSP_BUSY = 0x26, 1240 DSP_RESET_REQUIRED = 0x27, 1241 DSP_UNKNOWN_RESULT = 0x28, 1242 DSP_CRC_ERROR = 0x29, 1243 DSP_AUDIO_GAIN_ADJ_FAIL = 0x2a, 1244 DSP_AUDIO_GAIN_CHK_ERROR = 0x2b, 1245 DSP_WARNING = 0x2c, 1246 DSP_POWERDOWN_MODE = 0x2d, 1247 1248 RT200_NTSC_M = 0x01, 1249 RT200_NTSC_433 = 0x03, 1250 RT200_NTSC_J = 0x04, 1251 RT200_PAL_B = 0x05, 1252 RT200_PAL_D = 0x06, 1253 RT200_PAL_G = 0x07, 1254 RT200_PAL_H = 0x08, 1255 RT200_PAL_I = 0x09, 1256 RT200_PAL_N = 0x0a, 1257 RT200_PAL_Ncomb = 0x0b, 1258 RT200_PAL_M = 0x0c, 1259 RT200_PAL_60 = 0x0d, 1260 RT200_SECAM = 0x0e, 1261 RT200_SECAM_B = 0x0f, 1262 RT200_SECAM_D = 0x10, 1263 RT200_SECAM_G = 0x11, 1264 RT200_SECAM_H = 0x12, 1265 RT200_SECAM_K = 0x13, 1266 RT200_SECAM_K1 = 0x14, 1267 RT200_SECAM_L = 0x15, 1268 RT200_SECAM_L1 = 0x16, 1269 RT200_480i = 0x17, 1270 RT200_480p = 0x18, 1271 RT200_576i = 0x19, 1272 RT200_720p = 0x1a, 1273 RT200_1080i = 0x1b 1274 1275 }; 1276 1277 1278 /* RT200 stuff there's no way I'm converting these to enums...*/ 1279 /* RT200 */ 1280 #define VIP_INT_CNTL__FB_INT0 0x02000000 1281 #define VIP_INT_CNTL__FB_INT0_CLR 0x02000000 1282 #define VIP_GPIO_INOUT 0x0030 1283 #define VIP_GPIO_CNTL 0x0034 1284 #define VIP_CLKOUT_GPIO_CNTL 0x0038 1285 #define VIP_RIPINTF_PORT_CNTL 0x003c 1286 1287 /* RT200 */ 1288 #define VIP_GPIO_INOUT 0x0030 1289 #define VIP_GPIO_CNTL 0x0034 1290 #define VIP_HOSTINTF_PORT_CNTL 0x003c 1291 #define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SN 0x00000008 1292 #define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SP 0x00000080 1293 #define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SR 0x00000100 1294 #define VIP_HOSTINTF_PORT_CNTL__SUB_SYS_ID_EN 0x00010000 1295 #define VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE 0x00300000 1296 #define VIP_HOSTINTF_PORT_CNTL__FIFOA_ENDIAN_SWAP 0x00c00000 1297 #define VIP_HOSTINTF_PORT_CNTL__FIFOB_ENDIAN_SWAP 0x03000000 1298 #define VIP_HOSTINTF_PORT_CNTL__FIFOC_ENDIAN_SWAP 0x0c000000 1299 #define VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP 0x30000000 1300 #define VIP_HOSTINTF_PORT_CNTL__FIFOE_ENDIAN_SWAP 0xc0000000 1301 1302 /* RT200 */ 1303 #define VIP_DSP_PLL_CNTL 0x0bc 1304 1305 /* RT200 */ 1306 #define VIP_TC_SOURCE 0x300 1307 #define VIP_TC_DESTINATION 0x304 1308 #define VIP_TC_COMMAND 0x308 1309 1310 /* RT200 */ 1311 #define VIP_TC_STATUS 0x030c 1312 #define VIP_TC_STATUS__TC_CHAN_BUSY 0x00007fff 1313 #define VIP_TC_STATUS__TC_WRITE_PENDING 0x00008000 1314 #define VIP_TC_STATUS__TC_FIFO_4_EMPTY 0x00040000 1315 #define VIP_TC_STATUS__TC_FIFO_6_EMPTY 0x00080000 1316 #define VIP_TC_STATUS__TC_FIFO_8_EMPTY 0x00100000 1317 #define VIP_TC_STATUS__TC_FIFO_10_EMPTY 0x00200000 1318 #define VIP_TC_STATUS__TC_FIFO_4_FULL 0x04000000 1319 #define VIP_TC_STATUS__TC_FIFO_6_FULL 0x08080000 1320 #define VIP_TC_STATUS__TC_FIFO_8_FULL 0x10080000 1321 #define VIP_TC_STATUS__TC_FIFO_10_FULL 0x20080000 1322 #define VIP_TC_STATUS__DSP_ILLEGAL_OP 0x80080000 1323 1324 /* RT200 */ 1325 #define VIP_TC_DOWNLOAD 0x0310 1326 #define VIP_TC_DOWNLOAD__TC_DONE_MASK 0x00003fff 1327 #define VIP_TC_DOWNLOAD__TC_RESET_MODE 0x00060000 1328 1329 /* RT200 */ 1330 #define VIP_FB_INT 0x0314 1331 #define VIP_FB_INT__INT_7 0x00000080 1332 #define VIP_FB_SCRATCH0 0x0318 1333 #define VIP_FB_SCRATCH1 0x031c 1334 1335 struct rt200_microc_head 1336 { 1337 unsigned int device_id; 1338 unsigned int vendor_id; 1339 unsigned int revision_id; 1340 unsigned int num_seg; 1341 }; 1342 1343 struct rt200_microc_seg 1344 { 1345 unsigned int num_bytes; 1346 unsigned int download_dst; 1347 unsigned int crc_val; 1348 1349 unsigned char* data; 1350 struct rt200_microc_seg* next; 1351 }; 1352 1353 1354 struct rt200_microc_data 1355 { 1356 struct rt200_microc_head microc_head; 1357 struct rt200_microc_seg* microc_seg_list; 1358 }; 1359 1360 #endif 1361