1 /* 2 * Copyright 2009, Colin Günther, coling@gmx.de. 3 * All Rights Reserved. Distributed under the terms of the MIT License. 4 */ 5 6 7 #include <sys/bus.h> 8 #include <sys/kernel.h> 9 10 #include <dev/pci/pcivar.h> 11 12 #include <machine/bus.h> 13 14 #include <net/if.h> 15 #include <net/if_media.h> 16 17 #include <net80211/ieee80211_var.h> 18 #include <net80211/ieee80211_amrr.h> 19 #include <net80211/ieee80211_ratectl.h> 20 21 #include <dev/ral/rt2560reg.h> 22 #include <dev/ral/rt2560var.h> 23 #include <dev/ral/rt2661var.h> 24 #include <dev/ral/rt2860reg.h> 25 #include <dev/ral/rt2860var.h> 26 27 28 HAIKU_FBSD_WLAN_DRIVER_GLUE(ralinkwifi, ral, pci) 29 HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE | FBSD_WLAN); 30 HAIKU_FIRMWARE_VERSION(0); 31 HAIKU_FIRMWARE_NAME_MAP(4) = { 32 {"rt2561fw", "rt2561.bin"}, 33 {"rt2561sfw", "rt2561s.bin"}, 34 {"rt2661fw", "rt2661.bin"}, 35 {"rt2860fw", "rt2860.bin"} 36 }; 37 38 NO_HAIKU_FBSD_MII_DRIVER(); 39 NO_HAIKU_REENABLE_INTERRUPTS(); 40 41 42 #define RT2661_INT_MASK_CSR 0x346c 43 #define RT2661_MCU_INT_MASK_CSR 0x0018 44 45 46 int 47 HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) 48 { 49 struct rt2560_softc* sc = (struct rt2560_softc*)device_get_softc(dev); 50 // sc_ifp is common between context data structures 51 52 switch (pci_get_device(dev)) { 53 case 0x0201: 54 // disable interrupts 55 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 56 57 if (!(sc->sc_flags & RT2560_F_RUNNING)) { 58 // don't re-enable interrupts if we're shutting down 59 return 0; 60 } 61 break; 62 case 0x0301: 63 case 0x0302: 64 case 0x0401: 65 // disable MAC and MCU interrupts 66 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 67 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 68 69 if (!(sc->sc_flags & RAL_RUNNING)) { 70 // don't re-enable interrupts if we're shutting down 71 return 0; 72 } 73 break; 74 default: 75 { 76 uint32 r; 77 struct rt2860_softc* sc = 78 (struct rt2860_softc*)device_get_softc(dev); 79 r = RAL_READ(sc, RT2860_INT_STATUS); 80 if (r == 0 || r == 0xffffffff) 81 return 0; 82 83 atomic_set((int32*)&sc->sc_intr_status, r); 84 break; 85 } 86 } 87 88 return 1; 89 } 90