xref: /haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/glue.c (revision 4a55cc230cf7566cadcbb23b1928eefff8aea9a2)
1 /*
2  * Copyright 2009, Colin Günther, coling@gmx.de. All rights reserved.
3  * Copyright 2018, Haiku, Inc. All rights reserved.
4  * Distributed under the terms of the MIT license.
5  */
6 
7 
8 #include <sys/bus.h>
9 #include <sys/kernel.h>
10 
11 #include <machine/bus.h>
12 
13 #include <net/if.h>
14 #include <net/if_media.h>
15 
16 #include <net80211/ieee80211_var.h>
17 #include <net80211/ieee80211_amrr.h>
18 #include <net80211/ieee80211_ratectl.h>
19 
20 #include <dev/iwn/if_iwnreg.h>
21 #include <dev/iwn/if_iwnvar.h>
22 
23 
24 HAIKU_FBSD_WLAN_DRIVER_GLUE(iprowifi4965, iwn, pci)
25 NO_HAIKU_FBSD_MII_DRIVER();
26 NO_HAIKU_REENABLE_INTERRUPTS();
27 HAIKU_DRIVER_REQUIREMENTS(FBSD_WLAN);
28 HAIKU_FIRMWARE_VERSION(44417);
29 HAIKU_FIRMWARE_NAME_MAP({
30 	{"iwn100fw", "iwlwifi-100-39.ucode"},
31 	{"iwn105fw", "iwlwifi-105-6-18.ucode"},
32 	{"iwn135fw", "iwlwifi-135-6-18.ucode"},
33 	{"iwn1000fw", "iwlwifi-1000-39.ucode"},
34 	{"iwn2000fw", "iwlwifi-2000-18.ucode"},
35 	{"iwn2030fw", "iwlwifi-2030-18.ucode"},
36 	{"iwn4965fw", "iwlwifi-4965-228.ucode"},
37 	{"iwn5000fw", "iwlwifi-5000-8.ucode"},
38 	{"iwn5150fw", "iwlwifi-5150-8.ucode"},
39 	{"iwn6000fw", "iwlwifi-6000-9.ucode"},
40 	{"iwn6000g2afw", "iwlwifi-6000g2a-18.ucode"},
41 	{"iwn6000g2bfw", "iwlwifi-6000g2b-18.ucode"},
42 	{"iwn6050fw", "iwlwifi-6050-41.ucode"}
43 });
44 
45 
46 int
47 HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
48 {
49 	struct iwn_softc* sc = (struct iwn_softc*)device_get_softc(dev);
50 	uint32 r1, r2;
51 
52 	/* Disable interrupts. */
53 	IWN_WRITE(sc, IWN_INT_MASK, 0);
54 
55 	r1 = IWN_READ(sc, IWN_INT);
56 	if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) {
57 		return 0; /* Hardware gone! */
58 	}
59 	r2 = IWN_READ(sc, IWN_FH_INT);
60 
61 	if (r1 == 0 && r2 == 0) {
62 		// not for us
63 		if (sc->sc_flags & IWN_FLAG_RUNNING)
64 			IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
65 		return 0;
66 	}
67 
68 	atomic_set((int32*)&sc->sc_intr_status_1, r1);
69 	atomic_set((int32*)&sc->sc_intr_status_2, r2);
70 
71 	return 1;
72 }
73