1 /* 2 * Copyright 2021, Adrien Destugues, pulkomandy@pulkomandy.tk 3 * Distributed under the terms of the MIT License. 4 */ 5 6 7 #include "vesa_private.h" 8 #include "vesa.h" 9 10 #include <SupportDefs.h> 11 12 #define _GNU_SOURCE 13 #include <string.h> 14 15 #include "atombios.h" 16 #include "driver.h" 17 #include "edid_raw.h" 18 #include "utility.h" 19 #include "vesa_info.h" 20 21 22 extern bios_module_info* sBIOSModule; 23 24 25 status_t 26 vbe_patch_intel_bios(bios_state* state, display_mode& mode) 27 { 28 edid1_detailed_timing_raw timing; 29 30 timing.pixel_clock = mode.timing.pixel_clock / 10; 31 32 timing.h_active = mode.timing.h_display & 0xFF; 33 timing.h_active_high = (mode.timing.h_display >> 8) & 0xF; 34 35 uint16 h_blank = mode.timing.h_total - mode.timing.h_display; 36 timing.h_blank = h_blank & 0xff; 37 timing.h_blank_high = (h_blank >> 8) & 0xF; 38 39 timing.v_active = mode.timing.v_display & 0xFF; 40 timing.v_active_high = (mode.timing.v_display >> 8) & 0xF; 41 42 uint16 v_blank = mode.timing.v_total - mode.timing.v_display; 43 timing.v_blank = v_blank & 0xff; 44 timing.v_blank_high = (v_blank >> 8) & 0xF; 45 46 uint16 h_sync_off = mode.timing.h_sync_start - mode.timing.h_display; 47 timing.h_sync_off = h_sync_off & 0xFF; 48 timing.h_sync_off_high = (h_sync_off >> 8) & 0x3; 49 50 uint16 h_sync_width = mode.timing.h_sync_end - mode.timing.h_sync_start; 51 timing.h_sync_width = h_sync_width & 0xFF; 52 timing.h_sync_width_high = (h_sync_width >> 8) & 0x3; 53 54 uint16 v_sync_off = mode.timing.v_sync_start - mode.timing.v_display; 55 timing.v_sync_off = v_sync_off & 0xF; 56 timing.v_sync_off_high = (v_sync_off >> 4) & 0x3; 57 58 uint16 v_sync_width = mode.timing.v_sync_end - mode.timing.v_sync_start; 59 timing.v_sync_width = v_sync_width & 0xF; 60 timing.v_sync_width_high = (v_sync_width >> 4) & 0x3; 61 62 timing.h_size = 0; 63 timing.v_size = 0; 64 timing.h_size_high = 0; 65 timing.v_size_high = 0; 66 timing.h_border = 0; 67 timing.v_border = 0; 68 timing.interlaced = 0; 69 timing.stereo = 0; 70 timing.sync = 3; 71 timing.misc = 0; 72 timing.stereo_il = 0; 73 74 static const uint8 knownMode[] = { 0x64, 0x19, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 75 0x88, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; 76 // This is the EDID description for a standard 1024x768 timing. We will find and replace 77 // all occurences of it in the BIOS with our custom mode. 78 79 // Get a pointer to the BIOS 80 const uintptr_t kBiosBase = 0xc0000; 81 const size_t kBiosSize = 0x10000; 82 uint8_t* bios = (uint8_t*)sBIOSModule->virtual_address(state, kBiosBase); 83 uint8_t* biosEnd = bios + kBiosSize; 84 85 int replacementCount = 0; 86 while (bios < biosEnd) { 87 bios = (uint8_t*)memmem(bios, biosEnd - bios, knownMode, sizeof(knownMode)); 88 if (bios == NULL) 89 break; 90 memcpy(bios, &timing, sizeof(timing)); 91 bios += sizeof(timing); 92 replacementCount++; 93 } 94 95 dprintf(DEVICE_NAME ": patched custom mode in %d locations\n", replacementCount); 96 97 // Did we manage to find a mode descriptor to replace? 98 if (replacementCount == 0) 99 return B_NOT_SUPPORTED; 100 return B_OK; 101 } 102 103 104 status_t 105 vbe_patch_nvidia_bios(bios_state* state, display_mode& mode) 106 { 107 struct nvidia_mode { 108 uint32 width; 109 uint32 height; 110 uint8 patch0[17]; 111 uint8 patch1[9]; 112 uint8 patch2[13]; 113 uint8 patch3[5]; 114 }; 115 116 static const nvidia_mode allowedModes[] = { 117 {1280, 720, {0x16, 0xCB, 0x9F, 0x9F, 0x8F, 0xA7, 0x17, 0xEA, 0xD2, 0xCF, 0xCF, 0xEB, 0x47, 118 0xE0, 0xC0, 0x00, 0x01}, 119 {0x00, 0x05, 0xD0, 0x02, 0xA0, 0x2C, 0x10, 0x07, 0x05}, 120 {0x7B, 0x01, 0x03, 0x7B, 0x01, 0x08, 0x01, 0x20, 0x80, 0x02, 0xFF, 0xFF, 0x20}, 121 {0x00, 0x05, 0xBA, 0xD0, 0x02}}, 122 {1280, 800, {0x12, 0xCD, 0x9F, 0x9F, 0x91, 0xA9, 0x1A, 0x3A, 0x21, 0x1F, 0x1F, 0x3B, 0x44, 123 0xFE, 0xC0, 0x00, 0x01}, 124 {0x00, 0x05, 0x20, 0x03, 0xA0, 0x32, 0x10, 0x23, 0x05}, 125 {0x61, 0x01, 0x03, 0x61, 0x01, 0x08, 0x01, 0x20, 0x80, 0x02, 0xFF, 0xFF, 0x20}, 126 {0x00, 0x05, 0xBA, 0x20, 0x03}}, 127 {1360, 768, {0x16, 0xB9, 0xA9, 0x9F, 0x8F, 0xB2, 0x16, 0x14, 0x01, 0xFF, 0xCF, 0xEB, 0x46, 128 0xEA, 0xC0, 0x00, 0x01}, 129 {0x50, 0x05, 0x00, 0x03, 0xAA, 0x2F, 0x10, 0x07, 0x05}, 130 {0x4D, 0x01, 0x03, 0x4D, 0x01, 0x08, 0x01, 0x20, 0xA8, 0x02, 0xFF, 0xFF, 0x20}, 131 {0x50, 0x05, 0xBA, 0x00, 0x03}}, 132 {1400, 1050, {0x12, 0xE6, 0xAE, 0xAE, 0x8A, 0xBB, 0x8E, 0x3D, 0x1B, 0x19, 0x19, 0x3E, 0x0E, 133 0x00, 0xC0, 0x24, 0x12}, 134 {0x78, 0x05, 0x1A, 0x04, 0xAF, 0x4A, 0x0E, 0x21, 0x05}, 135 {0x49, 0x01, 0x03, 0x49, 0x01, 0x08, 0x01, 0x20, 0xBC, 0x02, 0xFF, 0xFF, 0x20}, 136 {0x78, 0x05, 0xBA, 0x1A, 0x04}}, 137 {1440, 900, {0x12, 0xE9, 0xB3, 0xB3, 0x8D, 0xBF, 0x92, 0xA3, 0x85, 0x83, 0x83, 0xA4, 0x48, 138 0xFE, 0xC0, 0x00, 0x00}, 139 {0xA0, 0x05, 0x84, 0x03, 0xB4, 0x38, 0x10, 0x24, 0x05}, 140 {0x65, 0x01, 0x03, 0x65, 0x01, 0x08, 0x01, 0x20, 0xD0, 0x02, 0xFF, 0xFF, 0x20}, 141 {0xA0, 0x05, 0xBA, 0x84, 0x03}}, 142 {1600, 900, {0x1A, 0xD7, 0xC7, 0xC7, 0x9B, 0xCD, 0x11, 0x9C, 0x86, 0x83, 0x83, 0x9D, 0x4B, 143 0xFE, 0xC0, 0x00, 0x00}, 144 {0x40, 0x06, 0x84, 0x03, 0xC8, 0x38, 0x10, 0x27, 0x05}, 145 {0x67, 0x01, 0x03, 0x67, 0x01, 0x08, 0x01, 0x20, 0x20, 0x03, 0xFF, 0xFF, 0x20}, 146 {0x40, 0x06, 0xBA, 0x84, 0x03}}, 147 {1600, 1200, {0x12, 0x03, 0xC7, 0xC7, 0x87, 0xD1, 0x09, 0xE0, 0xB1, 0xAF, 0xAF, 0xE1, 0x04, 148 0x00, 0x01, 0x24, 0x13}, 149 {0x40, 0x06, 0xB0, 0x04, 0xC8, 0x4A, 0x10, 0x19, 0x05}, 150 {0x4A, 0x01, 0x03, 0x4A, 0x01, 0x08, 0x01, 0x20, 0x20, 0x03, 0xFF, 0xFF, 0x20}, 151 {0x40, 0x06, 0xBA, 0xB0, 0x04}}, 152 {1680, 1050, {0x12, 0x15, 0xD1, 0xD1, 0x99, 0xE0, 0x17, 0x3D, 0x1B, 0x19, 0x19, 0x3E, 0x0E, 153 0x00, 0x01, 0x24, 0x13}, 154 {0x90, 0x06, 0x1A, 0x04, 0xD2, 0x41, 0x10, 0x25, 0x05}, 155 {0x69, 0x01, 0x03, 0x69, 0x01, 0x08, 0x01, 0x20, 0x48, 0x03, 0xFF, 0xFF, 0x20}, 156 {0x90, 0x06, 0xBA, 0x1A, 0x04}}, 157 {1920, 1080, {0x16, 0x0E, 0xEF, 0x9F, 0x8F, 0xFD, 0x02, 0x63, 0x3B, 0x37, 0xCF, 0xEB, 0x40, 158 0x00, 0xC1, 0x24, 0x02}, 159 {0x80, 0x07, 0x38, 0x04, 0xF0, 0x42, 0x10, 0x07, 0x05}, 160 {0x4D, 0x01, 0x03, 0x4D, 0x01, 0x08, 0x01, 0x20, 0xC0, 0x03, 0xFF, 0xFF, 0x20}, 161 {0x80, 0x07, 0xBA, 0x38, 0x04}}, 162 {1920, 1200, {0x12, 0x3F, 0xEF, 0xEF, 0x83, 0x01, 0x1B, 0xD8, 0xB1, 0xAF, 0xAF, 0xD9, 0x04, 163 0x00, 0x41, 0x25, 0x12}, 164 {0x80, 0x07, 0xB0, 0x04, 0xF0, 0x4B, 0x10, 0x26, 0x05}, 165 {0x7D, 0x01, 0x03, 0x7D, 0x01, 0x08, 0x01, 0x20, 0xC0, 0x03, 0xFF, 0xFF, 0x20}, 166 {0x80, 0x07, 0xBA, 0xB0, 0x04}}, 167 {2048, 1536, {0x12, 0x63, 0xFF, 0xFF, 0x9D, 0x12, 0x0E, 0x34, 0x01, 0x00, 0x00, 0x35, 0x44, 168 0xE0, 0x41, 0x25, 0x13}, 169 {0x00, 0x08, 0x00, 0x06, 0x00, 0x60, 0x10, 0x22, 0x05}, 170 {0x7A, 0x01, 0x03, 0x52, 0x01, 0x08, 0x01, 0x20, 0x00, 0x04, 0xFF, 0xFF, 0x20}, 171 {0x00, 0x08, 0xBA, 0x00, 0x06}} 172 }; 173 174 static const nvidia_mode knownMode = { 0, 0, 175 {0x34, 0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x9c, 0x8f, 0x96, 0xb9, 0x8e, 0x1f, 0x00, 176 0x00, 0x00}, 177 {0x28, 0x00, 0x19, 0x00, 0x28, 0x18, 0x08, 0x08, 0x05}, 178 {0x82, 0x0f, 0x03, 0x01, 0x00, 0x00, 0x08, 0x04, 0x14, 0x00, 0x00, 0x08, 0x17}, 179 {0x40, 0x06, 0xba, 0xb0, 0x04} 180 }; 181 182 size_t i; 183 for (i = 0; i < B_COUNT_OF(allowedModes); i++) { 184 if (allowedModes[i].width == mode.timing.h_display 185 && allowedModes[i].height == mode.timing.v_display) { 186 break; 187 } 188 } 189 190 if (i >= B_COUNT_OF(allowedModes)) 191 return B_BAD_VALUE; 192 193 // Get a pointer to the BIOS 194 const uintptr_t kBiosBase = 0xc0000; 195 const size_t kBiosSize = 0x10000; 196 uint8_t* biosBase = (uint8_t*)sBIOSModule->virtual_address(state, kBiosBase); 197 uint8_t* biosEnd = biosBase + kBiosSize; 198 199 int replacementCount = 0; 200 uint8_t* bios = biosBase; 201 while (bios < biosEnd) { 202 bios = (uint8_t*)memmem(bios, biosEnd - bios, knownMode.patch0, sizeof(knownMode.patch0)); 203 if (bios == NULL) 204 break; 205 memcpy(bios, allowedModes[i].patch0, sizeof(allowedModes[i].patch0)); 206 bios += sizeof(knownMode.patch0); 207 replacementCount++; 208 } 209 dprintf(DEVICE_NAME ": applied patch0 in %d locations\n", replacementCount); 210 211 replacementCount = 0; 212 bios = biosBase; 213 while (bios < biosEnd) { 214 bios = (uint8_t*)memmem(bios, biosEnd - bios, knownMode.patch1, sizeof(knownMode.patch1)); 215 if (bios == NULL) 216 break; 217 memcpy(bios, allowedModes[i].patch1, sizeof(allowedModes[i].patch1)); 218 bios += sizeof(knownMode.patch1); 219 replacementCount++; 220 } 221 dprintf(DEVICE_NAME ": applied patch1 in %d locations\n", replacementCount); 222 223 replacementCount = 0; 224 bios = biosBase; 225 while (bios < biosEnd) { 226 bios = (uint8_t*)memmem(bios, biosEnd - bios, knownMode.patch2, sizeof(knownMode.patch2)); 227 if (bios == NULL) 228 break; 229 memcpy(bios, allowedModes[i].patch2, sizeof(allowedModes[i].patch2)); 230 bios += sizeof(knownMode.patch2); 231 replacementCount++; 232 } 233 dprintf(DEVICE_NAME ": applied patch2 in %d locations\n", replacementCount); 234 235 replacementCount = 0; 236 bios = biosBase; 237 while (bios < biosEnd) { 238 bios = (uint8_t*)memmem(bios, biosEnd - bios, knownMode.patch3, sizeof(knownMode.patch3)); 239 if (bios == NULL) 240 break; 241 memcpy(bios, allowedModes[i].patch3, sizeof(allowedModes[i].patch3)); 242 bios += sizeof(knownMode.patch3); 243 replacementCount++; 244 } 245 dprintf(DEVICE_NAME ": applied patch3 in %d locations\n", replacementCount); 246 247 if ((biosBase[0x34] & 0x8F) == 0x80) 248 biosBase[0x34] |= 0x01; 249 250 return B_OK; 251 } 252 253 254 status_t 255 vbe_patch_atom1_bios(vesa_info& info, bios_state* state, display_mode& mode) 256 { 257 // Get a pointer to the BIOS 258 const uintptr_t kBiosBase = 0xc0000; 259 uint8_t* bios = (uint8_t*)sBIOSModule->virtual_address(state, kBiosBase); 260 261 ATOM_MODE_TIMING* timing = (ATOM_MODE_TIMING*)(bios + info.shared_info->mode_table_offset); 262 dprintf(DEVICE_NAME ": patching ATOM mode timing (overwriting mode %dx%d)\n", 263 timing->usCRTC_H_Disp, timing->usCRTC_V_Disp); 264 265 timing->usCRTC_H_Total = mode.timing.h_total; 266 timing->usCRTC_H_Disp = mode.timing.h_display; 267 timing->usCRTC_H_SyncStart = mode.timing.h_sync_start; 268 timing->usCRTC_H_SyncWidth = mode.timing.h_sync_end - mode.timing.h_sync_start; 269 270 timing->usCRTC_V_Total = mode.timing.v_total; 271 timing->usCRTC_V_Disp = mode.timing.v_display; 272 timing->usCRTC_V_SyncStart = mode.timing.v_sync_start; 273 timing->usCRTC_V_SyncWidth = mode.timing.v_sync_end - mode.timing.v_sync_start; 274 275 timing->usPixelClock = mode.timing.pixel_clock / 10; 276 277 return B_OK; 278 } 279 280 281 status_t 282 vbe_patch_atom2_bios(vesa_info& info, bios_state* state, display_mode& mode) 283 { 284 // Get a pointer to the BIOS 285 const uintptr_t kBiosBase = 0xc0000; 286 uint8_t* bios = (uint8_t*)sBIOSModule->virtual_address(state, kBiosBase); 287 288 ATOM_DTD_FORMAT* timing = (ATOM_DTD_FORMAT*)(bios + info.shared_info->mode_table_offset); 289 dprintf(DEVICE_NAME ": patching ATOM DTD format (overwriting mode %dx%d)\n", 290 timing->usHActive, timing->usVActive); 291 292 timing->usHBlanking_Time = mode.timing.h_total - mode.timing.h_display; 293 timing->usHActive = mode.timing.h_display; 294 timing->usHSyncOffset = mode.timing.h_sync_start; 295 timing->usHSyncWidth = mode.timing.h_sync_end - mode.timing.h_sync_start; 296 297 timing->usVBlanking_Time = mode.timing.v_total - mode.timing.v_display; 298 timing->usVActive = mode.timing.v_display; 299 timing->usVSyncOffset = mode.timing.v_sync_start; 300 timing->usVSyncWidth = mode.timing.v_sync_end - mode.timing.v_sync_start; 301 302 timing->usPixClk = mode.timing.pixel_clock / 10; 303 304 return B_OK; 305 } 306 307 308 /*! Identify the BIOS type if it's one of the common ones, and locate where the BIOS store its 309 * allowed video modes table. We can then patch this table to add extra video modes that the 310 * manufacturer didn't allow. 311 */ 312 void 313 vesa_identify_bios(bios_state* state, vesa_shared_info* sharedInfo) 314 { 315 // Get a pointer to the BIOS 316 const uintptr_t kBiosBase = 0xc0000; 317 uint8_t* bios = (uint8_t*)sBIOSModule->virtual_address(state, kBiosBase); 318 319 const size_t kAtomBiosHeaderOffset = 0x48; 320 const char kAtomSignature[] = {'A', 'T', 'O', 'M'}; 321 322 ATOM_ROM_HEADER* atomRomHeader = (ATOM_ROM_HEADER*)(bios + kAtomBiosHeaderOffset); 323 324 sharedInfo->bios_type = kUnknownBiosType; 325 326 if (*(uint16*)(bios + 0x44) == 0x8086) { 327 dprintf(DEVICE_NAME ": detected Intel BIOS\n"); 328 329 // TODO check if we can find the mode table 330 sharedInfo->bios_type = kIntelBiosType; 331 } else if (memcmp(atomRomHeader->uaFirmWareSignature, kAtomSignature, 4) == 0) { 332 dprintf(DEVICE_NAME ": detected ATOM BIOS\n"); 333 334 ATOM_MASTER_DATA_TABLE* masterDataTable = (ATOM_MASTER_DATA_TABLE*)(bios 335 + atomRomHeader->usMasterDataTableOffset); 336 dprintf(DEVICE_NAME ": list of data tables: %p", &masterDataTable->ListOfDataTables); 337 ATOM_ANALOG_TV_INFO* standardVesaTable = (ATOM_ANALOG_TV_INFO*)(bios 338 + masterDataTable->ListOfDataTables.StandardVESA_Timing); 339 dprintf(DEVICE_NAME ": std_vesa: %p", standardVesaTable); 340 sharedInfo->mode_table_offset = (uint8*)&standardVesaTable->aModeTimings - bios; 341 342 size_t tableSize = standardVesaTable->sHeader.usStructureSize 343 - sizeof(ATOM_COMMON_TABLE_HEADER); 344 if (tableSize % sizeof(ATOM_MODE_TIMING) == 0) 345 sharedInfo->bios_type = kAtomBiosType2; 346 else 347 sharedInfo->bios_type = kAtomBiosType1; 348 } else if (memmem(bios, 512, "NVID", 4) != NULL) { 349 dprintf(DEVICE_NAME ": detected nVidia BIOS\n"); 350 351 // TODO check if we can find the mode table 352 sharedInfo->bios_type = kNVidiaBiosType; 353 } else { 354 dprintf(DEVICE_NAME ": unknown BIOS type, custom video modes will not be available\n"); 355 } 356 } 357 358 359 /*! Set a custom display mode by live patching the VESA BIOS to insert it in the modeline table. 360 * 361 * This is only supported for some video cards, where the format of the mode lines is known. 362 */ 363 status_t 364 vesa_set_custom_display_mode(vesa_info& info, display_mode& mode) 365 { 366 int32 modeIndex = -1; 367 if (info.shared_info->bios_type == kUnknownBiosType) 368 return B_NOT_SUPPORTED; 369 370 // Prepare BIOS environment 371 bios_state* state; 372 status_t status = vbe_call_prepare(&state); 373 if (status != B_OK) 374 return status; 375 376 // Patch bios to inject custom video mode 377 switch (info.shared_info->bios_type) { 378 case kIntelBiosType: 379 status = vbe_patch_intel_bios(state, mode); 380 // The patch replaces the 1024x768 modes with our custom resolution. We can then use 381 // mode 0x118 which is the standard VBE2 mode for 1024x768 at 32 bits per pixel, and 382 // know it will use our new timings. 383 break; 384 case kNVidiaBiosType: 385 status = vbe_patch_nvidia_bios(state, mode); 386 break; 387 case kAtomBiosType1: 388 status = vbe_patch_atom1_bios(info, state, mode); 389 break; 390 case kAtomBiosType2: 391 status = vbe_patch_atom2_bios(info, state, mode); 392 break; 393 default: 394 status = B_NOT_SUPPORTED; 395 break; 396 } 397 398 if (status != B_OK) 399 goto out; 400 401 // The patching modified some mode, but we don't know which one. So we need to rescan the mode 402 // list to find the correct one. 403 struct vbe_mode_info modeInfo; 404 for (uint32 i = 0; i < info.shared_info->vesa_mode_count; i++) { 405 status = vbe_get_mode_info(state, info.modes[i].mode, &modeInfo); 406 if (status != B_OK) { 407 // Sometimes the patching prevents us from getting the mode info? 408 dprintf(DEVICE_NAME ": vesa_set_custom_display_mode(): cannot get mode info for %x\n", 409 info.modes[i].mode); 410 // Just ignore modes that turn out to be invalid... 411 continue; 412 } 413 414 if (modeInfo.width == mode.timing.h_display && modeInfo.height == mode.timing.v_display 415 && get_color_space_for_depth(info.modes[i].bits_per_pixel) == mode.space) { 416 modeIndex = info.modes[i].mode; 417 break; 418 } 419 } 420 421 if (modeIndex >= 0) { 422 dprintf(DEVICE_NAME ": custom mode resolution %dx%d succesfully patched at index %" 423 B_PRIx32 "\n", modeInfo.width, modeInfo.height, modeIndex); 424 } else { 425 dprintf(DEVICE_NAME ": video mode patching failed!\n"); 426 goto out; 427 } 428 429 // Set mode 430 status = vbe_set_mode(state, modeIndex); 431 if (status != B_OK) { 432 dprintf(DEVICE_NAME ": vesa_set_custom_display_mode(): cannot set mode\n"); 433 goto out; 434 } 435 436 if (info.modes[modeIndex].bits_per_pixel <= 8) 437 vbe_set_bits_per_gun(state, info, 8); 438 439 // Map new frame buffer if necessary 440 441 status = remap_frame_buffer(info, modeInfo.physical_base, modeInfo.width, 442 modeInfo.height, modeInfo.bits_per_pixel, modeInfo.bytes_per_row, 443 false); 444 445 if (status == B_OK) { 446 // Update shared frame buffer information 447 info.shared_info->current_mode.virtual_width = modeInfo.width; 448 info.shared_info->current_mode.virtual_height = modeInfo.height; 449 info.shared_info->current_mode.space = get_color_space_for_depth( 450 modeInfo.bits_per_pixel); 451 } 452 453 out: 454 vbe_call_finish(state); 455 return status; 456 } 457 458 459