1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Clemens Zeidler, haiku@clemens-zeidler.de 8 * Fredrik Holmqvis, fredrik.holmqvist@gmail.com 9 * Alexander von Gluck, kallisti5@unixzen.com 10 */ 11 12 13 #include "radeon_hd.h" 14 #include "sensors.h" 15 16 #include "AreaKeeper.h" 17 #include "driver.h" 18 #include "utility.h" 19 20 #include <unistd.h> 21 #include <stdio.h> 22 #include <string.h> 23 #include <errno.h> 24 25 #include <boot_item.h> 26 #include <driver_settings.h> 27 #include <util/kernel_cpp.h> 28 #include <vm/vm.h> 29 30 31 #define TRACE_DEVICE 32 #ifdef TRACE_DEVICE 33 # define TRACE(x...) dprintf("radeon_hd: " x) 34 #else 35 # define TRACE(x) ; 36 #endif 37 38 #define ERROR(x...) dprintf("radeon_hd: " x) 39 40 41 // #pragma mark - 42 43 44 status_t 45 mapAtomBIOS(radeon_info &info, uint32 romBase, uint32 romSize) 46 { 47 TRACE("%s: seeking AtomBIOS @ 0x%" B_PRIX32 " [size: 0x%" B_PRIX32 "]\n", 48 __func__, romBase, romSize); 49 50 uint8* rom; 51 52 // attempt to access area specified 53 area_id testArea = map_physical_memory("radeon hd rom probe", 54 romBase, romSize, B_ANY_KERNEL_ADDRESS, B_READ_AREA, 55 (void**)&rom); 56 57 if (testArea < 0) { 58 ERROR("%s: couldn't map potential rom @ 0x%" B_PRIX32 59 "\n", __func__, romBase); 60 return B_NO_MEMORY; 61 } 62 63 // check for valid BIOS signature 64 if (rom[0] != 0x55 || rom[1] != 0xAA) { 65 uint16 id = rom[0] + (rom[1] << 8); 66 TRACE("%s: BIOS signature incorrect @ 0x%" B_PRIX32 " (%X)\n", 67 __func__, romBase, id); 68 delete_area(testArea); 69 return B_ERROR; 70 } 71 72 // see if valid AtomBIOS rom 73 uint16 romHeader = RADEON_BIOS16(rom, 0x48); 74 bool romValid = !memcmp(&rom[romHeader + 4], "ATOM", 4) 75 || !memcmp(&rom[romHeader + 4], "MOTA", 4); 76 77 if (romValid == false) { 78 // FAIL : a PCI VGA bios but not AtomBIOS 79 uint16 id = rom[0] + (rom[1] << 8); 80 TRACE("%s: not AtomBIOS rom at 0x%" B_PRIX32 "(%X)\n", 81 __func__, romBase, id); 82 delete_area(testArea); 83 return B_ERROR; 84 } 85 86 info.rom_area = create_area("radeon hd AtomBIOS", 87 (void**)&info.atom_buffer, B_ANY_KERNEL_ADDRESS, 88 romSize, B_NO_LOCK, B_READ_AREA | B_WRITE_AREA); 89 90 if (info.rom_area < 0) { 91 ERROR("%s: unable to map kernel AtomBIOS space!\n", 92 __func__); 93 delete_area(testArea); 94 return B_NO_MEMORY; 95 } 96 97 memset((void*)info.atom_buffer, 0, romSize); 98 // Prevent unknown code execution by AtomBIOS parser 99 memcpy(info.atom_buffer, (void*)rom, romSize); 100 // Copy AtomBIOS to kernel area 101 102 // validate copied rom is valid 103 romHeader = RADEON_BIOS16(info.atom_buffer, 0x48); 104 romValid = !memcmp(&info.atom_buffer[romHeader + 4], "ATOM", 4) 105 || !memcmp(&info.atom_buffer[romHeader + 4], "MOTA", 4); 106 107 if (romValid == true) { 108 set_area_protection(info.rom_area, B_READ_AREA); 109 ERROR("%s: AtomBIOS verified and locked\n", __func__); 110 } else 111 ERROR("%s: AtomBIOS memcpy failed!\n", __func__); 112 113 delete_area(testArea); 114 return romValid ? B_OK : B_ERROR; 115 } 116 117 118 static status_t 119 radeon_hd_getbios(radeon_info &info) 120 { 121 TRACE("card(%ld): %s: called\n", info.id, __func__); 122 123 uint32 romBase = 0; 124 uint32 romSize = 0; 125 uint32 romMethod = 0; 126 127 status_t mapResult = B_ERROR; 128 129 // first we try to find the AtomBIOS rom via various methods 130 for (romMethod = 0; romMethod < 3; romMethod++) { 131 switch(romMethod) { 132 case 0: 133 // TODO: *** New ACPI method 134 ERROR("%s: ACPI ATRM AtomBIOS TODO\n", __func__); 135 break; 136 case 1: 137 // *** Discreet card on IGP, check PCI BAR 0 138 // On post, the bios puts a copy of the IGP 139 // AtomBIOS at the start of the video ram 140 romBase = info.pci->u.h0.base_registers[PCI_BAR_FB]; 141 romSize = 256 * 1024; 142 143 if (romBase == 0 || romSize == 0) { 144 ERROR("%s: No base found at PCI FB BAR\n", __func__); 145 } else { 146 mapResult = mapAtomBIOS(info, romBase, romSize); 147 } 148 break; 149 case 2: 150 { 151 // *** PCI ROM BAR 152 // Enable ROM decoding for PCI BAR rom 153 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4); 154 pciConfig |= PCI_rom_enable; 155 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 156 157 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4); 158 if ((flags & PCI_rom_enable) != 0) 159 TRACE("%s: PCI ROM decode enabled\n", __func__); 160 161 romBase = info.pci->u.h0.rom_base; 162 romSize = info.pci->u.h0.rom_size; 163 164 if (romBase == 0 || romSize == 0) { 165 ERROR("%s: No base found at PCI ROM BAR\n", __func__); 166 } else { 167 mapResult = mapAtomBIOS(info, romBase, romSize); 168 } 169 170 // Disable ROM decoding 171 pciConfig &= ~PCI_rom_enable; 172 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 173 break; 174 } 175 } 176 177 if (mapResult == B_OK) { 178 ERROR("%s: AtomBIOS found using active method %" B_PRIu32 179 " at 0x%" B_PRIX32 "\n", __func__, romMethod, romBase); 180 break; 181 } else { 182 ERROR("%s: AtomBIOS not found using active method %" B_PRIu32 183 " at 0x%" B_PRIX32 "\n", __func__, romMethod, romBase); 184 } 185 } 186 187 if (mapResult == B_OK) { 188 info.shared_info->rom_phys = romBase; 189 info.shared_info->rom_size = romSize; 190 } else 191 ERROR("%s: Active AtomBIOS search failed.\n", __func__); 192 193 return mapResult; 194 } 195 196 197 static status_t 198 radeon_hd_getbios_ni(radeon_info &info) 199 { 200 TRACE("card(%ld): %s: called\n", info.id, __func__); 201 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL); 202 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL); 203 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL); 204 uint32 vga_render_control 205 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL); 206 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL); 207 208 // enable the rom 209 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 210 // disable VGA mode 211 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control 212 & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 213 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 214 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control 215 & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 216 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 217 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, 218 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 219 220 write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 221 222 // try to grab the bios via PCI ROM bar 223 // Enable ROM decoding for PCI BAR rom 224 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4); 225 pciConfig |= PCI_rom_enable; 226 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 227 228 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4); 229 if (flags & PCI_rom_enable) 230 TRACE("%s: PCI ROM decode enabled\n", __func__); 231 232 uint32 romBase = info.pci->u.h0.rom_base; 233 uint32 romSize = info.pci->u.h0.rom_size; 234 235 status_t result = B_OK; 236 if (romBase == 0 || romSize == 0) { 237 ERROR("%s: No AtomBIOS location found at PCI ROM BAR\n", __func__); 238 result = B_ERROR; 239 } else { 240 result = mapAtomBIOS(info, romBase, romSize); 241 } 242 243 if (result == B_OK) { 244 ERROR("%s: AtomBIOS found using disabled method at 0x%" B_PRIX32 245 " [size: 0x%" B_PRIX32 "]\n", __func__, romBase, romSize); 246 info.shared_info->rom_phys = romBase; 247 info.shared_info->rom_size = romSize; 248 } 249 250 // Disable ROM decoding 251 pciConfig &= ~PCI_rom_enable; 252 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 253 254 // restore regs 255 write32(info.registers + R600_BUS_CNTL, bus_cntl); 256 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control); 257 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control); 258 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control); 259 write32(info.registers + R600_ROM_CNTL, rom_cntl); 260 261 return result; 262 } 263 264 265 static status_t 266 radeon_hd_getbios_r700(radeon_info &info) 267 { 268 TRACE("card(%ld): %s: called\n", info.id, __func__); 269 uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL); 270 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL); 271 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL); 272 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL); 273 uint32 vga_render_control 274 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL); 275 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL); 276 277 // disable VIP 278 write32(info.registers + RADEON_VIPH_CONTROL, 279 (viph_control & ~RADEON_VIPH_EN)); 280 // enable the rom 281 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 282 // disable VGA mode 283 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control 284 & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 285 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 286 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control 287 & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 288 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 289 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, 290 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 291 292 write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 293 294 // try to grab the bios via PCI ROM bar 295 // Enable ROM decoding for PCI BAR rom 296 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4); 297 pciConfig |= PCI_rom_enable; 298 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 299 300 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4); 301 if (flags & PCI_rom_enable) 302 TRACE("%s: PCI ROM decode enabled\n", __func__); 303 304 uint32 romBase = info.pci->u.h0.rom_base; 305 uint32 romSize = info.pci->u.h0.rom_size; 306 307 status_t result = B_OK; 308 if (romBase == 0 || romSize == 0) { 309 ERROR("%s: No AtomBIOS location found at PCI ROM BAR\n", __func__); 310 result = B_ERROR; 311 } else { 312 result = mapAtomBIOS(info, romBase, romSize); 313 } 314 315 if (result == B_OK) { 316 ERROR("%s: AtomBIOS found using disabled method at 0x%" B_PRIX32 317 " [size: 0x%" B_PRIX32 "]\n", __func__, romBase, romSize); 318 info.shared_info->rom_phys = romBase; 319 info.shared_info->rom_size = romSize; 320 } 321 322 // Disable ROM decoding 323 pciConfig &= ~PCI_rom_enable; 324 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 325 326 // restore regs 327 write32(info.registers + RADEON_VIPH_CONTROL, viph_control); 328 write32(info.registers + R600_BUS_CNTL, bus_cntl); 329 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control); 330 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control); 331 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control); 332 write32(info.registers + R600_ROM_CNTL, rom_cntl); 333 334 return result; 335 } 336 337 338 static status_t 339 radeon_hd_getbios_r600(radeon_info &info) 340 { 341 TRACE("card(%ld): %s: called\n", info.id, __func__); 342 uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL); 343 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL); 344 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL); 345 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL); 346 uint32 vga_render_control 347 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL); 348 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL); 349 uint32 general_pwrmgt = read32(info.registers + R600_GENERAL_PWRMGT); 350 uint32 low_vid_lower_gpio_cntl 351 = read32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL); 352 uint32 medium_vid_lower_gpio_cntl 353 = read32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL); 354 uint32 high_vid_lower_gpio_cntl 355 = read32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL); 356 uint32 ctxsw_vid_lower_gpio_cntl 357 = read32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL); 358 uint32 lower_gpio_enable 359 = read32(info.registers + R600_LOWER_GPIO_ENABLE); 360 361 // disable VIP 362 write32(info.registers + RADEON_VIPH_CONTROL, 363 (viph_control & ~RADEON_VIPH_EN)); 364 // enable the rom 365 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 366 // disable VGA mode 367 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control 368 & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 369 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 370 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control 371 & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 372 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 373 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, 374 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 375 376 write32(info.registers + R600_ROM_CNTL, 377 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) 378 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | R600_SCK_OVERWRITE)); 379 380 write32(info.registers + R600_GENERAL_PWRMGT, 381 (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 382 write32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL, 383 (low_vid_lower_gpio_cntl & ~0x400)); 384 write32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL, 385 (medium_vid_lower_gpio_cntl & ~0x400)); 386 write32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL, 387 (high_vid_lower_gpio_cntl & ~0x400)); 388 write32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL, 389 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 390 write32(info.registers + R600_LOWER_GPIO_ENABLE, 391 (lower_gpio_enable | 0x400)); 392 393 // try to grab the bios via PCI ROM bar 394 // Enable ROM decoding for PCI BAR rom 395 uint32 pciConfig = get_pci_config(info.pci, PCI_rom_base, 4); 396 pciConfig |= PCI_rom_enable; 397 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 398 399 uint32 flags = get_pci_config(info.pci, PCI_rom_base, 4); 400 if (flags & PCI_rom_enable) 401 TRACE("%s: PCI ROM decode enabled\n", __func__); 402 403 uint32 romBase = info.pci->u.h0.rom_base; 404 uint32 romSize = info.pci->u.h0.rom_size; 405 406 status_t result = B_OK; 407 if (romBase == 0 || romSize == 0) { 408 ERROR("%s: No AtomBIOS location found at PCI ROM BAR\n", __func__); 409 result = B_ERROR; 410 } else { 411 result = mapAtomBIOS(info, romBase, romSize); 412 } 413 414 if (result == B_OK) { 415 ERROR("%s: AtomBIOS found using disabled method at 0x%" B_PRIX32 416 " [size: 0x%" B_PRIX32 "]\n", __func__, romBase, romSize); 417 info.shared_info->rom_phys = romBase; 418 info.shared_info->rom_size = romSize; 419 } 420 421 // Disable ROM decoding 422 pciConfig &= ~PCI_rom_enable; 423 set_pci_config(info.pci, PCI_rom_base, 4, pciConfig); 424 425 // restore regs 426 write32(info.registers + RADEON_VIPH_CONTROL, viph_control); 427 write32(info.registers + R600_BUS_CNTL, bus_cntl); 428 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control); 429 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control); 430 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control); 431 write32(info.registers + R600_ROM_CNTL, rom_cntl); 432 write32(info.registers + R600_GENERAL_PWRMGT, general_pwrmgt); 433 write32(info.registers + R600_LOW_VID_LOWER_GPIO_CNTL, 434 low_vid_lower_gpio_cntl); 435 write32(info.registers + R600_MEDIUM_VID_LOWER_GPIO_CNTL, 436 medium_vid_lower_gpio_cntl); 437 write32(info.registers + R600_HIGH_VID_LOWER_GPIO_CNTL, 438 high_vid_lower_gpio_cntl); 439 write32(info.registers + R600_CTXSW_VID_LOWER_GPIO_CNTL, 440 ctxsw_vid_lower_gpio_cntl); 441 write32(info.registers + R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 442 443 return result; 444 } 445 446 447 static status_t 448 radeon_hd_getbios_avivo(radeon_info &info) 449 { 450 TRACE("card(%ld): %s: called\n", info.id, __func__); 451 uint32 sepromControl = read32(info.registers + RADEON_SEPROM_CNTL1); 452 uint32 viphControl = read32(info.registers + RADEON_VIPH_CONTROL); 453 uint32 busControl = read32(info.registers + RV370_BUS_CNTL); 454 uint32 d1vgaControl = read32(info.registers + AVIVO_D1VGA_CONTROL); 455 uint32 d2vgaControl = read32(info.registers + AVIVO_D2VGA_CONTROL); 456 uint32 vgaRenderControl 457 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL); 458 uint32 gpioPadA = read32(info.registers + RADEON_GPIOPAD_A); 459 uint32 gpioPadEN = read32(info.registers + RADEON_GPIOPAD_EN); 460 uint32 gpioPadMask = read32(info.registers + RADEON_GPIOPAD_MASK); 461 462 write32(info.registers + RADEON_SEPROM_CNTL1, 463 ((sepromControl & ~RADEON_SCK_PRESCALE_MASK) 464 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); 465 write32(info.registers + RADEON_GPIOPAD_A, 0); 466 write32(info.registers + RADEON_GPIOPAD_EN, 0); 467 write32(info.registers + RADEON_GPIOPAD_MASK, 0); 468 469 // disable VIP 470 write32(info.registers + RADEON_VIPH_CONTROL, 471 (viphControl & ~RADEON_VIPH_EN)); 472 473 // enable the ROM 474 write32(info.registers + RV370_BUS_CNTL, 475 (busControl & ~RV370_BUS_BIOS_DIS_ROM)); 476 477 // disable VGA 478 write32(info.registers + AVIVO_D1VGA_CONTROL, 479 (d1vgaControl & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 480 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 481 write32(info.registers + AVIVO_D2VGA_CONTROL, 482 (d2vgaControl & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE 483 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); 484 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, 485 (vgaRenderControl & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 486 487 uint32 romBase = info.pci->u.h0.rom_base; 488 uint32 romSize = info.pci->u.h0.rom_size; 489 490 status_t result = B_OK; 491 if (romBase == 0 || romSize == 0) { 492 ERROR("%s: No AtomBIOS location found at PCI ROM BAR\n", __func__); 493 result = B_ERROR; 494 } else { 495 result = mapAtomBIOS(info, romBase, romSize); 496 } 497 498 if (result == B_OK) { 499 ERROR("%s: AtomBIOS found using disabled method at 0x%" B_PRIX32 500 " [size: 0x%" B_PRIX32 "]\n", __func__, romBase, romSize); 501 info.shared_info->rom_phys = romBase; 502 info.shared_info->rom_size = romSize; 503 } 504 505 // restore registers 506 write32(info.registers + RADEON_SEPROM_CNTL1, sepromControl); 507 write32(info.registers + RADEON_VIPH_CONTROL, viphControl); 508 write32(info.registers + RV370_BUS_CNTL, busControl); 509 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vgaControl); 510 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vgaControl); 511 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vgaRenderControl); 512 write32(info.registers + RADEON_GPIOPAD_A, gpioPadA); 513 write32(info.registers + RADEON_GPIOPAD_EN, gpioPadEN); 514 write32(info.registers + RADEON_GPIOPAD_MASK, gpioPadMask); 515 516 return result; 517 } 518 519 520 status_t 521 radeon_hd_init(radeon_info &info) 522 { 523 TRACE("card(%ld): %s: called\n", info.id, __func__); 524 525 ERROR("%s: card(%ld): " 526 "Radeon %s 1002:%" B_PRIX32 "\n", __func__, info.id, 527 radeon_chip_name[info.chipsetID], info.pciID); 528 529 // *** Map shared info 530 AreaKeeper sharedCreator; 531 info.shared_area = sharedCreator.Create("radeon hd shared info", 532 (void**)&info.shared_info, B_ANY_KERNEL_ADDRESS, 533 ROUND_TO_PAGE_SIZE(sizeof(radeon_shared_info)), B_FULL_LOCK, 0); 534 if (info.shared_area < B_OK) { 535 ERROR("%s: card (%ld): couldn't map shared area!\n", 536 __func__, info.id); 537 return info.shared_area; 538 } 539 540 memset((void*)info.shared_info, 0, sizeof(radeon_shared_info)); 541 sharedCreator.Detach(); 542 543 // *** Map Memory mapped IO 544 AreaKeeper mmioMapper; 545 info.registers_area = mmioMapper.Map("radeon hd mmio", 546 info.pci->u.h0.base_registers[PCI_BAR_MMIO], 547 info.pci->u.h0.base_register_sizes[PCI_BAR_MMIO], 548 B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 549 (void**)&info.registers); 550 if (mmioMapper.InitCheck() < B_OK) { 551 ERROR("%s: card (%ld): couldn't map memory I/O!\n", 552 __func__, info.id); 553 return info.registers_area; 554 } 555 mmioMapper.Detach(); 556 557 // *** Populate frame buffer information 558 if (info.chipsetID >= RADEON_CEDAR) { 559 if ((info.chipsetFlags & CHIP_APU) != 0 560 || (info.chipsetFlags & CHIP_IGP) != 0) { 561 // Evergreen+ fusion in bytes 562 info.shared_info->graphics_memory_size 563 = read32(info.registers + CONFIG_MEMSIZE) / 1024; 564 } else { 565 // Evergreen+ has memory stored in MB 566 info.shared_info->graphics_memory_size 567 = read32(info.registers + CONFIG_MEMSIZE) * 1024; 568 } 569 } else if (info.chipsetID >= RADEON_R600) { 570 // R600-R700 has memory stored in bytes 571 info.shared_info->graphics_memory_size 572 = read32(info.registers + CONFIG_MEMSIZE) / 1024; 573 } else { 574 // R420 - R600 cards 575 // older cards use RADEON_CONFIG_MEMSIZE vs CONFIG_MEMSIZE 576 if ((info.chipsetFlags & CHIP_IGP) != 0) { 577 // NB_TOM holds amount of ram stolen for GPU 578 uint32 tom = read32(info.registers + RADEON_NB_TOM); 579 info.shared_info->graphics_memory_size 580 = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 581 write32(info.registers + RADEON_CONFIG_MEMSIZE, 582 info.shared_info->graphics_memory_size); 583 } else { 584 info.shared_info->graphics_memory_size 585 = read32(info.registers + RADEON_CONFIG_MEMSIZE); 586 if (info.shared_info->graphics_memory_size == 0) { 587 // known bug if video memory == 8MB 588 info.shared_info->graphics_memory_size = 8192; 589 write32(info.registers + RADEON_CONFIG_MEMSIZE, 590 info.shared_info->graphics_memory_size * 1024); 591 } 592 } 593 } 594 595 uint32 barSize = info.pci->u.h0.base_register_sizes[PCI_BAR_FB] / 1024; 596 597 // if graphics memory is larger then PCI bar, just map bar 598 if (info.shared_info->graphics_memory_size == 0) { 599 // we can recover as we have PCI FB bar, but this should be fixed 600 ERROR("%s: Error: found 0MB video ram, using PCI bar size...\n", 601 __func__); 602 info.shared_info->frame_buffer_size = barSize; 603 } else if (info.shared_info->graphics_memory_size > barSize) { 604 TRACE("%s: shrinking frame buffer to PCI bar...\n", 605 __func__); 606 info.shared_info->frame_buffer_size = barSize; 607 } else { 608 info.shared_info->frame_buffer_size 609 = info.shared_info->graphics_memory_size; 610 } 611 612 TRACE("%s: mapping a frame buffer of %" B_PRIu32 "MB out of %" B_PRIu32 613 "MB video ram\n", __func__, info.shared_info->frame_buffer_size / 1024, 614 info.shared_info->graphics_memory_size / 1024); 615 616 // *** Framebuffer mapping 617 AreaKeeper frambufferMapper; 618 info.framebuffer_area = frambufferMapper.Map("radeon hd frame buffer", 619 info.pci->u.h0.base_registers[PCI_BAR_FB], 620 info.shared_info->frame_buffer_size * 1024, 621 B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA, 622 (void**)&info.shared_info->frame_buffer); 623 if (frambufferMapper.InitCheck() < B_OK) { 624 ERROR("%s: card(%ld): couldn't map frame buffer!\n", 625 __func__, info.id); 626 return info.framebuffer_area; 627 } 628 629 // Turn on write combining for the frame buffer area 630 vm_set_area_memory_type(info.framebuffer_area, 631 info.pci->u.h0.base_registers[PCI_BAR_FB], B_MTR_WC); 632 633 frambufferMapper.Detach(); 634 635 info.shared_info->frame_buffer_area = info.framebuffer_area; 636 info.shared_info->frame_buffer_phys 637 = info.pci->u.h0.base_registers[PCI_BAR_FB]; 638 639 // Pass common information to accelerant 640 info.shared_info->deviceIndex = info.id; 641 info.shared_info->pciID = info.pciID; 642 info.shared_info->chipsetID = info.chipsetID; 643 info.shared_info->chipsetFlags = info.chipsetFlags; 644 info.shared_info->dceMajor = info.dceMajor; 645 info.shared_info->dceMinor = info.dceMinor; 646 info.shared_info->registers_area = info.registers_area; 647 strncpy(info.shared_info->deviceName, 648 info.deviceName, MAX_NAME_LENGTH); 649 strncpy(info.shared_info->chipsetName, 650 radeon_chip_name[info.chipsetID], MAX_NAME_LENGTH); 651 652 // *** AtomBIOS mapping 653 // First we try an active bios read 654 status_t biosStatus = radeon_hd_getbios(info); 655 656 if (biosStatus != B_OK) { 657 // If the active read fails, we try a disabled read 658 if (info.chipsetID >= RADEON_CAICOS) 659 biosStatus = radeon_hd_getbios_ni(info); 660 else if (info.chipsetID >= RADEON_RV770) 661 biosStatus = radeon_hd_getbios_r700(info); 662 else if (info.chipsetID >= RADEON_R600) 663 biosStatus = radeon_hd_getbios_r600(info); 664 else if (info.chipsetID >= RADEON_RS600) 665 biosStatus = radeon_hd_getbios_avivo(info); 666 // else legacy_read_disabled_bios 667 } 668 669 if (biosStatus != B_OK) { 670 // *** very last resort, shadow bios VGA rom 671 ERROR("%s: Can't find an AtomBIOS rom! Trying shadow rom...\n", 672 __func__); 673 674 // This works as long as the primary card is what this driver 675 // is loaded for. Multiple cards may pose the risk of loading 676 // the wrong AtomBIOS for the wrong card. 677 678 uint32 romBase = 0xC0000; 679 uint32 romSize = 128 * 1024; 680 // what happens when AtomBIOS goes over 128Kb? 681 // A Radeon HD 6990 has a 128Kb AtomBIOS 682 683 if (mapAtomBIOS(info, romBase, romSize) == B_OK) { 684 ERROR("%s: Found AtomBIOS at VGA shadow rom\n", __func__); 685 // Whew! 686 info.shared_info->rom_phys = romBase; 687 info.shared_info->rom_size = romSize; 688 biosStatus = B_OK; 689 } 690 } 691 692 // Check if a valid AtomBIOS image was found. 693 if (biosStatus != B_OK) { 694 ERROR("%s: card (%ld): couldn't find AtomBIOS rom!\n", 695 __func__, info.id); 696 ERROR("%s: card (%ld): exiting. Please open a bug ticket" 697 " at haiku-os.org with your /var/log/syslog\n", 698 __func__, info.id); 699 // Fallback to VESA (more likely crash app_server) 700 return B_ERROR; 701 } 702 703 info.shared_info->has_rom = (biosStatus == B_OK) ? true : false; 704 info.shared_info->rom_area = (biosStatus == B_OK) ? info.rom_area : -1; 705 706 // *** Pull active monitor VESA EDID from boot loader 707 edid1_info* edidInfo 708 = (edid1_info*)get_boot_item(EDID_BOOT_INFO, NULL); 709 710 if (edidInfo != NULL) { 711 TRACE("card(%ld): %s found VESA EDID information.\n", info.id, 712 __func__); 713 info.shared_info->has_edid = true; 714 memcpy(&info.shared_info->edid_info, edidInfo, sizeof(edid1_info)); 715 } else { 716 TRACE("card(%ld): %s didn't find VESA EDID modes.\n", info.id, 717 __func__); 718 info.shared_info->has_edid = false; 719 } 720 721 TRACE("card(%ld): %s completed successfully!\n", info.id, __func__); 722 723 TRACE("card(%ld): GPU thermal status: %" B_PRId32 "C\n", info.id, 724 radeon_thermal_query(info) / 1000); 725 726 return B_OK; 727 } 728 729 730 void 731 radeon_hd_uninit(radeon_info &info) 732 { 733 TRACE("card(%ld): %s called\n", info.id, __func__); 734 735 delete_area(info.shared_area); 736 delete_area(info.registers_area); 737 delete_area(info.framebuffer_area); 738 delete_area(info.rom_area); 739 } 740 741