1 /* 2 * Copyright (c) 2002-2004, Thomas Kurschel 3 * Distributed under the terms of the MIT license. 4 */ 5 #ifndef _RADEON_DRIVER_H 6 #define _RADEON_DRIVER_H 7 8 9 #include "radeon_interface.h" 10 #include "memory_manager.h" 11 12 #include <KernelExport.h> 13 #include <GraphicsDefs.h> 14 #include "AGP.h" 15 16 // logging helpers 17 extern int debug_level_flow; 18 extern int debug_level_info; 19 extern int debug_level_error; 20 21 /*#define DEBUG_WAIT_ON_MSG 1000000 22 #define DEBUG_WAIT_ON_ERROR 1000000*/ 23 24 #define DEBUG_MSG_PREFIX "Radeon - " 25 #include "debug_ext.h" 26 27 #include "log_coll.h" 28 29 30 #define MAX_DEVICES 8 31 32 // size of PCI GART; 33 // the only user is the command processor, which needs 1 MB, 34 // so make sure that GART is large enough 35 #define PCI_GART_SIZE 1024*1024 36 37 // size of CP ring buffer in dwords 38 #define CP_RING_SIZE 2048 39 40 41 // GART info (either PCI or AGP) 42 typedef struct { 43 // data accessed via GART 44 struct { 45 area_id area; // area of data 46 size_t size; // size of buffer 47 void *ptr; // CPU pointer to data 48 area_id unaligned_area; // unaligned address (see PCI_GART.c) 49 } buffer; 50 51 // GATT info (address translation table) 52 struct { 53 area_id area; // area containing GATT 54 uint32 *ptr; // CPU pointer to GATT 55 uint32 phys; // physical address of GATT 56 } GATT; 57 } GART_info; 58 59 // info about graphics RAM 60 typedef struct { 61 int ml; 62 int MB; 63 int Trcd; 64 int Trp; 65 int Twr; 66 int CL; 67 int Tr2w; 68 int loop_latency; 69 int Rloop; 70 int width; 71 } ram_info; 72 73 // ROM information 74 typedef struct { 75 area_id bios_area; // only mapped during detection 76 77 uint32 phys_address; // physical address of BIOS 78 uint32 size; // size in bytes 79 80 // the following is only useful if ROM is mapped during detection, 81 // but the difference if the offset of hw info 82 uint8 *bios_ptr; // begin of entire BIOS 83 uint8 *rom_ptr; // begin of ROM containing hw info 84 } rom_info; 85 86 87 // timer for VBI emulation 88 typedef struct { 89 timer te; /* timer entry for add_timer() */ 90 struct device_info *di; /* pointer to the owning device */ 91 bigtime_t when_target; /* when we're supposed to wake up */ 92 } timer_info; 93 94 95 // info about one device 96 typedef struct device_info { 97 uint32 is_open; 98 area_id shared_area; 99 shared_info *si; 100 101 area_id virtual_card_area; 102 virtual_card *vc; 103 vuint8 *regs; 104 105 radeon_type asic; 106 uint8 num_crtc; 107 tv_chip_type tv_chip; 108 bool is_mobility; 109 bool new_pll; 110 bool has_vip; 111 bool is_igp; 112 bool has_no_i2c; 113 bool acc_dma; 114 115 fp_info fp_info; 116 disp_entity routing; 117 118 general_pll_info pll; 119 tmds_pll_info tmds_pll[4]; 120 ram_info ram; 121 char ram_type[32]; // human-readable name of ram type 122 uint32 local_mem_size; 123 124 rom_info rom; 125 bool is_atombios; // legacy ROM, or "AtomBios" 126 127 GART_info pci_gart; // PCI GART 128 GART_info agp_gart; // AGP GART (unsupported) 129 memory_type_e nonlocal_map; // default type of non-local memory; 130 131 mem_info *memmgr[mt_last+1]; // memory managers; 132 // if there is no AGP; the entries for non_local 133 // and PCI are the same 134 135 // VBI data 136 uint32 interrupt_count; 137 uint32 vbi_count[2]; 138 // VBI emulation 139 int32 shutdown_virtual_irq; // true, to shutdown virtual interrupts 140 timer_info ti_a; /* a pool of two timer managment buffers */ 141 timer_info ti_b; 142 timer_info *current_timer; /* the timer buffer that's currently in use */ 143 144 // DMA GUI engine 145 sem_id dma_sem; 146 uint32 dma_desc_max_num; 147 uint32 dma_desc_handle; 148 uint32 dma_desc_offset; 149 150 // capture engine 151 spinlock cap_spinlock; // synchronization for following capture data 152 sem_id cap_sem; // semaphore released on capture interrupt 153 uint32 cap_int_status; // content of CAP_INT_STATUS during lost capture irq 154 uint32 cap_counter; // counter of capture interrupts 155 bigtime_t cap_timestamp; // timestamp of last capture interrupt 156 157 uint32 dac2_cntl; // original dac2_cntl register content 158 159 radeon_settings settings; // overrides read from radeon.settings 160 161 pci_info pcii; 162 agp_info agpi; 163 char name[MAX_RADEON_DEVICE_NAME_LENGTH]; 164 char video_name[MAX_RADEON_DEVICE_NAME_LENGTH]; 165 } device_info; 166 167 168 // device list and some global data 169 typedef struct { 170 uint32 count; 171 benaphore kernel; 172 // every device is exported as a graphics and a video card 173 char *device_names[2*MAX_DEVICES+1]; 174 device_info di[MAX_DEVICES]; 175 } radeon_devices; 176 177 178 extern pci_module_info *pci_bus; 179 extern agp_gart_module_info *sAGP; 180 extern radeon_devices *devices; 181 182 183 // detect.c 184 bool Radeon_CardDetect( void ); 185 void Radeon_ProbeDevices( void ); 186 187 188 // init.c 189 status_t Radeon_FirstOpen( device_info *di ); 190 void Radeon_LastClose( device_info *di ); 191 status_t Radeon_MapDevice( device_info *di, bool mmio_only ); 192 void Radeon_UnmapDevice(device_info *di); 193 194 195 // bios.c 196 status_t Radeon_MapBIOS( pci_info *pcii, rom_info *ri ); 197 void Radeon_UnmapBIOS( rom_info *ri ); 198 status_t Radeon_ReadBIOSData( device_info *di ); 199 200 201 // PCI_GART.c 202 status_t Radeon_InitPCIGART( device_info *di ); 203 void Radeon_CleanupPCIGART( device_info *di ); 204 205 206 // irq.c 207 status_t Radeon_SetupIRQ( device_info *di, char *buffer ); 208 void Radeon_CleanupIRQ( device_info *di ); 209 210 211 // agp.c 212 void Radeon_Set_AGP( device_info *di, bool enable_agp ); 213 214 215 // mem_controller.c 216 void Radeon_InitMemController( device_info *di ); 217 218 219 // CP_setup.c 220 void Radeon_WaitForIdle( device_info *di, bool acquire_lock, bool keep_lock ); 221 void Radeon_WaitForFifo( device_info *di, int entries ); 222 void Radeon_ResetEngine( device_info *di ); 223 status_t Radeon_InitCP( device_info *di ); 224 void Radeon_UninitCP( device_info *di ); 225 void Radeon_SetDynamicClock( device_info *di, int mode ); 226 227 228 // vip.c 229 bool Radeon_VIPRead( device_info *di, uint channel, uint address, uint32 *data, bool lock ); 230 bool Radeon_VIPWrite( device_info *di, uint8 channel, uint address, uint32 data, bool lock ); 231 bool Radeon_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock); 232 bool Radeon_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock); 233 int Radeon_FindVIPDevice( device_info *di, uint32 device_id ); 234 void Radeon_VIPReset( device_info *di, bool lock ); 235 236 237 // dma.c 238 status_t Radeon_InitDMA( device_info *di ); 239 status_t Radeon_DMACopy( 240 device_info *di, uint32 src, char *target, size_t size, 241 bool lock_mem, bool contiguous ); 242 243 #endif 244