xref: /haiku/src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h (revision 4f00613311d0bd6b70fa82ce19931c41f071ea4e)
1 /*
2 	Copyright (c) 2002-2004, Thomas Kurschel
3 
4 
5 	Part of Radeon kernel driver
6 
7 	Common header file
8 */
9 
10 #ifndef _RADEON_DRIVER_H
11 #define _RADEON_DRIVER_H
12 
13 #include "radeon_interface.h"
14 #include "memmgr.h"
15 
16 #include <KernelExport.h>
17 #include <GraphicsDefs.h>
18 
19 
20 // logging helpers
21 extern int debug_level_flow;
22 extern int debug_level_info;
23 extern int debug_level_error;
24 
25 /*#define DEBUG_WAIT_ON_MSG 1000000
26 #define DEBUG_WAIT_ON_ERROR 1000000*/
27 
28 #define DEBUG_MSG_PREFIX "Radeon - "
29 #include "debug_ext.h"
30 
31 #include "log_coll.h"
32 
33 
34 #define MAX_DEVICES	8
35 
36 // size of PCI GART;
37 // the only user is the command processor, which needs 1 MB,
38 // so make sure that GART is large enough
39 #define PCI_GART_SIZE 1024*1024
40 
41 // size of CP ring buffer in dwords
42 #define CP_RING_SIZE 2048
43 
44 
45 // GART info (either PCI or AGP)
46 typedef struct {
47 	// data accessed via GART
48 	struct {
49 		area_id area;			// area of data
50 		size_t size;			// size of buffer
51 		void *ptr;				// CPU pointer to data
52 		area_id unaligned_area;	// unaligned address (see PCI_GART.c)
53 	} buffer;
54 
55 	// GATT info (address translation table)
56 	struct {
57 		area_id area;			// area containing GATT
58 		uint32 *ptr;			// CPU pointer to GATT
59 		uint32 phys;			// physical address of GATT
60 	} GATT;
61 } GART_info;
62 
63 // info about graphics RAM
64 typedef struct {
65 	int ml;
66 	int MB;
67 	int Trcd;
68 	int Trp;
69 	int Twr;
70 	int CL;
71 	int Tr2w;
72 	int loop_latency;
73 	int Rloop;
74 } ram_info;
75 
76 // ROM information
77 typedef struct {
78 	area_id		bios_area;		// only mapped during detection
79 
80 	uint32		phys_address;	// physical address of BIOS
81 	uint32		size;			// size in bytes
82 
83 	// the following is only useful if ROM is mapped during detection,
84 	// but the difference if the offset of hw info
85 	uint8		*bios_ptr;		// begin of entire BIOS
86 	uint8		*rom_ptr;		// begin of ROM containing hw info
87 } rom_info;
88 
89 
90 // timer for VBI emulation
91 typedef struct {
92 	timer		te;				/* timer entry for add_timer() */
93 	struct device_info	*di;	/* pointer to the owning device */
94 	bigtime_t	when_target;	/* when we're supposed to wake up */
95 } timer_info;
96 
97 
98 // info about one device
99 typedef struct device_info {
100 	uint32		is_open;
101 	area_id		shared_area;
102 	shared_info	*si;
103 
104 	area_id		virtual_card_area;
105 	virtual_card *vc;
106 	vuint8		*regs;
107 
108 	radeon_type	asic;
109 	uint8 		num_crtc;
110 	tv_chip_type tv_chip;
111 	bool		is_mobility;
112 	bool		new_pll;
113 	bool		has_vip;
114 	bool		is_igp;
115 	//display_type_e disp_type[2];
116 	fp_info		fp_info;
117 
118 	general_pll_info pll;
119 	ram_info	ram;
120 	char		ram_type[32];	// human-readable name of ram type
121 	uint32		local_mem_size;
122 
123 	rom_info	rom;
124 
125 	GART_info	pci_gart;		// PCI GART
126 	GART_info	agp_gart;		// AGP GART (unsupported)
127 	memory_type_e	nonlocal_map;	// default type of non-local memory;
128 
129 	mem_info	*memmgr[mt_last+1];	// memory managers;
130 								// if there is no AGP; the entries for non_local
131 								// and PCI are the same
132 
133 	// VBI data
134 	uint32      interrupt_count;
135 	uint32		vbi_count[2];
136 	// VBI emulation
137 	int32		shutdown_virtual_irq;	// true, to shutdown virtual interrupts
138 	timer_info  ti_a;           /* a pool of two timer managment buffers */
139     timer_info  ti_b;
140     timer_info  *current_timer; /* the timer buffer that's currently in use */
141 
142     // DMA GUI engine
143     sem_id		dma_sem;
144     uint32		dma_desc_max_num;
145     uint32		dma_desc_handle;
146     uint32		dma_desc_offset;
147 
148     // capture engine
149     spinlock	cap_spinlock;	// synchronization for following capture data
150    	sem_id		cap_sem;		// semaphore released on capture interrupt
151 	uint32		cap_int_status;	// content of CAP_INT_STATUS during lost capture irq
152 	uint32		cap_counter;	// counter of capture interrupts
153 	bigtime_t	cap_timestamp;	// timestamp of last capture interrupt
154 
155 	uint32		dac2_cntl;		// original dac2_cntl register content
156 
157 	pci_info	pcii;
158 	char		name[MAX_RADEON_DEVICE_NAME_LENGTH];
159 	char		video_name[MAX_RADEON_DEVICE_NAME_LENGTH];
160 } device_info;
161 
162 
163 // device list and some global data
164 typedef struct {
165 	uint32		count;
166 	benaphore	kernel;
167 	// every device is exported as a graphics and a video card
168 	char		*device_names[2*MAX_DEVICES+1];
169 	device_info	di[MAX_DEVICES];
170 } radeon_devices;
171 
172 
173 extern pci_module_info *pci_bus;
174 extern radeon_devices *devices;
175 
176 
177 // detect.c
178 bool Radeon_CardDetect( void );
179 void Radeon_ProbeDevices( void );
180 
181 
182 // init.c
183 status_t Radeon_FirstOpen( device_info *di );
184 void Radeon_LastClose( device_info *di );
185 status_t Radeon_MapDevice( device_info *di, bool mmio_only );
186 void Radeon_UnmapDevice(device_info *di);
187 
188 
189 // bios.c
190 status_t Radeon_MapBIOS( pci_info *pcii, rom_info *ri );
191 void Radeon_UnmapBIOS( rom_info *ri );
192 status_t Radeon_ReadBIOSData( device_info *di );
193 
194 
195 // PCI_GART.c
196 status_t Radeon_InitPCIGART( device_info *di );
197 void Radeon_CleanupPCIGART( device_info *di );
198 
199 
200 // irq.c
201 status_t Radeon_SetupIRQ( device_info *di, char *buffer );
202 void Radeon_CleanupIRQ( device_info *di );
203 
204 
205 // agp.c
206 void Radeon_Fix_AGP(void);
207 
208 
209 // mem_controller.c
210 void Radeon_InitMemController( device_info *di );
211 
212 
213 // CP_setup.c
214 void Radeon_WaitForIdle( device_info *di, bool acquire_lock, bool keep_lock );
215 void Radeon_WaitForFifo( device_info *di, int entries );
216 void Radeon_ResetEngine( device_info *di );
217 status_t Radeon_InitCP( device_info *di );
218 void Radeon_UninitCP( device_info *di );
219 
220 
221 // vip.c
222 bool Radeon_VIPRead( device_info *di, uint channel, uint address, uint32 *data, bool lock );
223 bool Radeon_VIPWrite( device_info *di, uint8 channel, uint address, uint32 data, bool lock );
224 int Radeon_FindVIPDevice( device_info *di, uint32 device_id );
225 
226 
227 // dma.c
228 status_t Radeon_InitDMA( device_info *di );
229 status_t Radeon_DMACopy(
230 	device_info *di, uint32 src, char *target, size_t size,
231 	bool lock_mem, bool contiguous );
232 
233 #endif
234