1 /* 2 * Copyright (c) 2002-2004, Thomas Kurschel 3 * Copyright (c) 2006-2007, Euan Kirkhope 4 * 5 * Distributed under the terms of the MIT license. 6 */ 7 8 /* 9 Init and clean-up of devices 10 11 TODO: support for multiple virtual card per device is 12 not implemented yet - there is only one per device; 13 apart from additional device names, we need proper 14 management of graphics mem to not interfere. 15 */ 16 17 #include "dac_regs.h" 18 #include "tv_out_regs.h" 19 #include "fp_regs.h" 20 #include "mmio.h" 21 #include "radeon_driver.h" 22 23 #include <PCI.h> 24 25 #include <stdio.h> 26 #include <string.h> 27 28 // helper macros for easier PCI access 29 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 30 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 31 32 extern radeon_settings current_settings; 33 34 // map frame buffer and registers 35 // mmio_only - true = map registers only (used during detection) 36 status_t Radeon_MapDevice( device_info *di, bool mmio_only ) 37 { 38 // framebuffer is stored in PCI range 0, 39 // register map in PCI range 2 40 int regs = 2; 41 int fb = 0; 42 char buffer[100]; 43 shared_info *si = di->si; 44 uint32 tmp; 45 pci_info *pcii = &(di->pcii); 46 status_t result; 47 48 SHOW_FLOW( 3, "device: %02X%02X%02X", 49 di->pcii.bus, di->pcii.device, di->pcii.function ); 50 51 si->ROM_area = si->regs_area = si->memory[mt_local].area = 0; 52 53 // enable memory mapped IO and frame buffer 54 // also, enable bus mastering (some BIOSes seem to 55 // disable that, like mine) 56 tmp = get_pci( PCI_command, 2 ); 57 SHOW_FLOW( 3, "old PCI command state: 0x%08lx", tmp ); 58 tmp |= PCI_command_io | PCI_command_memory | PCI_command_master; 59 set_pci( PCI_command, 2, tmp ); 60 61 // registers cannot be accessed directly by user apps, 62 // they need to clone area for safety reasons 63 SHOW_INFO( 1, "physical address of memory-mapped I/O: 0x%8lx-0x%8lx", 64 di->pcii.u.h0.base_registers[regs], 65 di->pcii.u.h0.base_registers[regs] + di->pcii.u.h0.base_register_sizes[regs] - 1 ); 66 67 sprintf( buffer, "%04X_%04X_%02X%02X%02X regs", 68 di->pcii.vendor_id, di->pcii.device_id, 69 di->pcii.bus, di->pcii.device, di->pcii.function ); 70 71 si->regs_area = map_physical_memory( 72 buffer, 73 di->pcii.u.h0.base_registers[regs], 74 di->pcii.u.h0.base_register_sizes[regs], 75 B_ANY_KERNEL_ADDRESS, 76 /*// for "poke" debugging 77 B_READ_AREA + B_WRITE_AREA*/ 78 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_USER_CLONEABLE_AREA, 79 (void **)&(di->regs)); 80 if( si->regs_area < 0 ) 81 return si->regs_area; 82 83 // that's all during detection as we have no clue about ROM or 84 // frame buffer at this point 85 if( mmio_only ) 86 return B_OK; 87 88 // ROM must be explicetely mapped by applications too 89 sprintf( buffer, "%04X_%04X_%02X%02X%02X ROM", 90 di->pcii.vendor_id, di->pcii.device_id, 91 di->pcii.bus, di->pcii.device, di->pcii.function ); 92 93 si->ROM_area = map_physical_memory( 94 buffer, 95 di->rom.phys_address, 96 di->rom.size, 97 B_ANY_KERNEL_ADDRESS, 98 0, 99 (void **)&(di->rom.rom_ptr)); 100 if( si->ROM_area < 0 ) { 101 result = si->ROM_area; 102 goto err2; 103 } 104 105 if( di->pcii.u.h0.base_register_sizes[fb] > di->local_mem_size ) { 106 // Radeons allocate more address range then really needed -> 107 // only map the area that contains physical memory 108 SHOW_INFO( 1, "restrict frame buffer from 0x%8lx to 0x%8lx bytes", 109 di->pcii.u.h0.base_register_sizes[fb], 110 di->local_mem_size 111 ); 112 di->pcii.u.h0.base_register_sizes[fb] = di->local_mem_size; 113 } 114 115 // framebuffer can be accessed by everyone 116 // this is not a perfect solution; preferably, only 117 // those areas owned by an application are mapped into 118 // its address space 119 // (this hack is needed by BeOS to write something onto screen in KDL) 120 SHOW_INFO( 1, "physical address of framebuffer: 0x%8lx-0x%8lx", 121 di->pcii.u.h0.base_registers[fb], 122 di->pcii.u.h0.base_registers[fb] + di->pcii.u.h0.base_register_sizes[fb] - 1 ); 123 124 sprintf(buffer, "%04X_%04X_%02X%02X%02X framebuffer", 125 di->pcii.vendor_id, di->pcii.device_id, 126 di->pcii.bus, di->pcii.device, di->pcii.function); 127 128 si->memory[mt_local].area = map_physical_memory( 129 buffer, 130 di->pcii.u.h0.base_registers[fb], 131 di->pcii.u.h0.base_register_sizes[fb], 132 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 133 B_READ_AREA | B_WRITE_AREA | B_USER_CLONEABLE_AREA, 134 (void **)&(si->local_mem)); 135 136 if( si->memory[mt_local].area < 0 ) { 137 SHOW_FLOW0( 3, "couldn't enable WC for frame buffer" ); 138 si->memory[mt_local].area = map_physical_memory( 139 buffer, 140 di->pcii.u.h0.base_registers[fb], 141 di->pcii.u.h0.base_register_sizes[fb], 142 B_ANY_KERNEL_BLOCK_ADDRESS, 143 B_READ_AREA | B_WRITE_AREA | B_USER_CLONEABLE_AREA, 144 (void **)&(si->local_mem)); 145 } 146 147 SHOW_FLOW( 3, "mapped frame buffer @%p", si->local_mem ); 148 149 if( si->memory[mt_local].area < 0 ) { 150 result = si->memory[mt_local].area; 151 goto err; 152 } 153 154 // save physical address though noone can probably make 155 // any use of it 156 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[fb]; 157 158 return B_OK; 159 160 err: 161 delete_area( si->ROM_area ); 162 err2: 163 delete_area( si->regs_area ); 164 return result; 165 } 166 167 168 // unmap PCI ranges 169 void Radeon_UnmapDevice(device_info *di) 170 { 171 shared_info *si = di->si; 172 pci_info *pcii = &(di->pcii); 173 uint32 tmp; 174 175 SHOW_FLOW0( 3, "" ); 176 177 // disable PCI ranges (though it probably won't 178 // hurt leaving them enabled) 179 tmp = get_pci( PCI_command, 2 ); 180 tmp &= ~PCI_command_io | PCI_command_memory | PCI_command_master; 181 set_pci( PCI_command, 2, tmp ); 182 183 if( si->regs_area > 0 ) 184 delete_area( si->regs_area ); 185 186 if( si->ROM_area > 0 ) 187 delete_area( si->ROM_area ); 188 189 if( si->memory[mt_local].area > 0 ) 190 delete_area( si->memory[mt_local].area ); 191 192 si->regs_area = si->ROM_area = si->memory[mt_local].area = 0; 193 } 194 195 196 // initialize shared infos on first open 197 status_t Radeon_FirstOpen( device_info *di ) 198 { 199 status_t result; 200 char buffer[100]; // B_OS_NAME_LENGTH is too short 201 shared_info *si; 202 //uint32 /*dma_block, */dma_offset; 203 204 // create shared info; don't allow access by apps - 205 // they'll clone it 206 sprintf( buffer, "%04X_%04X_%02X%02X%02X shared", 207 di->pcii.vendor_id, di->pcii.device_id, 208 di->pcii.bus, di->pcii.device, di->pcii.function ); 209 210 di->shared_area = create_area( 211 buffer, 212 (void **)&(di->si), 213 B_ANY_KERNEL_ADDRESS, 214 (sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1), 215 B_FULL_LOCK, 216 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_USER_CLONEABLE_AREA); 217 if (di->shared_area < 0) { 218 result = di->shared_area; 219 goto err8; 220 } 221 222 memset( di->si, 0, sizeof( *di->si )); 223 224 si = di->si; 225 226 si->settings = di->settings = current_settings; 227 228 if (di->settings.force_acc_dma) 229 di->acc_dma = true; 230 if (di->settings.force_acc_mmio) // force mmio will override dma... a tristate fuzzylogic, grey bool would be nice... 231 di->acc_dma = false; 232 233 #ifdef ENABLE_LOGGING 234 #ifdef LOG_INCLUDE_STARTUP 235 si->log = log_init( 1000000 ); 236 #endif 237 #endif 238 239 // copy all info into shared info 240 si->vendor_id = di->pcii.vendor_id; 241 si->device_id = di->pcii.device_id; 242 si->revision = di->pcii.revision; 243 244 si->asic = di->asic; 245 si->is_mobility = di->is_mobility; 246 si->tv_chip = di->tv_chip; 247 si->new_pll = di->new_pll; 248 si->is_igp = di->is_igp; 249 si->has_no_i2c = di->has_no_i2c; 250 si->is_atombios = di->is_atombios; 251 si->is_mobility = di->is_mobility; 252 si->panel_pwr_delay = di->si->panel_pwr_delay; 253 si->acc_dma = di->acc_dma; 254 255 memcpy(&si->routing, &di->routing, sizeof(disp_entity)); 256 257 // detecting theatre channel in kernel would lead to code duplication, 258 // so we let the first accelerant take care of it 259 si->theatre_channel = -1; 260 261 si->crtc[0].crtc_idx = 0; 262 si->crtc[0].flatpanel_port = 0; 263 si->crtc[1].crtc_idx = 1; 264 si->crtc[1].flatpanel_port = 1; 265 si->num_crtc = di->num_crtc; 266 267 if (di->is_mobility) 268 si->flatpanels[0] = di->fp_info; 269 270 si->pll = di->pll; 271 272 // create virtual card info; don't allow access by apps - 273 // they'll clone it 274 sprintf( buffer, "%04X_%04X_%02X%02X%02X virtual card 0", 275 di->pcii.vendor_id, di->pcii.device_id, 276 di->pcii.bus, di->pcii.device, di->pcii.function ); 277 di->virtual_card_area = create_area( 278 buffer, 279 (void **)&(di->vc), 280 B_ANY_KERNEL_ADDRESS, 281 (sizeof(virtual_card) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1), 282 B_FULL_LOCK, 283 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_USER_CLONEABLE_AREA); 284 if (di->virtual_card_area < 0) { 285 result = di->virtual_card_area; 286 goto err7; 287 } 288 289 // currently, we assign fixed ports to this virtual card 290 di->vc->assigned_crtc[0] = true; 291 di->vc->assigned_crtc[1] = si->num_crtc > 1; 292 di->vc->controlled_displays = 293 dd_tv_crt | dd_crt | dd_lvds | dd_dvi | dd_dvi_ext | dd_ctv | dd_stv; 294 295 di->vc->fb_mem_handle = 0; 296 di->vc->cursor.mem_handle = 0; 297 298 // create unique id 299 di->vc->id = di->virtual_card_area; 300 301 result = Radeon_MapDevice( di, false ); 302 if (result < 0) 303 goto err6; 304 305 // save dac2_cntl register 306 // on M6, we need to restore that during uninit, else you only get 307 // garbage on screen on reboot if both CRTCs are used 308 if( di->asic == rt_rv100 && di->is_mobility) 309 di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 ); 310 311 memcpy(&si->tmds_pll, &di->tmds_pll, sizeof(di->tmds_pll)); 312 si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL); 313 si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL); 314 315 // print these out to capture bios status... 316 // if ( di->is_mobility ) { 317 SHOW_INFO0( 2, "Copy of Laptop Display Regs for Reference:"); 318 SHOW_INFO( 2, "LVDS GEN = %8lx", INREG( di->regs, RADEON_LVDS_GEN_CNTL )); 319 SHOW_INFO( 2, "LVDS PLL = %8lx", INREG( di->regs, RADEON_LVDS_PLL_CNTL )); 320 SHOW_INFO( 2, "TMDS PLL = %8lx", INREG( di->regs, RADEON_TMDS_PLL_CNTL )); 321 SHOW_INFO( 2, "TMDS TRANS = %8lx", INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL )); 322 SHOW_INFO( 2, "FP1 GEN = %8lx", INREG( di->regs, RADEON_FP_GEN_CNTL )); 323 SHOW_INFO( 2, "FP2 GEN = %8lx", INREG( di->regs, RADEON_FP2_GEN_CNTL )); 324 SHOW_INFO( 2, "TV DAC = %8lx", INREG( di->regs, RADEON_TV_DAC_CNTL )); //not setup right when ext dvi 325 // } 326 327 result = Radeon_InitPCIGART( di ); 328 if( result < 0 ) 329 goto err5; 330 331 si->memory[mt_local].size = di->local_mem_size; 332 333 si->memory[mt_PCI].area = di->pci_gart.buffer.area; 334 si->memory[mt_PCI].size = di->pci_gart.buffer.size; 335 336 // currently, defaultnon-local memory is PCI memory 337 si->nonlocal_type = mt_PCI; 338 339 Radeon_InitMemController( di ); 340 341 // currently, we don't support VBI - something is broken there 342 // (it doesn't change a thing apart from crashing) 343 result = Radeon_SetupIRQ( di, buffer ); 344 if( result < 0 ) 345 goto err4; 346 347 // resolution of 2D register is 1K, resolution of CRTC etc. is higher, 348 // so 1K is the minimum block size; 349 // (CP cannot use local mem) 350 di->memmgr[mt_local] = mem_init("radeon local memory", 0, di->local_mem_size, 1024, 351 di->local_mem_size / 1024); 352 if (di->memmgr[mt_local] == NULL) { 353 result = B_NO_MEMORY; 354 goto err3; 355 } 356 357 // CP requires 4K alignment, which is the most restrictive I found 358 di->memmgr[mt_PCI] = mem_init("radeon PCI GART memory", 0, di->pci_gart.buffer.size, 4096, 359 di->pci_gart.buffer.size / 4096); 360 if (di->memmgr[mt_PCI] == NULL) { 361 result = B_NO_MEMORY; 362 goto err2; 363 } 364 365 // no AGP support 366 di->memmgr[mt_AGP] = NULL; 367 368 // fix AGP settings for IGP chipset 369 Radeon_Set_AGP( di, !di->settings.force_pci ); // disable AGP 370 371 372 // time to init Command Processor 373 result = Radeon_InitCP( di ); 374 if( result != B_OK ) 375 goto err; 376 377 if ( di->acc_dma ) 378 { 379 result = Radeon_InitDMA( di ); 380 if( result != B_OK ) 381 goto err0; 382 } 383 else 384 { 385 SHOW_INFO0( 0, "DMA is diabled using PIO mode"); 386 } 387 388 // mem_alloc( di->local_memmgr, 0x100000, (void *)-1, &dma_block, &dma_offset ); 389 /* dma_offset = 15 * 1024 * 1024; 390 391 si->nonlocal_mem = (uint32 *)((uint32)si->framebuffer + dma_offset); 392 si->nonlocal_vm_start = (uint32)si->framebuffer_pci + dma_offset;*/ 393 394 // set dynamic clocks for Mobilty chips 395 if (di->is_mobility && di->settings.dynamic_clocks) 396 Radeon_SetDynamicClock( di, 1); 397 398 return B_OK; 399 400 err0: 401 Radeon_UninitCP( di ); 402 err: 403 mem_destroy( di->memmgr[mt_PCI] ); 404 err2: 405 mem_destroy( di->memmgr[mt_local] ); 406 err3: 407 Radeon_CleanupIRQ( di ); 408 err4: 409 Radeon_CleanupPCIGART( di ); 410 err5: 411 Radeon_UnmapDevice( di ); 412 err6: 413 delete_area( di->virtual_card_area ); 414 err7: 415 delete_area( di->shared_area ); 416 err8: 417 return result; 418 } 419 420 // clean up shared info on last close 421 // (we could for device destruction, but this makes 422 // testing easier as everythings gets cleaned up 423 // during tests) 424 void Radeon_LastClose( device_info *di ) 425 { 426 if ( di->acc_dma ) 427 Radeon_UninitCP( di ); 428 429 // M6 fix - unfortunately, the device is never closed by app_server, 430 // not even before reboot 431 if( di->asic == rt_rv100 && di->is_mobility) 432 OUTREG( di->regs, RADEON_DAC_CNTL2, di->dac2_cntl ); 433 434 435 mem_destroy( di->memmgr[mt_local] ); 436 437 if( di->memmgr[mt_PCI] ) 438 mem_destroy( di->memmgr[mt_PCI] ); 439 440 if( di->memmgr[mt_AGP] ) 441 mem_destroy( di->memmgr[mt_AGP] ); 442 443 Radeon_CleanupIRQ( di ); 444 Radeon_CleanupPCIGART( di ); 445 Radeon_UnmapDevice(di); 446 447 #ifdef ENABLE_LOGGING 448 #ifdef LOG_INCLUDE_STARTUP 449 log_exit( di->si->log ); 450 #endif 451 #endif 452 453 delete_area( di->virtual_card_area ); 454 delete_area( di->shared_area ); 455 } 456