1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-6/2005. 8 */ 9 10 /* standard kernel driver stuff */ 11 #include <KernelExport.h> 12 #include <ISA.h> 13 #include <PCI.h> 14 #include <OS.h> 15 #include <driver_settings.h> 16 #include <malloc.h> 17 #include <stdlib.h> // for strtoXX 18 #include "AGP.h" 19 20 /* this is for the standardized portion of the driver API */ 21 /* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ 22 #include <graphic_driver.h> 23 24 /* this is for sprintf() */ 25 #include <stdio.h> 26 27 /* this is for string compares */ 28 #include <string.h> 29 30 /* The private interface between the accelerant and the kernel driver. */ 31 #include "DriverInterface.h" 32 #include "nv_macros.h" 33 34 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 35 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 36 37 #define MAX_DEVICES 8 38 39 #ifndef __HAIKU__ 40 # undef B_USER_CLONEABLE_AREA 41 # define B_USER_CLONEABLE_AREA 0 42 #endif 43 44 #define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed 45 46 /* Tell the kernel what revision of the driver API we support */ 47 int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 48 49 /* these structures are private to the kernel driver */ 50 typedef struct device_info device_info; 51 52 typedef struct { 53 timer te; /* timer entry for add_timer() */ 54 device_info *di; /* pointer to the owning device */ 55 bigtime_t when_target; /* when we're supposed to wake up */ 56 } timer_info; 57 58 struct device_info { 59 uint32 is_open; /* a count of how many times the devices has been opened */ 60 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 61 shared_info *si; /* a pointer to the shared area, for convenience */ 62 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 63 pci_info pcii; /* a convenience copy of the pci info for this device */ 64 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 65 }; 66 67 typedef struct { 68 uint32 count; /* number of devices actually found */ 69 benaphore kernel; /* for serializing opens/closes */ 70 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 71 device_info di[MAX_DEVICES]; /* device specific stuff */ 72 } DeviceData; 73 74 /* prototypes for our private functions */ 75 static status_t open_hook (const char* name, uint32 flags, void** cookie); 76 static status_t close_hook (void* dev); 77 static status_t free_hook (void* dev); 78 static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); 79 static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); 80 static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); 81 static status_t map_device(device_info *di); 82 static void unmap_device(device_info *di); 83 static void probe_devices(void); 84 static int32 nv_interrupt(void *data); 85 86 static DeviceData *pd; 87 static isa_module_info *isa_bus = NULL; 88 static pci_module_info *pci_bus = NULL; 89 static agp_module_info *agp_bus = NULL; 90 static device_hooks graphics_device_hooks = { 91 open_hook, 92 close_hook, 93 free_hook, 94 control_hook, 95 read_hook, 96 write_hook, 97 NULL, 98 NULL, 99 NULL, 100 NULL 101 }; 102 103 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 104 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 105 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 106 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 107 108 static uint16 nvidia_device_list[] = { 109 0x0020, /* Nvidia TNT1 */ 110 0x0028, /* Nvidia TNT2 (pro) */ 111 0x0029, /* Nvidia TNT2 Ultra */ 112 0x002a, /* Nvidia TNT2 */ 113 0x002b, /* Nvidia TNT2 */ 114 0x002c, /* Nvidia Vanta (Lt) */ 115 0x002d, /* Nvidia TNT2-M64 (Pro) */ 116 0x002e, /* Nvidia NV06 Vanta */ 117 0x002f, /* Nvidia NV06 Vanta */ 118 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 119 0x0041, /* Nvidia GeForce FX 6800 */ 120 0x0042, /* Nvidia GeForce FX 6800LE */ 121 0x0043, /* Nvidia unknown FX */ 122 0x0045, /* Nvidia GeForce FX 6800 GT */ 123 0x004d, /* Nvidia Quadro FX 4400 */ 124 0x004e, /* Nvidia Quadro FX 4000 */ 125 0x00a0, /* Nvidia Aladdin TNT2 */ 126 0x00c0, /* Nvidia unknown FX */ 127 0x00c1, /* Nvidia GeForce FX 6800 */ 128 0x00c2, /* Nvidia GeForce FX 6800LE */ 129 0x00c8, /* Nvidia GeForce FX 6800 Go */ 130 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 137 0x00f3, /* Nvidia GeForce 6200 */ 138 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 139 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 140 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 141 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 142 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 143 0x00fd, /* Nvidia Quadro PCX PCIe */ 144 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 145 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 146 0x0100, /* Nvidia GeForce256 SDR */ 147 0x0101, /* Nvidia GeForce256 DDR */ 148 0x0102, /* Nvidia GeForce256 Ultra */ 149 0x0103, /* Nvidia Quadro */ 150 0x0110, /* Nvidia GeForce2 MX/MX400 */ 151 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 152 0x0112, /* Nvidia GeForce2 Go */ 153 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 154 0x0140, /* Nvidia GeForce FX 6600 GT */ 155 0x0141, /* Nvidia GeForce FX 6600 */ 156 0x0144, /* Nvidia GeForce FX 6600 Go */ 157 0x0145, /* Nvidia GeForce FX 6610 XL */ 158 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 159 0x0148, /* Nvidia GeForce FX 6600 Go */ 160 0x014e, /* Nvidia Quadro FX 540 */ 161 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 162 0x0150, /* Nvidia GeForce2 GTS/Pro */ 163 0x0151, /* Nvidia GeForce2 Ti DDR */ 164 0x0152, /* Nvidia GeForce2 Ultra */ 165 0x0153, /* Nvidia Quadro2 Pro */ 166 0x0160, /* Nvidia unknown FX Go */ 167 0x0161, /* Nvidia GeForce 6200 TurboCache */ 168 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 169 0x0163, /* Nvidia unknown FX */ 170 0x0164, /* Nvidia GeForce FX 6200 Go */ 171 0x0165, /* Nvidia Quadro FX NVS 285 */ 172 0x0166, /* Nvidia unknown FX Go */ 173 0x0167, /* Nvidia GeForce 6200 Go */ 174 0x0168, /* Nvidia GeForce 6250 Go */ 175 0x016e, /* Nvidia unknown FX */ 176 0x0170, /* Nvidia GeForce4 MX 460 */ 177 0x0171, /* Nvidia GeForce4 MX 440 */ 178 0x0172, /* Nvidia GeForce4 MX 420 */ 179 0x0173, /* Nvidia GeForce4 MX 440SE */ 180 0x0174, /* Nvidia GeForce4 440 Go */ 181 0x0175, /* Nvidia GeForce4 420 Go */ 182 0x0176, /* Nvidia GeForce4 420 Go 32M */ 183 0x0177, /* Nvidia GeForce4 460 Go */ 184 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 185 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 186 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 187 0x017c, /* Nvidia Quadro4 500 GoGL */ 188 0x017d, /* Nvidia GeForce4 410 Go 16M */ 189 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 190 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 191 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 192 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 193 0x0186, /* Nvidia GeForce4 448 Go */ 194 0x0187, /* Nvidia GeForce4 488 Go */ 195 0x0188, /* Nvidia Quadro4 580 XGL */ 196 0x0189, /* Nvidia GeForce4 MX AGP8X */ 197 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 198 0x018b, /* Nvidia Quadro4 380 XGL */ 199 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 200 0x018d, /* Nvidia GeForce4 448 Go */ 201 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 202 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 203 0x0200, /* Nvidia GeForce3 */ 204 0x0201, /* Nvidia GeForce3 Ti 200 */ 205 0x0202, /* Nvidia GeForce3 Ti 500 */ 206 0x0203, /* Nvidia Quadro DCC */ 207 0x0211, /* Nvidia GeForce FX 6800 */ 208 0x0212, /* Nvidia GeForce FX 6800LE */ 209 0x0215, /* Nvidia GeForce FX 6800 GT */ 210 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 211 0x0250, /* Nvidia GeForce4 Ti 4600 */ 212 0x0251, /* Nvidia GeForce4 Ti 4400 */ 213 0x0252, /* Nvidia GeForce4 Ti 4600 */ 214 0x0253, /* Nvidia GeForce4 Ti 4200 */ 215 0x0258, /* Nvidia Quadro4 900 XGL */ 216 0x0259, /* Nvidia Quadro4 750 XGL */ 217 0x025b, /* Nvidia Quadro4 700 XGL */ 218 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 219 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 220 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 221 0x0286, /* Nvidia GeForce4 4200 Go */ 222 0x0288, /* Nvidia Quadro4 980 XGL */ 223 0x0289, /* Nvidia Quadro4 780 XGL */ 224 0x028c, /* Nvidia Quadro4 700 GoGL */ 225 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 226 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 227 0x0302, /* Nvidia GeForce FX 5800 */ 228 0x0308, /* Nvidia Quadro FX 2000 */ 229 0x0309, /* Nvidia Quadro FX 1000 */ 230 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 231 0x0312, /* Nvidia GeForce FX 5600 */ 232 0x0313, /* Nvidia unknown FX */ 233 0x0314, /* Nvidia GeForce FX 5600XT */ 234 0x0316, /* Nvidia unknown FX Go */ 235 0x0317, /* Nvidia unknown FX Go */ 236 0x031a, /* Nvidia GeForce FX 5600 Go */ 237 0x031b, /* Nvidia GeForce FX 5650 Go */ 238 0x031c, /* Nvidia Quadro FX 700 Go */ 239 0x031d, /* Nvidia unknown FX Go */ 240 0x031e, /* Nvidia unknown FX Go */ 241 0x031f, /* Nvidia unknown FX Go */ 242 0x0320, /* Nvidia GeForce FX 5200 */ 243 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 244 0x0322, /* Nvidia GeForce FX 5200 */ 245 0x0323, /* Nvidia GeForce FX 5200LE */ 246 0x0324, /* Nvidia GeForce FX 5200 Go */ 247 0x0325, /* Nvidia GeForce FX 5250 Go */ 248 0x0326, /* Nvidia GeForce FX 5500 */ 249 0x0327, /* Nvidia GeForce FX 5100 */ 250 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 251 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 252 0x032a, /* Nvidia Quadro NVS 280 PCI */ 253 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 254 0x032c, /* Nvidia GeForce FX 5300 Go */ 255 0x032d, /* Nvidia GeForce FX 5100 Go */ 256 0x032e, /* Nvidia unknown FX Go */ 257 0x032f, /* Nvidia unknown FX Go */ 258 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 259 0x0331, /* Nvidia GeForce FX 5900 */ 260 0x0332, /* Nvidia GeForce FX 5900 XT */ 261 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 262 0x0334, /* Nvidia GeForce FX 5900 ZT */ 263 0x0338, /* Nvidia Quadro FX 3000 */ 264 0x033f, /* Nvidia Quadro FX 700 */ 265 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 266 0x0342, /* Nvidia GeForce FX 5700 */ 267 0x0343, /* Nvidia GeForce FX 5700LE */ 268 0x0344, /* Nvidia GeForce FX 5700VE */ 269 0x0347, /* Nvidia GeForce FX 5700 Go */ 270 0x0348, /* Nvidia GeForce FX 5700 Go */ 271 0x034c, /* Nvidia Quadro FX 1000 Go */ 272 0x034e, /* Nvidia Quadro FX 1100 */ 273 0x034f, /* Nvidia unknown FX */ 274 0 275 }; 276 /* 277 not yet included nVidia ID's that are unknown, but used according to nvidia: 278 0x0049 //nv40 279 0x0142 //nv43 280 0x0143 //nv43 281 0x0147 //nv43 282 0x0149 //nv43 283 0x014b //nv43 284 0x014c //nv43 285 0x014d //nv43 286 0x0169 //nv44 go 287 0x016b //nv44 go 288 0x016c //nv44 go 289 0x016d //nv44 go 290 0x0210 //nv48 (existing? not in nvidia list) 291 0x021d //nv48 (existing? not in nvidia list) 292 0x021e //nv48 (existing? not in nvidia list) 293 0x0220 //nv44 294 0x0222 //nv44 295 0x0228 //nv44 go 296 0x0345 //nv36 297 0x0349 //nv36 go 298 0x034b //nv36. 299 */ 300 301 static uint16 elsa_device_list[] = { 302 0x0c60, /* Elsa Gladiac Geforce2 MX */ 303 0 304 }; 305 306 static uint16 nvstbsgs_device_list[] = { 307 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 308 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 309 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 310 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 311 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 312 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 313 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 314 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 315 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 316 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 317 0 318 }; 319 320 static uint16 varisys_device_list[] = { 321 0x3503, /* Varisys GeForce4 MX440 */ 322 0x3505, /* Varisys GeForce4 Ti 4200 */ 323 0 324 }; 325 326 static struct { 327 uint16 vendor; 328 uint16 *devices; 329 } SupportedDevices[] = { 330 {VENDOR_ID_NVIDIA, nvidia_device_list}, 331 {VENDOR_ID_ELSA, elsa_device_list}, 332 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 333 {VENDOR_ID_VARISYS, varisys_device_list}, 334 {0x0000, NULL} 335 }; 336 337 static nv_settings current_settings = { // see comments in nv.settings 338 // for driver 339 DRIVER_PREFIX ".accelerant", 340 false, // dumprom 341 // for accelerant 342 0x00000000, // logmask 343 0, // memory 344 true, // usebios 345 true, // hardcursor 346 false, // switchhead 347 false, // force_pci 348 false, // unhide_fw 349 true, // pgm_panel 350 false, // dma_acc 351 }; 352 353 static void dumprom (void *rom, uint32 size) 354 { 355 int fd; 356 uint32 cnt; 357 358 fd = open ("/boot/home/" DRIVER_PREFIX ".rom", O_WRONLY | O_CREAT, 0666); 359 if (fd < 0) return; 360 361 /* apparantly max. 32kb may be written at once; 362 * the ROM size is a multiple of that anyway. */ 363 for (cnt = 0; (cnt < size); cnt += 32768) 364 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 365 close (fd); 366 } 367 368 /* return 1 if vblank interrupt has occured */ 369 static int caused_vbi(vuint32 * regs) 370 { 371 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 372 } 373 374 /* clear the vblank interrupt */ 375 static void clear_vbi(vuint32 * regs) 376 { 377 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 378 } 379 380 static void enable_vbi(vuint32 * regs) 381 { 382 /* clear the vblank interrupt */ 383 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 384 /* enable nVidia interrupt source vblank */ 385 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 386 /* enable nVidia interrupt system hardware (b0-1) */ 387 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 388 } 389 390 static void disable_vbi(vuint32 * regs) 391 { 392 /* disable nVidia interrupt source vblank */ 393 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 394 /* clear the vblank interrupt */ 395 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 396 /* disable nVidia interrupt system hardware (b0-1) */ 397 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 398 } 399 400 /* 401 init_hardware() - Returns B_OK if one is 402 found, otherwise returns B_ERROR so the driver will be unloaded. 403 */ 404 status_t 405 init_hardware(void) { 406 long pci_index = 0; 407 pci_info pcii; 408 bool found_one = false; 409 410 /* choke if we can't find the PCI bus */ 411 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 412 return B_ERROR; 413 414 /* choke if we can't find the ISA bus */ 415 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 416 { 417 put_module(B_PCI_MODULE_NAME); 418 return B_ERROR; 419 } 420 421 /* while there are more pci devices */ 422 while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { 423 int vendor = 0; 424 425 /* if we match a supported vendor */ 426 while (SupportedDevices[vendor].vendor) { 427 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 428 uint16 *devices = SupportedDevices[vendor].devices; 429 /* while there are more supported devices */ 430 while (*devices) { 431 /* if we match a supported device */ 432 if (*devices == pcii.device_id ) { 433 434 found_one = true; 435 goto done; 436 } 437 /* next supported device */ 438 devices++; 439 } 440 } 441 vendor++; 442 } 443 /* next pci_info struct, please */ 444 pci_index++; 445 } 446 447 done: 448 /* put away the module manager */ 449 put_module(B_PCI_MODULE_NAME); 450 return (found_one ? B_OK : B_ERROR); 451 } 452 453 status_t 454 init_driver(void) { 455 void *settings_handle; 456 457 // get driver/accelerant settings, apsed 458 settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); 459 if (settings_handle != NULL) { 460 const char *item; 461 char *end; 462 uint32 value; 463 464 // for driver 465 item = get_driver_parameter (settings_handle, "accelerant", "", ""); 466 if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { 467 strcpy (current_settings.accelerant, item); 468 } 469 current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); 470 471 // for accelerant 472 item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); 473 value = strtoul (item, &end, 0); 474 if (*end == '\0') current_settings.logmask = value; 475 476 item = get_driver_parameter (settings_handle, "memory", "0", "0"); 477 value = strtoul (item, &end, 0); 478 if (*end == '\0') current_settings.memory = value; 479 480 current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); 481 current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); 482 current_settings.switchhead = get_driver_boolean_parameter (settings_handle, "switchhead", false, false); 483 current_settings.force_pci = get_driver_boolean_parameter (settings_handle, "force_pci", false, false); 484 current_settings.unhide_fw = get_driver_boolean_parameter (settings_handle, "unhide_fw", false, false); 485 current_settings.pgm_panel = get_driver_boolean_parameter (settings_handle, "pgm_panel", false, false); 486 current_settings.dma_acc = get_driver_boolean_parameter (settings_handle, "dma_acc", false, false); 487 488 unload_driver_settings (settings_handle); 489 } 490 491 /* get a handle for the pci bus */ 492 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 493 return B_ERROR; 494 495 /* get a handle for the isa bus */ 496 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 497 { 498 put_module(B_PCI_MODULE_NAME); 499 return B_ERROR; 500 } 501 502 /* get a handle for the agp bus if it exists */ 503 get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus); 504 505 /* driver private data */ 506 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 507 if (!pd) { 508 put_module(B_PCI_MODULE_NAME); 509 return B_ERROR; 510 } 511 /* initialize the benaphore */ 512 INIT_BEN(pd->kernel); 513 /* find all of our supported devices */ 514 probe_devices(); 515 return B_OK; 516 } 517 518 const char ** 519 publish_devices(void) { 520 /* return the list of supported devices */ 521 return (const char **)pd->device_names; 522 } 523 524 device_hooks * 525 find_device(const char *name) { 526 int index = 0; 527 while (pd->device_names[index]) { 528 if (strcmp(name, pd->device_names[index]) == 0) 529 return &graphics_device_hooks; 530 index++; 531 } 532 return NULL; 533 534 } 535 536 void uninit_driver(void) { 537 538 /* free the driver data */ 539 DELETE_BEN(pd->kernel); 540 free(pd); 541 pd = NULL; 542 543 /* put the pci module away */ 544 put_module(B_PCI_MODULE_NAME); 545 put_module(B_ISA_MODULE_NAME); 546 547 /* put the agp module away if it's there */ 548 if (agp_bus) put_module(B_AGP_MODULE_NAME); 549 } 550 551 static status_t map_device(device_info *di) 552 { 553 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 554 shared_info *si = di->si; 555 uint32 tmpUlong; 556 pci_info *pcii = &(di->pcii); 557 system_info sysinfo; 558 559 /*storage for the physical to virtual table (used for dma buffer)*/ 560 // physical_entry physical_memory[2]; 561 // #define G400_DMA_BUFFER_SIZE 1024*1024 562 563 /* variables for making copy of ROM */ 564 uint8* rom_temp; 565 area_id rom_area; 566 567 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 568 int registers = 0; 569 int frame_buffer = 1; 570 // int pseudo_dma = 2; 571 572 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 573 tmpUlong = get_pci(PCI_command, 2); 574 /* enable PCI access */ 575 tmpUlong |= PCI_command_memory; 576 /* enable busmastering */ 577 tmpUlong |= PCI_command_master; 578 /* disable ISA I/O access */ 579 tmpUlong &= ~PCI_command_io; 580 set_pci(PCI_command, 2, tmpUlong); 581 582 /*work out which version of BeOS is running*/ 583 get_system_info(&sysinfo); 584 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 585 { 586 si->use_clone_bugfix = 1; 587 } 588 else 589 { 590 si->use_clone_bugfix = 0; 591 } 592 593 /* work out a name for the register mapping */ 594 sprintf(buffer, DEVICE_FORMAT " regs", 595 di->pcii.vendor_id, di->pcii.device_id, 596 di->pcii.bus, di->pcii.device, di->pcii.function); 597 598 /* get a virtual memory address for the registers*/ 599 si->regs_area = map_physical_memory( 600 buffer, 601 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 602 (void *) di->pcii.u.h0.base_registers_pci[registers], 603 di->pcii.u.h0.base_register_sizes[registers], 604 B_ANY_KERNEL_ADDRESS, 605 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 606 (void **)&(di->regs)); 607 si->clone_bugfix_regs = (uint32 *) di->regs; 608 609 /* if mapping registers to vmem failed then pass on error */ 610 if (si->regs_area < 0) return si->regs_area; 611 612 /* work out a name for the ROM mapping*/ 613 sprintf(buffer, DEVICE_FORMAT " rom", 614 di->pcii.vendor_id, di->pcii.device_id, 615 di->pcii.bus, di->pcii.device, di->pcii.function); 616 617 /* disable ROM shadowing, we want the guaranteed exact contents of the chip */ 618 /* warning: 619 * don't touch: (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 620 * NV18, NV28 and NV34 keep working. 621 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 622 * however the actual ROM content (so the used part) is intact (confirmed). */ 623 //set_pci(NVCFG_ROMSHADOW, 4, 0); 624 625 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 626 tmpUlong = get_pci(PCI_rom_base, 4); 627 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 628 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 629 //legacy space will get us into trouble if we aren't the primary graphics card!! 630 //(as legacy space always has the primary card's ROM 'mapped'!) 631 if (tmpUlong) 632 { 633 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 634 tmpUlong |= 0x00000001; 635 set_pci(PCI_rom_base, 4, tmpUlong); 636 637 rom_area = map_physical_memory( 638 buffer, 639 (void *)di->pcii.u.h0.rom_base_pci, 640 di->pcii.u.h0.rom_size, 641 B_ANY_KERNEL_ADDRESS, 642 B_READ_AREA, 643 (void **)&(rom_temp) 644 ); 645 646 /* check if we got the BIOS signature (might fail on laptops..) */ 647 if (rom_temp[0]!=0x55 || rom_temp[1]!=0xaa) 648 { 649 /* apparantly no ROM is mapped here */ 650 delete_area(rom_area); 651 rom_area = -1; 652 /* force using ISA legacy map as fall-back */ 653 tmpUlong = 0x00000000; 654 } 655 } 656 657 if (!tmpUlong) 658 { 659 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 660 rom_area = map_physical_memory( 661 buffer, 662 (void *)0x000c0000, 663 65536, 664 B_ANY_KERNEL_ADDRESS, 665 B_READ_AREA, 666 (void **)&(rom_temp) 667 ); 668 } 669 670 /* if mapping ROM to vmem failed then clean up and pass on error */ 671 if (rom_area < 0) { 672 delete_area(si->regs_area); 673 si->regs_area = -1; 674 return rom_area; 675 } 676 677 /* dump ROM to file if selected in nv.settings 678 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 679 if (current_settings.dumprom) dumprom (rom_temp, 65536); 680 /* make a copy of ROM for future reference */ 681 memcpy (si->rom_mirror, rom_temp, 65536); 682 683 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 684 tmpUlong = get_pci(PCI_rom_base, 4); 685 tmpUlong &= 0xfffffffe; 686 set_pci(PCI_rom_base, 4, tmpUlong); 687 delete_area(rom_area); 688 689 /* work out a name for the framebuffer mapping*/ 690 sprintf(buffer, DEVICE_FORMAT " framebuffer", 691 di->pcii.vendor_id, di->pcii.device_id, 692 di->pcii.bus, di->pcii.device, di->pcii.function); 693 694 /* map the framebuffer into vmem, using Write Combining*/ 695 si->fb_area = map_physical_memory( 696 buffer, 697 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 698 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 699 di->pcii.u.h0.base_register_sizes[frame_buffer], 700 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 701 B_READ_AREA | B_WRITE_AREA, 702 &(si->framebuffer)); 703 704 /*if failed with write combining try again without*/ 705 if (si->fb_area < 0) { 706 si->fb_area = map_physical_memory( 707 buffer, 708 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 709 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 710 di->pcii.u.h0.base_register_sizes[frame_buffer], 711 B_ANY_KERNEL_BLOCK_ADDRESS, 712 B_READ_AREA | B_WRITE_AREA, 713 &(si->framebuffer)); 714 } 715 716 /* if there was an error, delete our other areas and pass on error*/ 717 if (si->fb_area < 0) 718 { 719 delete_area(si->regs_area); 720 si->regs_area = -1; 721 return si->fb_area; 722 } 723 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 724 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 725 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 726 727 // remember settings for use here and in accelerant 728 si->settings = current_settings; 729 730 /* in any case, return the result */ 731 return si->fb_area; 732 } 733 734 static void unmap_device(device_info *di) { 735 shared_info *si = di->si; 736 uint32 tmpUlong; 737 pci_info *pcii = &(di->pcii); 738 739 /* disable memory mapped IO */ 740 tmpUlong = get_pci(PCI_command, 4); 741 tmpUlong &= 0xfffffffc; 742 set_pci(PCI_command, 4, tmpUlong); 743 /* delete the areas */ 744 if (si->regs_area >= 0) delete_area(si->regs_area); 745 if (si->fb_area >= 0) delete_area(si->fb_area); 746 si->regs_area = si->fb_area = -1; 747 si->framebuffer = NULL; 748 di->regs = NULL; 749 } 750 751 static void probe_devices(void) { 752 uint32 pci_index = 0; 753 uint32 count = 0; 754 device_info *di = pd->di; 755 756 /* while there are more pci devices */ 757 while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { 758 int vendor = 0; 759 760 /* if we match a supported vendor */ 761 while (SupportedDevices[vendor].vendor) { 762 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 763 uint16 *devices = SupportedDevices[vendor].devices; 764 /* while there are more supported devices */ 765 while (*devices) { 766 /* if we match a supported device */ 767 if (*devices == di->pcii.device_id ) { 768 /* publish the device name */ 769 sprintf(di->name, "graphics/" DEVICE_FORMAT, 770 di->pcii.vendor_id, di->pcii.device_id, 771 di->pcii.bus, di->pcii.device, di->pcii.function); 772 773 /* remember the name */ 774 pd->device_names[count] = di->name; 775 /* mark the driver as available for R/W open */ 776 di->is_open = 0; 777 /* mark areas as not yet created */ 778 di->shared_area = -1; 779 /* mark pointer to shared data as invalid */ 780 di->si = NULL; 781 /* inc pointer to device info */ 782 di++; 783 /* inc count */ 784 count++; 785 /* break out of these while loops */ 786 goto next_device; 787 } 788 /* next supported device */ 789 devices++; 790 } 791 } 792 vendor++; 793 } 794 next_device: 795 /* next pci_info struct, please */ 796 pci_index++; 797 } 798 /* propagate count */ 799 pd->count = count; 800 /* terminate list of device names with a null pointer */ 801 pd->device_names[pd->count] = NULL; 802 } 803 804 static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) { 805 uint32 handled = B_HANDLED_INTERRUPT; 806 /* release the vblank semaphore */ 807 if (si->vblank >= 0) { 808 int32 blocked; 809 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 810 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 811 handled = B_INVOKE_SCHEDULER; 812 } 813 } 814 return handled; 815 } 816 817 static int32 818 nv_interrupt(void *data) 819 { 820 int32 handled = B_UNHANDLED_INTERRUPT; 821 device_info *di = (device_info *)data; 822 shared_info *si = di->si; 823 int32 *flags = &(si->flags); 824 vuint32 *regs; 825 826 /* is someone already handling an interrupt for this device? */ 827 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) { 828 goto exit0; 829 } 830 /* get regs */ 831 regs = di->regs; 832 833 /* was it a VBI? */ 834 if (caused_vbi(regs)) { 835 /*clear the interrupt*/ 836 clear_vbi(regs); 837 /*release the semaphore*/ 838 handled = thread_interrupt_work(flags, regs, si); 839 } 840 841 /* note that we're not in the handler any more */ 842 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 843 844 exit0: 845 return handled; 846 } 847 848 static status_t open_hook (const char* name, uint32 flags, void** cookie) { 849 int32 index = 0; 850 device_info *di; 851 shared_info *si; 852 thread_id thid; 853 thread_info thinfo; 854 status_t result = B_OK; 855 vuint32 *regs; 856 char shared_name[B_OS_NAME_LENGTH]; 857 physical_entry map[1]; 858 size_t net_buf_size; 859 void *unaligned_dma_buffer; 860 861 /* find the device name in the list of devices */ 862 /* we're never passed a name we didn't publish */ 863 while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; 864 865 /* for convienience */ 866 di = &(pd->di[index]); 867 868 /* make sure no one else has write access to the common data */ 869 AQUIRE_BEN(pd->kernel); 870 871 /* if it's already open for writing */ 872 if (di->is_open) { 873 /* mark it open another time */ 874 goto mark_as_open; 875 } 876 /* create the shared_info area */ 877 sprintf(shared_name, DEVICE_FORMAT " shared", 878 di->pcii.vendor_id, di->pcii.device_id, 879 di->pcii.bus, di->pcii.device, di->pcii.function); 880 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 881 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 882 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 883 B_USER_CLONEABLE_AREA); 884 if (di->shared_area < 0) { 885 /* return the error */ 886 result = di->shared_area; 887 goto done; 888 } 889 890 /* save a few dereferences */ 891 si = di->si; 892 893 /* create the DMA command buffer area */ 894 //fixme? for R4.5 a workaround for cloning would be needed! 895 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 896 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 897 /* create the area that will hold the DMA command buffer */ 898 si->unaligned_dma_area = 899 create_area("NV DMA cmd buffer", 900 (void **)&unaligned_dma_buffer, 901 B_ANY_KERNEL_ADDRESS, 902 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 903 B_FULL_LOCK | B_CONTIGUOUS, /* both properties needed: GPU always needs access */ 904 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 905 /* on error, abort */ 906 if (si->unaligned_dma_area < 0) 907 { 908 /* free the already created shared_info area, and return the error */ 909 result = si->unaligned_dma_area; 910 goto free_shared; 911 } 912 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 913 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 914 * even on older CPU's. */ 915 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 916 si->dma_buffer_pci = (void*) 917 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 918 919 /* map the net DMA command buffer into vmem, using Write Combining */ 920 si->dma_area = map_physical_memory( 921 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 922 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 923 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 924 /* if failed with write combining try again without */ 925 if (si->dma_area < 0) { 926 si->dma_area = map_physical_memory( 927 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 928 B_ANY_KERNEL_BLOCK_ADDRESS, 929 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 930 } 931 /* if there was an error, delete our other areas and pass on error*/ 932 if (si->dma_area < 0) 933 { 934 /* free the already created areas, and return the error */ 935 result = si->dma_area; 936 goto free_shared_and_uadma; 937 } 938 939 /* save the vendor and device IDs */ 940 si->vendor_id = di->pcii.vendor_id; 941 si->device_id = di->pcii.device_id; 942 si->revision = di->pcii.revision; 943 si->bus = di->pcii.bus; 944 si->device = di->pcii.device; 945 si->function = di->pcii.function; 946 947 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 948 * unified memory architecture (UMA) */ 949 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 950 { 951 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 952 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 953 si->ps.memory_size = 1024 * 1024 * 954 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 955 /* last 64kB RAM is used for the BIOS (or something else?) */ 956 si->ps.memory_size -= (64 * 1024); 957 break; 958 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 959 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 960 si->ps.memory_size = 1024 * 1024 * 961 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 962 /* last 64kB RAM is used for the BIOS (or something else?) */ 963 si->ps.memory_size -= (64 * 1024); 964 break; 965 default: 966 /* all other cards have own RAM: the amount of which is determined in the 967 * accelerant. */ 968 break; 969 } 970 971 /* map the device */ 972 result = map_device(di); 973 if (result < 0) goto free_shared_and_alldma; 974 result = B_OK; 975 976 /* create a semaphore for vertical blank management */ 977 si->vblank = create_sem(0, di->name); 978 if (si->vblank < 0) { 979 result = si->vblank; 980 goto unmap; 981 } 982 983 /* change the owner of the semaphores to the opener's team */ 984 /* this is required because apps can't aquire kernel semaphores */ 985 thid = find_thread(NULL); 986 get_thread_info(thid, &thinfo); 987 set_sem_owner(si->vblank, thinfo.team); 988 989 /* assign local regs pointer for SAMPLExx() macros */ 990 regs = di->regs; 991 992 /* disable and clear any pending interrupts */ 993 disable_vbi(regs); 994 995 /* If there is a valid interrupt line assigned then set up interrupts */ 996 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 997 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 998 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 999 { 1000 /* we are aborting! */ 1001 /* Note: the R4 graphics driver kit lacks this statement!! */ 1002 result = B_ERROR; 1003 /* interrupt does not exist so exit without installing our handler */ 1004 goto delete_the_sem; 1005 } 1006 else 1007 { 1008 /* otherwise install our interrupt handler */ 1009 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1010 /* bail if we couldn't install the handler */ 1011 if (result != B_OK) goto delete_the_sem; 1012 } 1013 1014 mark_as_open: 1015 /* mark the device open */ 1016 di->is_open++; 1017 1018 /* send the cookie to the opener */ 1019 *cookie = di; 1020 1021 goto done; 1022 1023 1024 delete_the_sem: 1025 delete_sem(si->vblank); 1026 1027 unmap: 1028 unmap_device(di); 1029 1030 free_shared_and_alldma: 1031 /* clean up our aligned DMA area */ 1032 delete_area(si->dma_area); 1033 si->dma_area = -1; 1034 si->dma_buffer = NULL; 1035 1036 free_shared_and_uadma: 1037 /* clean up our unaligned DMA area */ 1038 delete_area(si->unaligned_dma_area); 1039 si->unaligned_dma_area = -1; 1040 si->dma_buffer_pci = NULL; 1041 1042 free_shared: 1043 /* clean up our shared area */ 1044 delete_area(di->shared_area); 1045 di->shared_area = -1; 1046 di->si = NULL; 1047 1048 done: 1049 /* end of critical section */ 1050 RELEASE_BEN(pd->kernel); 1051 1052 /* all done, return the status */ 1053 return result; 1054 } 1055 1056 /* ---------- 1057 read_hook - does nothing, gracefully 1058 ----- */ 1059 static status_t 1060 read_hook (void* dev, off_t pos, void* buf, size_t* len) 1061 { 1062 *len = 0; 1063 return B_NOT_ALLOWED; 1064 } 1065 1066 /* ---------- 1067 write_hook - does nothing, gracefully 1068 ----- */ 1069 static status_t 1070 write_hook (void* dev, off_t pos, const void* buf, size_t* len) 1071 { 1072 *len = 0; 1073 return B_NOT_ALLOWED; 1074 } 1075 1076 /* ---------- 1077 close_hook - does nothing, gracefully 1078 ----- */ 1079 static status_t 1080 close_hook (void* dev) 1081 { 1082 /* we don't do anything on close: there might be dup'd fd */ 1083 return B_NO_ERROR; 1084 } 1085 1086 /* ----------- 1087 free_hook - close down the device 1088 ----------- */ 1089 static status_t 1090 free_hook (void* dev) { 1091 device_info *di = (device_info *)dev; 1092 shared_info *si = di->si; 1093 vuint32 *regs = di->regs; 1094 1095 /* lock the driver */ 1096 AQUIRE_BEN(pd->kernel); 1097 1098 /* if opened multiple times, decrement the open count and exit */ 1099 if (di->is_open > 1) 1100 goto unlock_and_exit; 1101 1102 /* disable and clear any pending interrupts */ 1103 disable_vbi(regs); 1104 1105 /* remove interrupt handler */ 1106 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1107 1108 /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ 1109 delete_sem(si->vblank); 1110 si->vblank = -1; 1111 1112 /* free regs and framebuffer areas */ 1113 unmap_device(di); 1114 1115 /* clean up our aligned DMA area */ 1116 delete_area(si->dma_area); 1117 si->dma_area = -1; 1118 si->dma_buffer = NULL; 1119 1120 /* clean up our unaligned DMA area */ 1121 delete_area(si->unaligned_dma_area); 1122 si->unaligned_dma_area = -1; 1123 si->dma_buffer_pci = NULL; 1124 1125 /* clean up our shared area */ 1126 delete_area(di->shared_area); 1127 di->shared_area = -1; 1128 di->si = NULL; 1129 1130 unlock_and_exit: 1131 /* mark the device available */ 1132 di->is_open--; 1133 /* unlock the driver */ 1134 RELEASE_BEN(pd->kernel); 1135 /* all done */ 1136 return B_OK; 1137 } 1138 1139 /* ----------- 1140 control_hook - where the real work is done 1141 ----------- */ 1142 static status_t 1143 control_hook (void* dev, uint32 msg, void *buf, size_t len) { 1144 device_info *di = (device_info *)dev; 1145 status_t result = B_DEV_INVALID_IOCTL; 1146 uint32 tmpUlong; 1147 1148 switch (msg) { 1149 /* the only PUBLIC ioctl */ 1150 case B_GET_ACCELERANT_SIGNATURE: { 1151 char *sig = (char *)buf; 1152 strcpy(sig, current_settings.accelerant); 1153 result = B_OK; 1154 } break; 1155 1156 /* PRIVATE ioctl from here on */ 1157 case NV_GET_PRIVATE_DATA: { 1158 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1159 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1160 gpd->shared_info_area = di->shared_area; 1161 result = B_OK; 1162 } 1163 } break; 1164 case NV_GET_PCI: { 1165 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1166 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1167 pci_info *pcii = &(di->pcii); 1168 gsp->value = get_pci(gsp->offset, gsp->size); 1169 result = B_OK; 1170 } 1171 } break; 1172 case NV_SET_PCI: { 1173 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1174 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1175 pci_info *pcii = &(di->pcii); 1176 set_pci(gsp->offset, gsp->size, gsp->value); 1177 result = B_OK; 1178 } 1179 } break; 1180 case NV_DEVICE_NAME: { // apsed 1181 nv_device_name *dn = (nv_device_name *)buf; 1182 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1183 strcpy(dn->name, di->name); 1184 result = B_OK; 1185 } 1186 } break; 1187 case NV_RUN_INTERRUPTS: { 1188 nv_set_bool_state *ri = (nv_set_bool_state *)buf; 1189 if (ri->magic == NV_PRIVATE_DATA_MAGIC) { 1190 vuint32 *regs = di->regs; 1191 if (ri->do_it) { 1192 enable_vbi(regs); 1193 } else { 1194 disable_vbi(regs); 1195 } 1196 result = B_OK; 1197 } 1198 } break; 1199 case NV_GET_NTH_AGP_INFO: { 1200 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1201 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1202 nai->exist = false; 1203 nai->agp_bus = false; 1204 if (agp_bus) { 1205 nai->agp_bus = true; 1206 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1207 nai->exist = true; 1208 } 1209 } 1210 result = B_OK; 1211 } 1212 } break; 1213 case NV_ENABLE_AGP: { 1214 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1215 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1216 if (agp_bus) { 1217 nca->agp_bus = true; 1218 (*agp_bus->enable_agp)(&(nca->cmd)); 1219 } else { 1220 nca->agp_bus = false; 1221 nca->cmd = 0; 1222 } 1223 result = B_OK; 1224 } 1225 } break; 1226 case NV_ISA_OUT: { 1227 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1228 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1229 pci_info *pcii = &(di->pcii); 1230 1231 /* lock the driver: 1232 * no other graphics card may have ISA I/O enabled when we enter */ 1233 AQUIRE_BEN(pd->kernel); 1234 1235 /* enable ISA I/O access */ 1236 tmpUlong = get_pci(PCI_command, 2); 1237 tmpUlong |= PCI_command_io; 1238 set_pci(PCI_command, 2, tmpUlong); 1239 1240 if (io_isa->size == 1) 1241 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1242 else 1243 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1244 result = B_OK; 1245 1246 /* disable ISA I/O access */ 1247 tmpUlong = get_pci(PCI_command, 2); 1248 tmpUlong &= ~PCI_command_io; 1249 set_pci(PCI_command, 2, tmpUlong); 1250 1251 /* end of critical section */ 1252 RELEASE_BEN(pd->kernel); 1253 } 1254 } break; 1255 case NV_ISA_IN: { 1256 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1257 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1258 pci_info *pcii = &(di->pcii); 1259 1260 /* lock the driver: 1261 * no other graphics card may have ISA I/O enabled when we enter */ 1262 AQUIRE_BEN(pd->kernel); 1263 1264 /* enable ISA I/O access */ 1265 tmpUlong = get_pci(PCI_command, 2); 1266 tmpUlong |= PCI_command_io; 1267 set_pci(PCI_command, 2, tmpUlong); 1268 1269 if (io_isa->size == 1) 1270 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1271 else 1272 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1273 result = B_OK; 1274 1275 /* disable ISA I/O access */ 1276 tmpUlong = get_pci(PCI_command, 2); 1277 tmpUlong &= ~PCI_command_io; 1278 set_pci(PCI_command, 2, tmpUlong); 1279 1280 /* end of critical section */ 1281 RELEASE_BEN(pd->kernel); 1282 } 1283 } break; 1284 } 1285 return result; 1286 } 1287