1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-1/2016. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <directories.h> 21 #include <driver_settings.h> 22 23 #include <stdlib.h> 24 #include <stdio.h> 25 #include <string.h> 26 27 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 28 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 29 30 #define MAX_DEVICES 8 31 32 #ifndef __HAIKU__ 33 # undef B_USER_CLONEABLE_AREA 34 # define B_USER_CLONEABLE_AREA 0 35 #endif 36 37 /* Tell the kernel what revision of the driver API we support */ 38 int32 api_version = B_CUR_DRIVER_API_VERSION; 39 40 /* these structures are private to the kernel driver */ 41 typedef struct device_info device_info; 42 43 typedef struct { 44 timer te; /* timer entry for add_timer() */ 45 device_info *di; /* pointer to the owning device */ 46 bigtime_t when_target; /* when we're supposed to wake up */ 47 } timer_info; 48 49 struct device_info { 50 uint32 is_open; /* a count of how many times the devices has been opened */ 51 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 52 shared_info *si; /* a pointer to the shared area, for convenience */ 53 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 54 pci_info pcii; /* a convenience copy of the pci info for this device */ 55 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 56 }; 57 58 typedef struct { 59 uint32 count; /* number of devices actually found */ 60 benaphore kernel; /* for serializing opens/closes */ 61 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 62 device_info di[MAX_DEVICES]; /* device specific stuff */ 63 } DeviceData; 64 65 /* prototypes for our private functions */ 66 static status_t open_hook(const char* name, uint32 flags, void** cookie); 67 static status_t close_hook(void* dev); 68 static status_t free_hook(void* dev); 69 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 70 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 71 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 72 static status_t map_device(device_info *di); 73 static void unmap_device(device_info *di); 74 static void probe_devices(void); 75 static int32 nv_interrupt(void *data); 76 77 static DeviceData *pd; 78 static isa_module_info *isa_bus = NULL; 79 static pci_module_info *pci_bus = NULL; 80 static agp_gart_module_info *agp_bus = NULL; 81 static device_hooks graphics_device_hooks = { 82 open_hook, 83 close_hook, 84 free_hook, 85 control_hook, 86 read_hook, 87 write_hook, 88 NULL, 89 NULL, 90 NULL, 91 NULL 92 }; 93 94 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 95 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 96 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 97 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 98 99 static uint16 nvidia_device_list[] = { 100 0x0020, /* Nvidia TNT1 */ 101 0x0028, /* Nvidia TNT2 (pro) */ 102 0x0029, /* Nvidia TNT2 Ultra */ 103 0x002a, /* Nvidia TNT2 */ 104 0x002b, /* Nvidia TNT2 */ 105 0x002c, /* Nvidia Vanta (Lt) */ 106 0x002d, /* Nvidia TNT2-M64 (Pro) */ 107 0x002e, /* Nvidia NV06 Vanta */ 108 0x002f, /* Nvidia NV06 Vanta */ 109 0x0040, /* Nvidia Geforce FX 6800 Ultra */ 110 0x0041, /* Nvidia Geforce FX 6800 */ 111 0x0042, /* Nvidia Geforce FX 6800LE */ 112 0x0043, /* Nvidia Geforce 6800 XE */ 113 0x0045, /* Nvidia Geforce FX 6800 GT */ 114 0x0046, /* Nvidia Geforce FX 6800 GT */ 115 0x0047, /* Nvidia Geforce 6800 GS */ 116 0x0048, /* Nvidia Geforce FX 6800 XT */ 117 0x0049, /* Nvidia unknown FX */ 118 0x004d, /* Nvidia Quadro FX 4400 */ 119 0x004e, /* Nvidia Quadro FX 4000 */ 120 0x0091, /* Nvidia Geforce 7800 GTX PCIe */ 121 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 122 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 123 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 124 0x009d, /* Nvidia Quadro FX 4500 */ 125 0x00a0, /* Nvidia Aladdin TNT2 */ 126 0x00c0, /* Nvidia Geforce 6800 GS */ 127 0x00c1, /* Nvidia Geforce FX 6800 */ 128 0x00c2, /* Nvidia Geforce FX 6800LE */ 129 0x00c3, /* Nvidia Geforce FX 6800 XT */ 130 0x00c8, /* Nvidia Geforce FX 6800 Go */ 131 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */ 132 0x00cc, /* Nvidia Quadro FX 1400 Go */ 133 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 134 0x00ce, /* Nvidia Quadro FX 1400 */ 135 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */ 136 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */ 137 0x00f2, /* Nvidia Geforce FX 6600 AGP */ 138 0x00f3, /* Nvidia Geforce 6200 */ 139 0x00f4, /* Nvidia Geforce 6600 LE */ 140 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */ 141 0x00f6, /* Nvidia Geforce 6800 GS */ 142 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 143 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */ 144 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */ 145 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */ 146 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */ 147 0x00fd, /* Nvidia Quadro PCX PCIe */ 148 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 149 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */ 150 0x0100, /* Nvidia Geforce256 SDR */ 151 0x0101, /* Nvidia Geforce256 DDR */ 152 0x0102, /* Nvidia Geforce256 Ultra */ 153 0x0103, /* Nvidia Quadro */ 154 0x0110, /* Nvidia Geforce2 MX/MX400 */ 155 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */ 156 0x0112, /* Nvidia Geforce2 Go */ 157 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 158 0x0140, /* Nvidia Geforce FX 6600 GT */ 159 0x0141, /* Nvidia Geforce FX 6600 */ 160 0x0142, /* Nvidia Geforce FX 6600LE */ 161 0x0143, /* Nvidia Geforce 6600 VE */ 162 0x0144, /* Nvidia Geforce FX 6600 Go */ 163 0x0145, /* Nvidia Geforce FX 6610 XL */ 164 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */ 165 0x0147, /* Nvidia Geforce FX 6700 XL */ 166 0x0148, /* Nvidia Geforce FX 6600 Go */ 167 0x0149, /* Nvidia Geforce FX 6600 GT Go */ 168 0x014b, /* Nvidia unknown FX */ 169 0x014c, /* Nvidia Quadro FX 540 MXM */ 170 0x014d, /* Nvidia unknown FX */ 171 0x014e, /* Nvidia Quadro FX 540 */ 172 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */ 173 0x0150, /* Nvidia Geforce2 GTS/Pro */ 174 0x0151, /* Nvidia Geforce2 Ti DDR */ 175 0x0152, /* Nvidia Geforce2 Ultra */ 176 0x0153, /* Nvidia Quadro2 Pro */ 177 0x0160, /* Nvidia Geforce 6500 Go */ 178 0x0161, /* Nvidia Geforce 6200 TurboCache */ 179 0x0162, /* Nvidia Geforce 6200SE TurboCache */ 180 0x0163, /* Nvidia Geforce 6200LE */ 181 0x0164, /* Nvidia Geforce FX 6200 Go */ 182 0x0165, /* Nvidia Quadro FX NVS 285 */ 183 0x0166, /* Nvidia Geforce 6400 Go */ 184 0x0167, /* Nvidia Geforce 6200 Go */ 185 0x0168, /* Nvidia Geforce 6400 Go */ 186 0x0169, /* Nvidia Geforce 6250 Go */ 187 0x016a, /* Nvidia Geforce 7100 GS */ 188 0x016b, /* Nvidia unknown FX Go */ 189 0x016c, /* Nvidia unknown FX Go */ 190 0x016d, /* Nvidia unknown FX Go */ 191 0x016e, /* Nvidia unknown FX */ 192 0x0170, /* Nvidia Geforce4 MX 460 */ 193 0x0171, /* Nvidia Geforce4 MX 440 */ 194 0x0172, /* Nvidia Geforce4 MX 420 */ 195 0x0173, /* Nvidia Geforce4 MX 440SE */ 196 0x0174, /* Nvidia Geforce4 440 Go */ 197 0x0175, /* Nvidia Geforce4 420 Go */ 198 0x0176, /* Nvidia Geforce4 420 Go 32M */ 199 0x0177, /* Nvidia Geforce4 460 Go */ 200 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 201 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */ 202 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 203 0x017c, /* Nvidia Quadro4 500 GoGL */ 204 0x017d, /* Nvidia Geforce4 410 Go 16M */ 205 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */ 206 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */ 207 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */ 208 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */ 209 0x0186, /* Nvidia Geforce4 448 Go */ 210 0x0187, /* Nvidia Geforce4 488 Go */ 211 0x0188, /* Nvidia Quadro4 580 XGL */ 212 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */ 213 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 214 0x018b, /* Nvidia Quadro4 380 XGL */ 215 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 216 0x018d, /* Nvidia Geforce4 448 Go */ 217 0x01a0, /* Nvidia Geforce2 Integrated GPU */ 218 0x01d1, /* Nvidia Geforce 7300 LE */ 219 0x01d3, /* Nvidia Geforce 7300 SE */ 220 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */ 221 0x01d8, /* Nvidia Geforce 7400 GO */ 222 0x01dd, /* Nvidia Geforce 7500 LE */ 223 0x01df, /* Nvidia Geforce 7300 GS */ 224 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */ 225 0x0200, /* Nvidia Geforce3 */ 226 0x0201, /* Nvidia Geforce3 Ti 200 */ 227 0x0202, /* Nvidia Geforce3 Ti 500 */ 228 0x0203, /* Nvidia Quadro DCC */ 229 0x0211, /* Nvidia Geforce FX 6800 */ 230 0x0212, /* Nvidia Geforce FX 6800LE */ 231 0x0215, /* Nvidia Geforce FX 6800 GT */ 232 0x0218, /* Nvidia Geforce 6800 XT */ 233 0x0220, /* Nvidia unknown FX */ 234 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */ 235 0x0222, /* Nvidia unknown FX */ 236 0x0228, /* Nvidia unknown FX Go */ 237 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */ 238 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */ 239 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */ 240 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */ 241 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */ 242 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */ 243 0x0250, /* Nvidia Geforce4 Ti 4600 */ 244 0x0251, /* Nvidia Geforce4 Ti 4400 */ 245 0x0252, /* Nvidia Geforce4 Ti 4600 */ 246 0x0253, /* Nvidia Geforce4 Ti 4200 */ 247 0x0258, /* Nvidia Quadro4 900 XGL */ 248 0x0259, /* Nvidia Quadro4 750 XGL */ 249 0x025b, /* Nvidia Quadro4 700 XGL */ 250 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */ 251 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */ 252 0x0282, /* Nvidia Geforce4 Ti 4800SE */ 253 0x0286, /* Nvidia Geforce4 4200 Go */ 254 0x0288, /* Nvidia Quadro4 980 XGL */ 255 0x0289, /* Nvidia Quadro4 780 XGL */ 256 0x028c, /* Nvidia Quadro4 700 GoGL */ 257 0x0290, /* Nvidia Geforce 7900 GTX */ 258 0x0291, /* Nvidia Geforce 7900 GT */ 259 0x0292, /* Nvidia Geforce 7900 GS */ 260 0x0293, /* Nvidia Geforce 7900 GX2 */ 261 0x0294, /* Nvidia Geforce 7950 GX2 */ 262 0x0295, /* Nvidia Geforce 7950 GT */ 263 0x0298, /* Nvidia Geforce Go 7900 GS */ 264 0x0299, /* Nvidia Geforce Go 7900 GTX */ 265 0x029c, /* Nvidia Quadro FX 5500 */ 266 0x029f, /* Nvidia Quadro FX 4500 X2 */ 267 0x02a0, /* Nvidia Geforce3 Integrated GPU */ 268 0x02e0, /* Nvidia Geforce 7600 GT */ 269 0x02e1, /* Nvidia Geforce 7600 GS */ 270 0x02e2, /* Nvidia Geforce 7300 GT */ 271 0x0301, /* Nvidia Geforce FX 5800 Ultra */ 272 0x0302, /* Nvidia Geforce FX 5800 */ 273 0x0308, /* Nvidia Quadro FX 2000 */ 274 0x0309, /* Nvidia Quadro FX 1000 */ 275 0x0311, /* Nvidia Geforce FX 5600 Ultra */ 276 0x0312, /* Nvidia Geforce FX 5600 */ 277 0x0313, /* Nvidia unknown FX */ 278 0x0314, /* Nvidia Geforce FX 5600XT */ 279 0x0316, /* Nvidia unknown FX Go */ 280 0x0317, /* Nvidia unknown FX Go */ 281 0x031a, /* Nvidia Geforce FX 5600 Go */ 282 0x031b, /* Nvidia Geforce FX 5650 Go */ 283 0x031c, /* Nvidia Quadro FX 700 Go */ 284 0x031d, /* Nvidia unknown FX Go */ 285 0x031e, /* Nvidia unknown FX Go */ 286 0x031f, /* Nvidia unknown FX Go */ 287 0x0320, /* Nvidia Geforce FX 5200 */ 288 0x0321, /* Nvidia Geforce FX 5200 Ultra */ 289 0x0322, /* Nvidia Geforce FX 5200 */ 290 0x0323, /* Nvidia Geforce FX 5200LE */ 291 0x0324, /* Nvidia Geforce FX 5200 Go */ 292 0x0325, /* Nvidia Geforce FX 5250 Go */ 293 0x0326, /* Nvidia Geforce FX 5500 */ 294 0x0327, /* Nvidia Geforce FX 5100 */ 295 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */ 296 0x0329, /* Nvidia Geforce FX 5200 (PPC) */ 297 0x032a, /* Nvidia Quadro NVS 280 PCI */ 298 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 299 0x032c, /* Nvidia Geforce FX 5300 Go */ 300 0x032d, /* Nvidia Geforce FX 5100 Go */ 301 0x032e, /* Nvidia unknown FX Go */ 302 0x032f, /* Nvidia unknown FX Go */ 303 0x0330, /* Nvidia Geforce FX 5900 Ultra */ 304 0x0331, /* Nvidia Geforce FX 5900 */ 305 0x0332, /* Nvidia Geforce FX 5900 XT */ 306 0x0333, /* Nvidia Geforce FX 5950 Ultra */ 307 0x0334, /* Nvidia Geforce FX 5900 ZT */ 308 0x0338, /* Nvidia Quadro FX 3000 */ 309 0x033f, /* Nvidia Quadro FX 700 */ 310 0x0341, /* Nvidia Geforce FX 5700 Ultra */ 311 0x0342, /* Nvidia Geforce FX 5700 */ 312 0x0343, /* Nvidia Geforce FX 5700LE */ 313 0x0344, /* Nvidia Geforce FX 5700VE */ 314 0x0345, /* Nvidia unknown FX */ 315 0x0347, /* Nvidia Geforce FX 5700 Go */ 316 0x0348, /* Nvidia Geforce FX 5700 Go */ 317 0x0349, /* Nvidia unknown FX Go */ 318 0x034b, /* Nvidia unknown FX Go */ 319 0x034c, /* Nvidia Quadro FX 1000 Go */ 320 0x034e, /* Nvidia Quadro FX 1100 */ 321 0x034f, /* Nvidia unknown FX */ 322 0x0391, /* Nvidia Geforce 7600 GT */ 323 0x0392, /* Nvidia Geforce 7600 GS */ 324 0x0393, /* Nvidia Geforce 7300 GT */ 325 0x0394, /* Nvidia Geforce 7600 LE */ 326 0x0398, /* Nvidia Geforce 7600 GO */ 327 0x03d0, /* Nvidia Geforce 6100 nForce 430 */ 328 0x03d1, /* Nvidia Geforce 6100 nForce 405 */ 329 0x03d2, /* Nvidia Geforce 6100 nForce 400 */ 330 0x03d5, /* Nvidia Geforce 6100 nForce 420 */ 331 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */ 332 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */ 333 0 334 }; 335 336 static uint16 elsa_device_list[] = { 337 0x0c60, /* Elsa Gladiac Geforce2 MX */ 338 0 339 }; 340 341 static uint16 nvstbsgs_device_list[] = { 342 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 343 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 344 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 345 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 346 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 347 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 348 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 349 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 350 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 351 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 352 0 353 }; 354 355 static uint16 varisys_device_list[] = { 356 0x3503, /* Varisys Geforce4 MX440 */ 357 0x3505, /* Varisys Geforce4 Ti 4200 */ 358 0 359 }; 360 361 static struct { 362 uint16 vendor; 363 uint16 *devices; 364 } SupportedDevices[] = { 365 {VENDOR_ID_NVIDIA, nvidia_device_list}, 366 {VENDOR_ID_ELSA, elsa_device_list}, 367 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 368 {VENDOR_ID_VARISYS, varisys_device_list}, 369 {0x0000, NULL} 370 }; 371 372 static nv_settings sSettings = { // see comments in nvidia.settings 373 /* for driver */ 374 DRIVER_PREFIX ".accelerant", 375 "none", // primary 376 false, // dumprom 377 /* for accelerant */ 378 0x00000000, // logmask 379 0, // memory 380 0, // tv_output 381 true, // usebios 382 true, // hardcursor 383 false, // switchhead 384 false, // force_pci 385 false, // unhide_fw 386 false, // pgm_panel 387 true, // dma_acc 388 false, // vga_on_tv 389 false, // force_sync 390 false, // force_ws 391 false, // block_acc 392 0, // gpu_clk 393 0, // ram_clk 394 true, // check_edid 395 }; 396 397 398 static void 399 dumprom(void *rom, uint32 size, pci_info pcii) 400 { 401 int fd; 402 uint32 cnt; 403 char fname[64]; 404 405 /* determine the romfile name: we need split-up per card in the system */ 406 sprintf (fname, kUserDirectory "//" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 407 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 408 409 fd = open (fname, O_WRONLY | O_CREAT, 0666); 410 if (fd < 0) return; 411 412 /* apparantly max. 32kb may be written at once; 413 * the ROM size is a multiple of that anyway. */ 414 for (cnt = 0; (cnt < size); cnt += 32768) 415 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 416 close (fd); 417 } 418 419 420 /*! return 1 if vblank interrupt has occured */ 421 static int 422 caused_vbi_crtc1(vuint32 * regs) 423 { 424 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 425 } 426 427 428 /*! clear the vblank interrupt */ 429 static void 430 clear_vbi_crtc1(vuint32 * regs) 431 { 432 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 433 } 434 435 436 static void 437 enable_vbi_crtc1(vuint32 * regs) 438 { 439 /* clear the vblank interrupt */ 440 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 441 /* enable nVidia interrupt source vblank */ 442 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 443 /* enable nVidia interrupt system hardware (b0-1) */ 444 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 445 } 446 447 448 static void 449 disable_vbi_crtc1(vuint32 * regs) 450 { 451 /* disable nVidia interrupt source vblank */ 452 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 453 /* clear the vblank interrupt */ 454 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 455 } 456 457 458 /*! return 1 if vblank interrupt has occured */ 459 static int 460 caused_vbi_crtc2(vuint32 * regs) 461 { 462 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 463 } 464 465 466 /*! clear the vblank interrupt */ 467 static void 468 clear_vbi_crtc2(vuint32 * regs) 469 { 470 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 471 } 472 473 474 static void 475 enable_vbi_crtc2(vuint32 * regs) 476 { 477 /* clear the vblank interrupt */ 478 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 479 /* enable nVidia interrupt source vblank */ 480 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 481 /* enable nVidia interrupt system hardware (b0-1) */ 482 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 483 } 484 485 486 static void 487 disable_vbi_crtc2(vuint32 * regs) 488 { 489 /* disable nVidia interrupt source vblank */ 490 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 491 /* clear the vblank interrupt */ 492 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 493 } 494 495 496 //fixme: 497 //dangerous code, on singlehead cards better not try accessing secondary head 498 //registers (card might react in unpredictable ways, though there's only a small 499 //chance we actually run into this). 500 //fix requires (some) card recognition code to be moved from accelerant to 501 //kerneldriver... 502 static void 503 disable_vbi_all(vuint32 * regs) 504 { 505 /* disable nVidia interrupt source vblank */ 506 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 507 /* clear the vblank interrupt */ 508 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 509 510 /* disable nVidia interrupt source vblank */ 511 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 512 /* clear the vblank interrupt */ 513 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 514 515 /* disable nVidia interrupt system hardware (b0-1) */ 516 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 517 } 518 519 520 static status_t 521 map_device(device_info *di) 522 { 523 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 524 shared_info *si = di->si; 525 uint32 tmpUlong, tmpROMshadow; 526 pci_info *pcii = &(di->pcii); 527 system_info sysinfo; 528 529 /* variables for making copy of ROM */ 530 uint8* rom_temp; 531 area_id rom_area = -1; 532 533 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 534 int registers = 0; 535 int frame_buffer = 1; 536 537 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 538 tmpUlong = get_pci(PCI_command, 2); 539 /* enable PCI access */ 540 tmpUlong |= PCI_command_memory; 541 /* enable busmastering */ 542 tmpUlong |= PCI_command_master; 543 /* disable ISA I/O access */ 544 tmpUlong &= ~PCI_command_io; 545 set_pci(PCI_command, 2, tmpUlong); 546 547 /*work out which version of BeOS is running*/ 548 get_system_info(&sysinfo); 549 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 550 { 551 si->use_clone_bugfix = 1; 552 } 553 else 554 { 555 si->use_clone_bugfix = 0; 556 } 557 558 /* work out a name for the register mapping */ 559 sprintf(buffer, DEVICE_FORMAT " regs", 560 di->pcii.vendor_id, di->pcii.device_id, 561 di->pcii.bus, di->pcii.device, di->pcii.function); 562 563 /* get a virtual memory address for the registers*/ 564 si->regs_area = map_physical_memory( 565 buffer, 566 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 567 di->pcii.u.h0.base_registers_pci[registers], 568 di->pcii.u.h0.base_register_sizes[registers], 569 B_ANY_KERNEL_ADDRESS, 570 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 571 (void **)&(di->regs)); 572 si->clone_bugfix_regs = (uint32 *) di->regs; 573 574 /* if mapping registers to vmem failed then pass on error */ 575 if (si->regs_area < 0) return si->regs_area; 576 577 /* work out a name for the ROM mapping*/ 578 sprintf(buffer, DEVICE_FORMAT " rom", 579 di->pcii.vendor_id, di->pcii.device_id, 580 di->pcii.bus, di->pcii.device, di->pcii.function); 581 582 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 583 /* warning: 584 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 585 * NV18, NV28 and NV34 keep working. 586 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 587 * however the actual ROM content (so the used part) is intact (confirmed). */ 588 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 589 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 590 set_pci(NVCFG_ROMSHADOW, 4, 0); 591 592 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 593 tmpUlong = get_pci(PCI_rom_base, 4); 594 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 595 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 596 //legacy space will get us into trouble if we aren't the primary graphics card!! 597 //(as legacy space always has the primary card's ROM 'mapped'!) 598 if (tmpUlong) { 599 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 600 tmpUlong |= 0x00000001; 601 set_pci(PCI_rom_base, 4, tmpUlong); 602 603 rom_area = map_physical_memory( 604 buffer, 605 di->pcii.u.h0.rom_base_pci, 606 di->pcii.u.h0.rom_size, 607 B_ANY_KERNEL_ADDRESS, 608 B_READ_AREA, 609 (void **)&(rom_temp) 610 ); 611 612 /* check if we got the BIOS and signature (might fail on laptops..) */ 613 if (rom_area >= 0) { 614 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 615 /* apparantly no ROM is mapped here */ 616 delete_area(rom_area); 617 rom_area = -1; 618 /* force using ISA legacy map as fall-back */ 619 tmpUlong = 0x00000000; 620 } 621 } else { 622 /* mapping failed: force using ISA legacy map as fall-back */ 623 tmpUlong = 0x00000000; 624 } 625 } 626 627 if (!tmpUlong) { 628 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 629 rom_area = map_physical_memory(buffer, 0x000c0000, 630 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 631 } 632 633 /* if mapping ROM to vmem failed then clean up and pass on error */ 634 if (rom_area < 0) { 635 delete_area(si->regs_area); 636 si->regs_area = -1; 637 return rom_area; 638 } 639 640 /* dump ROM to file if selected in nvidia.settings 641 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 642 if (sSettings.dumprom) 643 dumprom(rom_temp, 65536, di->pcii); 644 645 /* make a copy of ROM for future reference */ 646 memcpy(si->rom_mirror, rom_temp, 65536); 647 648 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 649 tmpUlong = get_pci(PCI_rom_base, 4); 650 tmpUlong &= 0xfffffffe; 651 set_pci(PCI_rom_base, 4, tmpUlong); 652 delete_area(rom_area); 653 654 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 655 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 656 657 /* work out a name for the framebuffer mapping*/ 658 sprintf(buffer, DEVICE_FORMAT " framebuffer", 659 di->pcii.vendor_id, di->pcii.device_id, 660 di->pcii.bus, di->pcii.device, di->pcii.function); 661 662 /* map the framebuffer into vmem, using Write Combining*/ 663 si->fb_area = map_physical_memory(buffer, 664 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 665 di->pcii.u.h0.base_registers_pci[frame_buffer], 666 di->pcii.u.h0.base_register_sizes[frame_buffer], 667 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 668 B_READ_AREA | B_WRITE_AREA, 669 &(si->framebuffer)); 670 671 /*if failed with write combining try again without*/ 672 if (si->fb_area < 0) { 673 si->fb_area = map_physical_memory(buffer, 674 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 675 di->pcii.u.h0.base_registers_pci[frame_buffer], 676 di->pcii.u.h0.base_register_sizes[frame_buffer], 677 B_ANY_KERNEL_BLOCK_ADDRESS, 678 B_READ_AREA | B_WRITE_AREA, 679 &(si->framebuffer)); 680 } 681 682 /* if there was an error, delete our other areas and pass on error*/ 683 if (si->fb_area < 0) { 684 delete_area(si->regs_area); 685 si->regs_area = -1; 686 return si->fb_area; 687 } 688 689 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 690 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 691 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 692 693 /* note the amount of memory mapped by the kerneldriver so we can make sure we 694 * don't attempt to adress more later on */ 695 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 696 697 // remember settings for use here and in accelerant 698 si->settings = sSettings; 699 700 /* in any case, return the result */ 701 return si->fb_area; 702 } 703 704 705 static void 706 unmap_device(device_info *di) 707 { 708 shared_info *si = di->si; 709 uint32 tmpUlong; 710 pci_info *pcii = &(di->pcii); 711 712 /* disable memory mapped IO */ 713 tmpUlong = get_pci(PCI_command, 4); 714 tmpUlong &= 0xfffffffc; 715 set_pci(PCI_command, 4, tmpUlong); 716 /* delete the areas */ 717 if (si->regs_area >= 0) 718 delete_area(si->regs_area); 719 if (si->fb_area >= 0) 720 delete_area(si->fb_area); 721 si->regs_area = si->fb_area = -1; 722 si->framebuffer = NULL; 723 di->regs = NULL; 724 } 725 726 727 static void 728 probe_devices(void) 729 { 730 uint32 pci_index = 0; 731 uint32 count = 0; 732 device_info *di = pd->di; 733 char tmp_name[B_OS_NAME_LENGTH]; 734 735 /* while there are more pci devices */ 736 while (count < MAX_DEVICES 737 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 738 int vendor = 0; 739 740 /* if we match a supported vendor */ 741 while (SupportedDevices[vendor].vendor) { 742 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 743 uint16 *devices = SupportedDevices[vendor].devices; 744 /* while there are more supported devices */ 745 while (*devices) { 746 /* if we match a supported device */ 747 if (*devices == di->pcii.device_id ) { 748 /* publish the device name */ 749 sprintf(tmp_name, DEVICE_FORMAT, 750 di->pcii.vendor_id, di->pcii.device_id, 751 di->pcii.bus, di->pcii.device, di->pcii.function); 752 /* tweak the exported name to show first in the alphabetically ordered /dev/ 753 * hierarchy folder, so the system will use it as primary adaptor if requested 754 * via nvidia.settings. */ 755 if (strcmp(tmp_name, sSettings.primary) == 0) 756 sprintf(tmp_name, "-%s", sSettings.primary); 757 /* add /dev/ hierarchy path */ 758 sprintf(di->name, "graphics/%s", tmp_name); 759 /* remember the name */ 760 pd->device_names[count] = di->name; 761 /* mark the driver as available for R/W open */ 762 di->is_open = 0; 763 /* mark areas as not yet created */ 764 di->shared_area = -1; 765 /* mark pointer to shared data as invalid */ 766 di->si = NULL; 767 /* inc pointer to device info */ 768 di++; 769 /* inc count */ 770 count++; 771 /* break out of these while loops */ 772 goto next_device; 773 } 774 /* next supported device */ 775 devices++; 776 } 777 } 778 vendor++; 779 } 780 next_device: 781 /* next pci_info struct, please */ 782 pci_index++; 783 } 784 /* propagate count */ 785 pd->count = count; 786 /* terminate list of device names with a null pointer */ 787 pd->device_names[pd->count] = NULL; 788 } 789 790 791 static uint32 792 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 793 { 794 uint32 handled = B_HANDLED_INTERRUPT; 795 /* release the vblank semaphore */ 796 if (si->vblank >= 0) { 797 int32 blocked; 798 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 799 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 800 handled = B_INVOKE_SCHEDULER; 801 } 802 } 803 return handled; 804 } 805 806 807 static int32 808 nv_interrupt(void *data) 809 { 810 int32 handled = B_UNHANDLED_INTERRUPT; 811 device_info *di = (device_info *)data; 812 shared_info *si = di->si; 813 int32 *flags = &(si->flags); 814 vuint32 *regs; 815 816 /* is someone already handling an interrupt for this device? */ 817 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 818 819 /* get regs */ 820 regs = di->regs; 821 822 /* was it a VBI? */ 823 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 824 if (si->ps.secondary_head) { 825 //fixme: 826 //rewrite once we use one driver instance 'per head' (instead of 'per card') 827 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 828 /* clear the interrupt(s) */ 829 clear_vbi_crtc1(regs); 830 clear_vbi_crtc2(regs); 831 /* release the semaphore */ 832 handled = thread_interrupt_work(flags, regs, si); 833 } 834 } else { 835 if (caused_vbi_crtc1(regs)) { 836 /* clear the interrupt */ 837 clear_vbi_crtc1(regs); 838 /* release the semaphore */ 839 handled = thread_interrupt_work(flags, regs, si); 840 } 841 } 842 843 /* note that we're not in the handler any more */ 844 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 845 846 exit0: 847 return handled; 848 } 849 850 851 // #pragma mark - device hooks 852 853 854 static status_t 855 open_hook(const char* name, uint32 flags, void** cookie) 856 { 857 int32 index = 0; 858 device_info *di; 859 shared_info *si; 860 thread_id thid; 861 thread_info thinfo; 862 status_t result = B_OK; 863 char shared_name[B_OS_NAME_LENGTH]; 864 physical_entry map[1]; 865 size_t net_buf_size; 866 void *unaligned_dma_buffer; 867 uint32 mem_size; 868 869 /* find the device name in the list of devices */ 870 /* we're never passed a name we didn't publish */ 871 while (pd->device_names[index] 872 && (strcmp(name, pd->device_names[index]) != 0)) 873 index++; 874 875 /* for convienience */ 876 di = &(pd->di[index]); 877 878 /* make sure no one else has write access to the common data */ 879 AQUIRE_BEN(pd->kernel); 880 881 /* if it's already open for writing */ 882 if (di->is_open) { 883 /* mark it open another time */ 884 goto mark_as_open; 885 } 886 /* create the shared_info area */ 887 sprintf(shared_name, DEVICE_FORMAT " shared", 888 di->pcii.vendor_id, di->pcii.device_id, 889 di->pcii.bus, di->pcii.device, di->pcii.function); 890 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 891 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 892 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 893 B_USER_CLONEABLE_AREA); 894 if (di->shared_area < 0) { 895 /* return the error */ 896 result = di->shared_area; 897 goto done; 898 } 899 900 /* save a few dereferences */ 901 si = di->si; 902 903 /* create the DMA command buffer area */ 904 //fixme? for R4.5 a workaround for cloning would be needed! 905 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 906 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 907 /* create the area that will hold the DMA command buffer */ 908 si->unaligned_dma_area = 909 create_area("NV DMA cmd buffer", 910 (void **)&unaligned_dma_buffer, 911 B_ANY_KERNEL_ADDRESS, 912 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 913 B_32_BIT_CONTIGUOUS, /* GPU always needs access */ 914 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 915 // TODO: Physical aligning can be done without waste using the 916 // private create_area_etc(). 917 /* on error, abort */ 918 if (si->unaligned_dma_area < 0) 919 { 920 /* free the already created shared_info area, and return the error */ 921 result = si->unaligned_dma_area; 922 goto free_shared; 923 } 924 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 925 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 926 * even on older CPU's. */ 927 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 928 si->dma_buffer_pci = (void*) 929 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); 930 931 /* map the net DMA command buffer into vmem, using Write Combining */ 932 si->dma_area = map_physical_memory( 933 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, 934 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 935 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 936 /* if failed with write combining try again without */ 937 if (si->dma_area < 0) { 938 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer", 939 (addr_t)si->dma_buffer_pci, net_buf_size, 940 B_ANY_KERNEL_BLOCK_ADDRESS, 941 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 942 } 943 /* if there was an error, delete our other areas and pass on error*/ 944 if (si->dma_area < 0) 945 { 946 /* free the already created areas, and return the error */ 947 result = si->dma_area; 948 goto free_shared_and_uadma; 949 } 950 951 /* save the vendor and device IDs */ 952 si->vendor_id = di->pcii.vendor_id; 953 si->device_id = di->pcii.device_id; 954 si->revision = di->pcii.revision; 955 si->bus = di->pcii.bus; 956 si->device = di->pcii.device; 957 si->function = di->pcii.function; 958 959 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 960 si->accelerant_in_use = false; 961 /* preset singlehead card to prevent early INT routine calls (once installed) to 962 * wrongly identify the INT request coming from us! */ 963 si->ps.secondary_head = false; 964 965 /* map the device */ 966 result = map_device(di); 967 if (result < 0) goto free_shared_and_alldma; 968 969 /* we will be returning OK status for sure now */ 970 result = B_OK; 971 972 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 973 * unified memory architecture (UMA) */ 974 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 975 { 976 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */ 977 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 978 mem_size = 1024 * 1024 * 979 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 980 /* don't attempt to adress memory not mapped by the kerneldriver */ 981 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 982 /* last 64kB RAM is used for the BIOS (or something else?) */ 983 si->ps.memory_size -= (64 * 1024); 984 break; 985 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */ 986 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 987 mem_size = 1024 * 1024 * 988 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 989 /* don't attempt to adress memory not mapped by the kerneldriver */ 990 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 991 /* last 64kB RAM is used for the BIOS (or something else?) */ 992 si->ps.memory_size -= (64 * 1024); 993 break; 994 default: 995 /* all other cards have own RAM: the amount of which is determined in the 996 * accelerant. */ 997 break; 998 } 999 1000 /* disable and clear any pending interrupts */ 1001 //fixme: 1002 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1003 disable_vbi_all(di->regs); 1004 1005 /* preset we can't use INT related functions */ 1006 si->ps.int_assigned = false; 1007 1008 /* create a semaphore for vertical blank management */ 1009 si->vblank = create_sem(0, di->name); 1010 if (si->vblank < 0) goto mark_as_open; 1011 1012 /* change the owner of the semaphores to the opener's team */ 1013 /* this is required because apps can't aquire kernel semaphores */ 1014 thid = find_thread(NULL); 1015 get_thread_info(thid, &thinfo); 1016 set_sem_owner(si->vblank, thinfo.team); 1017 1018 /* If there is a valid interrupt line assigned then set up interrupts */ 1019 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1020 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1021 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1022 { 1023 /* delete the semaphore as it won't be used */ 1024 delete_sem(si->vblank); 1025 si->vblank = -1; 1026 } 1027 else 1028 { 1029 /* otherwise install our interrupt handler */ 1030 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1031 /* bail if we couldn't install the handler */ 1032 if (result != B_OK) 1033 { 1034 /* delete the semaphore as it won't be used */ 1035 delete_sem(si->vblank); 1036 si->vblank = -1; 1037 } 1038 else 1039 { 1040 /* inform accelerant(s) we can use INT related functions */ 1041 si->ps.int_assigned = true; 1042 } 1043 } 1044 1045 mark_as_open: 1046 /* mark the device open */ 1047 di->is_open++; 1048 1049 /* send the cookie to the opener */ 1050 *cookie = di; 1051 1052 goto done; 1053 1054 1055 free_shared_and_alldma: 1056 /* clean up our aligned DMA area */ 1057 delete_area(si->dma_area); 1058 si->dma_area = -1; 1059 si->dma_buffer = NULL; 1060 1061 free_shared_and_uadma: 1062 /* clean up our unaligned DMA area */ 1063 delete_area(si->unaligned_dma_area); 1064 si->unaligned_dma_area = -1; 1065 si->dma_buffer_pci = NULL; 1066 1067 free_shared: 1068 /* clean up our shared area */ 1069 delete_area(di->shared_area); 1070 di->shared_area = -1; 1071 di->si = NULL; 1072 1073 done: 1074 /* end of critical section */ 1075 RELEASE_BEN(pd->kernel); 1076 1077 /* all done, return the status */ 1078 return result; 1079 } 1080 1081 1082 static status_t 1083 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1084 { 1085 *len = 0; 1086 return B_NOT_ALLOWED; 1087 } 1088 1089 1090 static status_t 1091 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1092 { 1093 *len = 0; 1094 return B_NOT_ALLOWED; 1095 } 1096 1097 1098 static status_t 1099 close_hook(void* dev) 1100 { 1101 /* we don't do anything on close: there might be dup'd fd */ 1102 return B_NO_ERROR; 1103 } 1104 1105 1106 static status_t 1107 free_hook(void* dev) 1108 { 1109 device_info *di = (device_info *)dev; 1110 shared_info *si = di->si; 1111 vuint32 *regs = di->regs; 1112 1113 /* lock the driver */ 1114 AQUIRE_BEN(pd->kernel); 1115 1116 /* if opened multiple times, decrement the open count and exit */ 1117 if (di->is_open > 1) 1118 goto unlock_and_exit; 1119 1120 /* disable and clear any pending interrupts */ 1121 //fixme: 1122 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1123 disable_vbi_all(regs); 1124 1125 if (si->ps.int_assigned) { 1126 /* remove interrupt handler */ 1127 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1128 1129 /* delete the semaphores, ignoring any errors ('cause the owning 1130 team may have died on us) */ 1131 delete_sem(si->vblank); 1132 si->vblank = -1; 1133 } 1134 1135 /* free regs and framebuffer areas */ 1136 unmap_device(di); 1137 1138 /* clean up our aligned DMA area */ 1139 delete_area(si->dma_area); 1140 si->dma_area = -1; 1141 si->dma_buffer = NULL; 1142 1143 /* clean up our unaligned DMA area */ 1144 delete_area(si->unaligned_dma_area); 1145 si->unaligned_dma_area = -1; 1146 si->dma_buffer_pci = NULL; 1147 1148 /* clean up our shared area */ 1149 delete_area(di->shared_area); 1150 di->shared_area = -1; 1151 di->si = NULL; 1152 1153 unlock_and_exit: 1154 /* mark the device available */ 1155 di->is_open--; 1156 /* unlock the driver */ 1157 RELEASE_BEN(pd->kernel); 1158 /* all done */ 1159 return B_OK; 1160 } 1161 1162 1163 static status_t 1164 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1165 { 1166 device_info *di = (device_info *)dev; 1167 status_t result = B_DEV_INVALID_IOCTL; 1168 uint32 tmpUlong; 1169 1170 switch (msg) { 1171 /* the only PUBLIC ioctl */ 1172 case B_GET_ACCELERANT_SIGNATURE: 1173 { 1174 strcpy((char* )buf, sSettings.accelerant); 1175 result = B_OK; 1176 break; 1177 } 1178 1179 /* PRIVATE ioctl from here on */ 1180 case NV_GET_PRIVATE_DATA: 1181 { 1182 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1183 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1184 gpd->shared_info_area = di->shared_area; 1185 result = B_OK; 1186 } 1187 break; 1188 } 1189 1190 case NV_GET_PCI: 1191 { 1192 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1193 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1194 pci_info *pcii = &(di->pcii); 1195 gsp->value = get_pci(gsp->offset, gsp->size); 1196 result = B_OK; 1197 } 1198 break; 1199 } 1200 1201 case NV_SET_PCI: 1202 { 1203 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1204 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1205 pci_info *pcii = &(di->pcii); 1206 set_pci(gsp->offset, gsp->size, gsp->value); 1207 result = B_OK; 1208 } 1209 break; 1210 } 1211 1212 case NV_DEVICE_NAME: 1213 { 1214 nv_device_name *dn = (nv_device_name *)buf; 1215 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1216 strcpy(dn->name, di->name); 1217 result = B_OK; 1218 } 1219 break; 1220 } 1221 1222 case NV_RUN_INTERRUPTS: 1223 { 1224 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1225 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1226 vuint32 *regs = di->regs; 1227 if (!(vi->crtc)) { 1228 if (vi->do_it) { 1229 enable_vbi_crtc1(regs); 1230 } else { 1231 disable_vbi_crtc1(regs); 1232 } 1233 } else { 1234 if (vi->do_it) { 1235 enable_vbi_crtc2(regs); 1236 } else { 1237 disable_vbi_crtc2(regs); 1238 } 1239 } 1240 result = B_OK; 1241 } 1242 break; 1243 } 1244 1245 case NV_GET_NTH_AGP_INFO: 1246 { 1247 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1248 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1249 nai->exist = false; 1250 nai->agp_bus = false; 1251 if (agp_bus) { 1252 nai->agp_bus = true; 1253 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1254 nai->exist = true; 1255 } 1256 } 1257 result = B_OK; 1258 } 1259 break; 1260 } 1261 1262 case NV_ENABLE_AGP: 1263 { 1264 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1265 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1266 if (agp_bus) { 1267 nca->agp_bus = true; 1268 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1269 } else { 1270 nca->agp_bus = false; 1271 nca->cmd = 0; 1272 } 1273 result = B_OK; 1274 } 1275 break; 1276 } 1277 1278 case NV_ISA_OUT: 1279 { 1280 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1281 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1282 pci_info *pcii = &(di->pcii); 1283 1284 /* lock the driver: 1285 * no other graphics card may have ISA I/O enabled when we enter */ 1286 AQUIRE_BEN(pd->kernel); 1287 1288 /* enable ISA I/O access */ 1289 tmpUlong = get_pci(PCI_command, 2); 1290 tmpUlong |= PCI_command_io; 1291 set_pci(PCI_command, 2, tmpUlong); 1292 1293 if (io_isa->size == 1) 1294 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1295 else 1296 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1297 result = B_OK; 1298 1299 /* disable ISA I/O access */ 1300 tmpUlong = get_pci(PCI_command, 2); 1301 tmpUlong &= ~PCI_command_io; 1302 set_pci(PCI_command, 2, tmpUlong); 1303 1304 /* end of critical section */ 1305 RELEASE_BEN(pd->kernel); 1306 } 1307 break; 1308 } 1309 1310 case NV_ISA_IN: 1311 { 1312 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1313 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1314 pci_info *pcii = &(di->pcii); 1315 1316 /* lock the driver: 1317 * no other graphics card may have ISA I/O enabled when we enter */ 1318 AQUIRE_BEN(pd->kernel); 1319 1320 /* enable ISA I/O access */ 1321 tmpUlong = get_pci(PCI_command, 2); 1322 tmpUlong |= PCI_command_io; 1323 set_pci(PCI_command, 2, tmpUlong); 1324 1325 if (io_isa->size == 1) 1326 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1327 else 1328 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1329 result = B_OK; 1330 1331 /* disable ISA I/O access */ 1332 tmpUlong = get_pci(PCI_command, 2); 1333 tmpUlong &= ~PCI_command_io; 1334 set_pci(PCI_command, 2, tmpUlong); 1335 1336 /* end of critical section */ 1337 RELEASE_BEN(pd->kernel); 1338 } 1339 break; 1340 } 1341 } 1342 1343 return result; 1344 } 1345 1346 1347 // #pragma mark - driver API 1348 1349 1350 status_t 1351 init_hardware(void) 1352 { 1353 long index = 0; 1354 pci_info pcii; 1355 bool found = false; 1356 1357 /* choke if we can't find the PCI bus */ 1358 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1359 return B_ERROR; 1360 1361 /* choke if we can't find the ISA bus */ 1362 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1363 { 1364 put_module(B_PCI_MODULE_NAME); 1365 return B_ERROR; 1366 } 1367 1368 /* while there are more pci devices */ 1369 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1370 int vendor = 0; 1371 1372 /* if we match a supported vendor */ 1373 while (SupportedDevices[vendor].vendor) { 1374 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1375 uint16 *devices = SupportedDevices[vendor].devices; 1376 /* while there are more supported devices */ 1377 while (*devices) { 1378 /* if we match a supported device */ 1379 if (*devices == pcii.device_id ) { 1380 1381 found = true; 1382 goto done; 1383 } 1384 /* next supported device */ 1385 devices++; 1386 } 1387 } 1388 vendor++; 1389 } 1390 /* next pci_info struct, please */ 1391 index++; 1392 } 1393 1394 done: 1395 /* put away the module manager */ 1396 put_module(B_PCI_MODULE_NAME); 1397 return found ? B_OK : B_ERROR; 1398 } 1399 1400 1401 status_t 1402 init_driver(void) 1403 { 1404 void *settings; 1405 1406 // get driver/accelerant settings 1407 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1408 if (settings != NULL) { 1409 const char *item; 1410 char *end; 1411 uint32 value; 1412 1413 // for driver 1414 item = get_driver_parameter(settings, "accelerant", "", ""); 1415 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1416 strcpy (sSettings.accelerant, item); 1417 1418 item = get_driver_parameter(settings, "primary", "", ""); 1419 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1420 strcpy(sSettings.primary, item); 1421 1422 sSettings.dumprom = get_driver_boolean_parameter(settings, 1423 "dumprom", false, false); 1424 1425 // for accelerant 1426 item = get_driver_parameter(settings, "logmask", 1427 "0x00000000", "0x00000000"); 1428 value = strtoul(item, &end, 0); 1429 if (*end == '\0') 1430 sSettings.logmask = value; 1431 1432 item = get_driver_parameter(settings, "memory", "0", "0"); 1433 value = strtoul(item, &end, 0); 1434 if (*end == '\0') 1435 sSettings.memory = value; 1436 1437 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1438 value = strtoul(item, &end, 0); 1439 if (*end == '\0') 1440 sSettings.tv_output = value; 1441 1442 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1443 "hardcursor", true, true); 1444 sSettings.usebios = get_driver_boolean_parameter(settings, 1445 "usebios", true, true); 1446 sSettings.switchhead = get_driver_boolean_parameter(settings, 1447 "switchhead", false, false); 1448 sSettings.force_pci = get_driver_boolean_parameter(settings, 1449 "force_pci", false, false); 1450 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1451 "unhide_fw", false, false); 1452 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1453 "pgm_panel", false, false); 1454 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1455 "dma_acc", true, true); 1456 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1457 "vga_on_tv", false, false); 1458 sSettings.force_sync = get_driver_boolean_parameter(settings, 1459 "force_sync", false, false); 1460 sSettings.force_ws = get_driver_boolean_parameter(settings, 1461 "force_ws", false, false); 1462 sSettings.block_acc = get_driver_boolean_parameter(settings, 1463 "block_acc", false, false); 1464 sSettings.check_edid = get_driver_boolean_parameter(settings, 1465 "check_edid", true, true); 1466 1467 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1468 value = strtoul(item, &end, 0); 1469 if (*end == '\0') 1470 sSettings.gpu_clk = value; 1471 1472 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1473 value = strtoul(item, &end, 0); 1474 if (*end == '\0') 1475 sSettings.ram_clk = value; 1476 1477 unload_driver_settings(settings); 1478 } 1479 1480 /* get a handle for the pci bus */ 1481 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1482 return B_ERROR; 1483 1484 /* get a handle for the isa bus */ 1485 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1486 put_module(B_PCI_MODULE_NAME); 1487 return B_ERROR; 1488 } 1489 1490 /* get a handle for the agp bus if it exists */ 1491 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1492 1493 /* driver private data */ 1494 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1495 if (!pd) { 1496 put_module(B_PCI_MODULE_NAME); 1497 return B_ERROR; 1498 } 1499 /* initialize the benaphore */ 1500 INIT_BEN(pd->kernel); 1501 /* find all of our supported devices */ 1502 probe_devices(); 1503 return B_OK; 1504 } 1505 1506 1507 const char ** 1508 publish_devices(void) 1509 { 1510 /* return the list of supported devices */ 1511 return (const char **)pd->device_names; 1512 } 1513 1514 1515 device_hooks * 1516 find_device(const char *name) 1517 { 1518 int index = 0; 1519 while (pd->device_names[index]) { 1520 if (strcmp(name, pd->device_names[index]) == 0) 1521 return &graphics_device_hooks; 1522 index++; 1523 } 1524 return NULL; 1525 1526 } 1527 1528 1529 void 1530 uninit_driver(void) 1531 { 1532 /* free the driver data */ 1533 DELETE_BEN(pd->kernel); 1534 free(pd); 1535 pd = NULL; 1536 1537 /* put the pci module away */ 1538 put_module(B_PCI_MODULE_NAME); 1539 put_module(B_ISA_MODULE_NAME); 1540 1541 /* put the agp module away if it's there */ 1542 if (agp_bus) 1543 put_module(B_AGP_GART_MODULE_NAME); 1544 } 1545 1546