1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-10/2007. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 109 0x0041, /* Nvidia GeForce FX 6800 */ 110 0x0042, /* Nvidia GeForce FX 6800LE */ 111 0x0043, /* Nvidia GeForce 6800 XE */ 112 0x0045, /* Nvidia GeForce FX 6800 GT */ 113 0x0046, /* Nvidia GeForce FX 6800 GT */ 114 0x0047, /* Nvidia GeForce 6800 GS */ 115 0x0048, /* Nvidia GeForce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia GeForce 6800 GS */ 126 0x00c1, /* Nvidia GeForce FX 6800 */ 127 0x00c2, /* Nvidia GeForce FX 6800LE */ 128 0x00c3, /* Nvidia GeForce FX 6800 XT */ 129 0x00c8, /* Nvidia GeForce FX 6800 Go */ 130 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 137 0x00f3, /* Nvidia GeForce 6200 */ 138 0x00f4, /* Nvidia GeForce 6600 LE */ 139 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia GeForce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 149 0x0100, /* Nvidia GeForce256 SDR */ 150 0x0101, /* Nvidia GeForce256 DDR */ 151 0x0102, /* Nvidia GeForce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia GeForce2 MX/MX400 */ 154 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia GeForce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia GeForce FX 6600 GT */ 158 0x0141, /* Nvidia GeForce FX 6600 */ 159 0x0142, /* Nvidia GeForce FX 6600LE */ 160 0x0143, /* Nvidia GeForce 6600 VE */ 161 0x0144, /* Nvidia GeForce FX 6600 Go */ 162 0x0145, /* Nvidia GeForce FX 6610 XL */ 163 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia GeForce FX 6700 XL */ 165 0x0148, /* Nvidia GeForce FX 6600 Go */ 166 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia GeForce2 GTS/Pro */ 173 0x0151, /* Nvidia GeForce2 Ti DDR */ 174 0x0152, /* Nvidia GeForce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia GeForce 6500 Go */ 177 0x0161, /* Nvidia GeForce 6200 TurboCache */ 178 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 179 0x0163, /* Nvidia GeForce 6200LE */ 180 0x0164, /* Nvidia GeForce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia GeForce 6400 Go */ 183 0x0167, /* Nvidia GeForce 6200 Go */ 184 0x0168, /* Nvidia GeForce 6400 Go */ 185 0x0169, /* Nvidia GeForce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia GeForce4 MX 460 */ 192 0x0171, /* Nvidia GeForce4 MX 440 */ 193 0x0172, /* Nvidia GeForce4 MX 420 */ 194 0x0173, /* Nvidia GeForce4 MX 440SE */ 195 0x0174, /* Nvidia GeForce4 440 Go */ 196 0x0175, /* Nvidia GeForce4 420 Go */ 197 0x0176, /* Nvidia GeForce4 420 Go 32M */ 198 0x0177, /* Nvidia GeForce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia GeForce4 410 Go 16M */ 204 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia GeForce4 448 Go */ 209 0x0187, /* Nvidia GeForce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia GeForce4 448 Go */ 216 0x0191, /* Nvidia GeForce 8800 GTX */ 217 0x0193, /* Nvidia GeForce 8800 GTS */ 218 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 219 0x01d1, /* Nvidia GeForce 7300 LE */ 220 0x01d3, /* Nvidia GeForce 7300 SE */ 221 0x01d8, /* Nvidia GeForce 7400 GO */ 222 0x01dd, /* Nvidia GeForce 7500 LE */ 223 0x01df, /* Nvidia GeForce 7300 GS */ 224 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 225 0x0200, /* Nvidia GeForce3 */ 226 0x0201, /* Nvidia GeForce3 Ti 200 */ 227 0x0202, /* Nvidia GeForce3 Ti 500 */ 228 0x0203, /* Nvidia Quadro DCC */ 229 0x0211, /* Nvidia GeForce FX 6800 */ 230 0x0212, /* Nvidia GeForce FX 6800LE */ 231 0x0215, /* Nvidia GeForce FX 6800 GT */ 232 0x0218, /* Nvidia GeForce 6800 XT */ 233 0x0220, /* Nvidia unknown FX */ 234 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 235 0x0222, /* Nvidia unknown FX */ 236 0x0228, /* Nvidia unknown FX Go */ 237 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 238 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 239 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / GeForce 6150LE */ 241 0x0250, /* Nvidia GeForce4 Ti 4600 */ 242 0x0251, /* Nvidia GeForce4 Ti 4400 */ 243 0x0252, /* Nvidia GeForce4 Ti 4600 */ 244 0x0253, /* Nvidia GeForce4 Ti 4200 */ 245 0x0258, /* Nvidia Quadro4 900 XGL */ 246 0x0259, /* Nvidia Quadro4 750 XGL */ 247 0x025b, /* Nvidia Quadro4 700 XGL */ 248 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 249 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 250 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 251 0x0286, /* Nvidia GeForce4 4200 Go */ 252 0x0288, /* Nvidia Quadro4 980 XGL */ 253 0x0289, /* Nvidia Quadro4 780 XGL */ 254 0x028c, /* Nvidia Quadro4 700 GoGL */ 255 0x0290, /* Nvidia GeForce 7900 GTX */ 256 0x0291, /* Nvidia GeForce 7900 GT */ 257 0x0293, /* Nvidia GeForce 7900 GX2 */ 258 0x0294, /* Nvidia GeForce 7950 GX2 */ 259 0x0295, /* Nvidia GeForce 7950 GT */ 260 0x0298, /* Nvidia GeForce Go 7900 GS */ 261 0x0299, /* Nvidia GeForce Go 7900 GTX */ 262 0x029c, /* Nvidia Quadro FX 5500 */ 263 0x029f, /* Nvidia Quadro FX 4500 X2 */ 264 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 265 0x02e1, /* Nvidia GeForce 7600 GS */ 266 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 267 0x0302, /* Nvidia GeForce FX 5800 */ 268 0x0308, /* Nvidia Quadro FX 2000 */ 269 0x0309, /* Nvidia Quadro FX 1000 */ 270 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 271 0x0312, /* Nvidia GeForce FX 5600 */ 272 0x0313, /* Nvidia unknown FX */ 273 0x0314, /* Nvidia GeForce FX 5600XT */ 274 0x0316, /* Nvidia unknown FX Go */ 275 0x0317, /* Nvidia unknown FX Go */ 276 0x031a, /* Nvidia GeForce FX 5600 Go */ 277 0x031b, /* Nvidia GeForce FX 5650 Go */ 278 0x031c, /* Nvidia Quadro FX 700 Go */ 279 0x031d, /* Nvidia unknown FX Go */ 280 0x031e, /* Nvidia unknown FX Go */ 281 0x031f, /* Nvidia unknown FX Go */ 282 0x0320, /* Nvidia GeForce FX 5200 */ 283 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 284 0x0322, /* Nvidia GeForce FX 5200 */ 285 0x0323, /* Nvidia GeForce FX 5200LE */ 286 0x0324, /* Nvidia GeForce FX 5200 Go */ 287 0x0325, /* Nvidia GeForce FX 5250 Go */ 288 0x0326, /* Nvidia GeForce FX 5500 */ 289 0x0327, /* Nvidia GeForce FX 5100 */ 290 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 291 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 292 0x032a, /* Nvidia Quadro NVS 280 PCI */ 293 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 294 0x032c, /* Nvidia GeForce FX 5300 Go */ 295 0x032d, /* Nvidia GeForce FX 5100 Go */ 296 0x032e, /* Nvidia unknown FX Go */ 297 0x032f, /* Nvidia unknown FX Go */ 298 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 299 0x0331, /* Nvidia GeForce FX 5900 */ 300 0x0332, /* Nvidia GeForce FX 5900 XT */ 301 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 302 0x0334, /* Nvidia GeForce FX 5900 ZT */ 303 0x0338, /* Nvidia Quadro FX 3000 */ 304 0x033f, /* Nvidia Quadro FX 700 */ 305 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 306 0x0342, /* Nvidia GeForce FX 5700 */ 307 0x0343, /* Nvidia GeForce FX 5700LE */ 308 0x0344, /* Nvidia GeForce FX 5700VE */ 309 0x0345, /* Nvidia unknown FX */ 310 0x0347, /* Nvidia GeForce FX 5700 Go */ 311 0x0348, /* Nvidia GeForce FX 5700 Go */ 312 0x0349, /* Nvidia unknown FX Go */ 313 0x034b, /* Nvidia unknown FX Go */ 314 0x034c, /* Nvidia Quadro FX 1000 Go */ 315 0x034e, /* Nvidia Quadro FX 1100 */ 316 0x034f, /* Nvidia unknown FX */ 317 0x0391, /* Nvidia GeForce 7600 GT */ 318 0x0392, /* Nvidia GeForce 7600 GS */ 319 0x0393, /* Nvidia GeForce 7300 GT */ 320 0x0394, /* Nvidia GeForce 7600 LE */ 321 0x0398, /* Nvidia GeForce 7600 GO */ 322 0x03d0, /* Nvidia GeForce 6100 nForce 430 */ 323 0x03d1, /* Nvidia GeForce 6100 nForce 405 */ 324 0x03d2, /* Nvidia GeForce 6100 nForce 400 */ 325 0x0400, /* Nvidia GeForce 8600 GTS */ 326 0x0402, /* Nvidia GeForce 8600 GT */ 327 0x0421, /* Nvidia GeForce 8500 GT */ 328 0x0422, /* Nvidia GeForce 8400 GS */ 329 0x0423, /* Nvidia GeForce 8300 GS */ 330 0 331 }; 332 333 static uint16 elsa_device_list[] = { 334 0x0c60, /* Elsa Gladiac Geforce2 MX */ 335 0 336 }; 337 338 static uint16 nvstbsgs_device_list[] = { 339 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 340 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 341 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 342 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 343 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 344 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 345 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 346 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 347 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 348 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 349 0 350 }; 351 352 static uint16 varisys_device_list[] = { 353 0x3503, /* Varisys GeForce4 MX440 */ 354 0x3505, /* Varisys GeForce4 Ti 4200 */ 355 0 356 }; 357 358 static struct { 359 uint16 vendor; 360 uint16 *devices; 361 } SupportedDevices[] = { 362 {VENDOR_ID_NVIDIA, nvidia_device_list}, 363 {VENDOR_ID_ELSA, elsa_device_list}, 364 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 365 {VENDOR_ID_VARISYS, varisys_device_list}, 366 {0x0000, NULL} 367 }; 368 369 static nv_settings sSettings = { // see comments in nvidia.settings 370 /* for driver */ 371 DRIVER_PREFIX ".accelerant", 372 "none", // primary 373 false, // dumprom 374 /* for accelerant */ 375 0x00000000, // logmask 376 0, // memory 377 0, // tv_output 378 true, // usebios 379 true, // hardcursor 380 false, // switchhead 381 false, // force_pci 382 false, // unhide_fw 383 true, // pgm_panel 384 true, // dma_acc 385 false, // vga_on_tv 386 false, // force_sync 387 false, // force_ws 388 0, // gpu_clk 389 0, // ram_clk 390 }; 391 392 393 static void 394 dumprom(void *rom, uint32 size, pci_info pcii) 395 { 396 int fd; 397 uint32 cnt; 398 char fname[64]; 399 400 /* determine the romfile name: we need split-up per card in the system */ 401 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 402 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 403 404 fd = open (fname, O_WRONLY | O_CREAT, 0666); 405 if (fd < 0) return; 406 407 /* apparantly max. 32kb may be written at once; 408 * the ROM size is a multiple of that anyway. */ 409 for (cnt = 0; (cnt < size); cnt += 32768) 410 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 411 close (fd); 412 } 413 414 415 /*! return 1 if vblank interrupt has occured */ 416 static int 417 caused_vbi_crtc1(vuint32 * regs) 418 { 419 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 420 } 421 422 423 /*! clear the vblank interrupt */ 424 static void 425 clear_vbi_crtc1(vuint32 * regs) 426 { 427 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 428 } 429 430 431 static void 432 enable_vbi_crtc1(vuint32 * regs) 433 { 434 /* clear the vblank interrupt */ 435 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 436 /* enable nVidia interrupt source vblank */ 437 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 438 /* enable nVidia interrupt system hardware (b0-1) */ 439 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 440 } 441 442 443 static void 444 disable_vbi_crtc1(vuint32 * regs) 445 { 446 /* disable nVidia interrupt source vblank */ 447 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 448 /* clear the vblank interrupt */ 449 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 450 } 451 452 453 /*! return 1 if vblank interrupt has occured */ 454 static int 455 caused_vbi_crtc2(vuint32 * regs) 456 { 457 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 458 } 459 460 461 /*! clear the vblank interrupt */ 462 static void 463 clear_vbi_crtc2(vuint32 * regs) 464 { 465 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 466 } 467 468 469 static void 470 enable_vbi_crtc2(vuint32 * regs) 471 { 472 /* clear the vblank interrupt */ 473 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 474 /* enable nVidia interrupt source vblank */ 475 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 476 /* enable nVidia interrupt system hardware (b0-1) */ 477 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 478 } 479 480 481 static void 482 disable_vbi_crtc2(vuint32 * regs) 483 { 484 /* disable nVidia interrupt source vblank */ 485 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 486 /* clear the vblank interrupt */ 487 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 488 } 489 490 491 //fixme: 492 //dangerous code, on singlehead cards better not try accessing secondary head 493 //registers (card might react in unpredictable ways, though there's only a small 494 //chance we actually run into this). 495 //fix requires (some) card recognition code to be moved from accelerant to 496 //kerneldriver... 497 static void 498 disable_vbi_all(vuint32 * regs) 499 { 500 /* disable nVidia interrupt source vblank */ 501 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 502 /* clear the vblank interrupt */ 503 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 504 505 /* disable nVidia interrupt source vblank */ 506 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 507 /* clear the vblank interrupt */ 508 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 509 510 /* disable nVidia interrupt system hardware (b0-1) */ 511 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 512 } 513 514 515 static status_t 516 map_device(device_info *di) 517 { 518 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 519 shared_info *si = di->si; 520 uint32 tmpUlong, tmpROMshadow; 521 pci_info *pcii = &(di->pcii); 522 system_info sysinfo; 523 524 /* variables for making copy of ROM */ 525 uint8* rom_temp; 526 area_id rom_area = -1; 527 528 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 529 int registers = 0; 530 int frame_buffer = 1; 531 532 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 533 tmpUlong = get_pci(PCI_command, 2); 534 /* enable PCI access */ 535 tmpUlong |= PCI_command_memory; 536 /* enable busmastering */ 537 tmpUlong |= PCI_command_master; 538 /* disable ISA I/O access */ 539 tmpUlong &= ~PCI_command_io; 540 set_pci(PCI_command, 2, tmpUlong); 541 542 /*work out which version of BeOS is running*/ 543 get_system_info(&sysinfo); 544 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 545 { 546 si->use_clone_bugfix = 1; 547 } 548 else 549 { 550 si->use_clone_bugfix = 0; 551 } 552 553 /* work out a name for the register mapping */ 554 sprintf(buffer, DEVICE_FORMAT " regs", 555 di->pcii.vendor_id, di->pcii.device_id, 556 di->pcii.bus, di->pcii.device, di->pcii.function); 557 558 /* get a virtual memory address for the registers*/ 559 si->regs_area = map_physical_memory( 560 buffer, 561 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 562 (void *) di->pcii.u.h0.base_registers_pci[registers], 563 di->pcii.u.h0.base_register_sizes[registers], 564 B_ANY_KERNEL_ADDRESS, 565 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 566 (void **)&(di->regs)); 567 si->clone_bugfix_regs = (uint32 *) di->regs; 568 569 /* if mapping registers to vmem failed then pass on error */ 570 if (si->regs_area < 0) return si->regs_area; 571 572 /* work out a name for the ROM mapping*/ 573 sprintf(buffer, DEVICE_FORMAT " rom", 574 di->pcii.vendor_id, di->pcii.device_id, 575 di->pcii.bus, di->pcii.device, di->pcii.function); 576 577 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 578 /* warning: 579 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 580 * NV18, NV28 and NV34 keep working. 581 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 582 * however the actual ROM content (so the used part) is intact (confirmed). */ 583 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 584 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 585 set_pci(NVCFG_ROMSHADOW, 4, 0); 586 587 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 588 tmpUlong = get_pci(PCI_rom_base, 4); 589 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 590 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 591 //legacy space will get us into trouble if we aren't the primary graphics card!! 592 //(as legacy space always has the primary card's ROM 'mapped'!) 593 if (tmpUlong) { 594 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 595 tmpUlong |= 0x00000001; 596 set_pci(PCI_rom_base, 4, tmpUlong); 597 598 rom_area = map_physical_memory( 599 buffer, 600 (void *)di->pcii.u.h0.rom_base_pci, 601 di->pcii.u.h0.rom_size, 602 B_ANY_KERNEL_ADDRESS, 603 B_READ_AREA, 604 (void **)&(rom_temp) 605 ); 606 607 /* check if we got the BIOS and signature (might fail on laptops..) */ 608 if (rom_area >= 0) { 609 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 610 /* apparantly no ROM is mapped here */ 611 delete_area(rom_area); 612 rom_area = -1; 613 /* force using ISA legacy map as fall-back */ 614 tmpUlong = 0x00000000; 615 } 616 } else { 617 /* mapping failed: force using ISA legacy map as fall-back */ 618 tmpUlong = 0x00000000; 619 } 620 } 621 622 if (!tmpUlong) { 623 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 624 rom_area = map_physical_memory(buffer, (void *)0x000c0000, 625 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 626 } 627 628 /* if mapping ROM to vmem failed then clean up and pass on error */ 629 if (rom_area < 0) { 630 delete_area(si->regs_area); 631 si->regs_area = -1; 632 return rom_area; 633 } 634 635 /* dump ROM to file if selected in nvidia.settings 636 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 637 if (sSettings.dumprom) 638 dumprom(rom_temp, 65536, di->pcii); 639 640 /* make a copy of ROM for future reference */ 641 memcpy(si->rom_mirror, rom_temp, 65536); 642 643 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 644 tmpUlong = get_pci(PCI_rom_base, 4); 645 tmpUlong &= 0xfffffffe; 646 set_pci(PCI_rom_base, 4, tmpUlong); 647 delete_area(rom_area); 648 649 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 650 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 651 652 /* work out a name for the framebuffer mapping*/ 653 sprintf(buffer, DEVICE_FORMAT " framebuffer", 654 di->pcii.vendor_id, di->pcii.device_id, 655 di->pcii.bus, di->pcii.device, di->pcii.function); 656 657 /* map the framebuffer into vmem, using Write Combining*/ 658 si->fb_area = map_physical_memory(buffer, 659 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 660 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 661 di->pcii.u.h0.base_register_sizes[frame_buffer], 662 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 663 B_READ_AREA | B_WRITE_AREA, 664 &(si->framebuffer)); 665 666 /*if failed with write combining try again without*/ 667 if (si->fb_area < 0) { 668 si->fb_area = map_physical_memory(buffer, 669 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 670 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 671 di->pcii.u.h0.base_register_sizes[frame_buffer], 672 B_ANY_KERNEL_BLOCK_ADDRESS, 673 B_READ_AREA | B_WRITE_AREA, 674 &(si->framebuffer)); 675 } 676 677 /* if there was an error, delete our other areas and pass on error*/ 678 if (si->fb_area < 0) { 679 delete_area(si->regs_area); 680 si->regs_area = -1; 681 return si->fb_area; 682 } 683 684 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 685 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 686 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 687 688 // remember settings for use here and in accelerant 689 si->settings = sSettings; 690 691 /* in any case, return the result */ 692 return si->fb_area; 693 } 694 695 696 static void 697 unmap_device(device_info *di) 698 { 699 shared_info *si = di->si; 700 uint32 tmpUlong; 701 pci_info *pcii = &(di->pcii); 702 703 /* disable memory mapped IO */ 704 tmpUlong = get_pci(PCI_command, 4); 705 tmpUlong &= 0xfffffffc; 706 set_pci(PCI_command, 4, tmpUlong); 707 /* delete the areas */ 708 if (si->regs_area >= 0) 709 delete_area(si->regs_area); 710 if (si->fb_area >= 0) 711 delete_area(si->fb_area); 712 si->regs_area = si->fb_area = -1; 713 si->framebuffer = NULL; 714 di->regs = NULL; 715 } 716 717 718 static void 719 probe_devices(void) 720 { 721 uint32 pci_index = 0; 722 uint32 count = 0; 723 device_info *di = pd->di; 724 char tmp_name[B_OS_NAME_LENGTH]; 725 726 /* while there are more pci devices */ 727 while (count < MAX_DEVICES 728 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 729 int vendor = 0; 730 731 /* if we match a supported vendor */ 732 while (SupportedDevices[vendor].vendor) { 733 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 734 uint16 *devices = SupportedDevices[vendor].devices; 735 /* while there are more supported devices */ 736 while (*devices) { 737 /* if we match a supported device */ 738 if (*devices == di->pcii.device_id ) { 739 /* publish the device name */ 740 sprintf(tmp_name, DEVICE_FORMAT, 741 di->pcii.vendor_id, di->pcii.device_id, 742 di->pcii.bus, di->pcii.device, di->pcii.function); 743 /* tweak the exported name to show first in the alphabetically ordered /dev/ 744 * hierarchy folder, so the system will use it as primary adaptor if requested 745 * via nvidia.settings. */ 746 if (strcmp(tmp_name, sSettings.primary) == 0) 747 sprintf(tmp_name, "-%s", sSettings.primary); 748 /* add /dev/ hierarchy path */ 749 sprintf(di->name, "graphics/%s", tmp_name); 750 /* remember the name */ 751 pd->device_names[count] = di->name; 752 /* mark the driver as available for R/W open */ 753 di->is_open = 0; 754 /* mark areas as not yet created */ 755 di->shared_area = -1; 756 /* mark pointer to shared data as invalid */ 757 di->si = NULL; 758 /* inc pointer to device info */ 759 di++; 760 /* inc count */ 761 count++; 762 /* break out of these while loops */ 763 goto next_device; 764 } 765 /* next supported device */ 766 devices++; 767 } 768 } 769 vendor++; 770 } 771 next_device: 772 /* next pci_info struct, please */ 773 pci_index++; 774 } 775 /* propagate count */ 776 pd->count = count; 777 /* terminate list of device names with a null pointer */ 778 pd->device_names[pd->count] = NULL; 779 } 780 781 782 static uint32 783 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 784 { 785 uint32 handled = B_HANDLED_INTERRUPT; 786 /* release the vblank semaphore */ 787 if (si->vblank >= 0) { 788 int32 blocked; 789 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 790 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 791 handled = B_INVOKE_SCHEDULER; 792 } 793 } 794 return handled; 795 } 796 797 798 static int32 799 nv_interrupt(void *data) 800 { 801 int32 handled = B_UNHANDLED_INTERRUPT; 802 device_info *di = (device_info *)data; 803 shared_info *si = di->si; 804 int32 *flags = &(si->flags); 805 vuint32 *regs; 806 807 /* is someone already handling an interrupt for this device? */ 808 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 809 810 /* get regs */ 811 regs = di->regs; 812 813 /* was it a VBI? */ 814 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 815 if (si->ps.secondary_head) { 816 //fixme: 817 //rewrite once we use one driver instance 'per head' (instead of 'per card') 818 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 819 /* clear the interrupt(s) */ 820 clear_vbi_crtc1(regs); 821 clear_vbi_crtc2(regs); 822 /* release the semaphore */ 823 handled = thread_interrupt_work(flags, regs, si); 824 } 825 } else { 826 if (caused_vbi_crtc1(regs)) { 827 /* clear the interrupt */ 828 clear_vbi_crtc1(regs); 829 /* release the semaphore */ 830 handled = thread_interrupt_work(flags, regs, si); 831 } 832 } 833 834 /* note that we're not in the handler any more */ 835 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 836 837 exit0: 838 return handled; 839 } 840 841 842 // #pragma mark - device hooks 843 844 845 static status_t 846 open_hook(const char* name, uint32 flags, void** cookie) 847 { 848 int32 index = 0; 849 device_info *di; 850 shared_info *si; 851 thread_id thid; 852 thread_info thinfo; 853 status_t result = B_OK; 854 char shared_name[B_OS_NAME_LENGTH]; 855 physical_entry map[1]; 856 size_t net_buf_size; 857 void *unaligned_dma_buffer; 858 859 /* find the device name in the list of devices */ 860 /* we're never passed a name we didn't publish */ 861 while (pd->device_names[index] 862 && (strcmp(name, pd->device_names[index]) != 0)) 863 index++; 864 865 /* for convienience */ 866 di = &(pd->di[index]); 867 868 /* make sure no one else has write access to the common data */ 869 AQUIRE_BEN(pd->kernel); 870 871 /* if it's already open for writing */ 872 if (di->is_open) { 873 /* mark it open another time */ 874 goto mark_as_open; 875 } 876 /* create the shared_info area */ 877 sprintf(shared_name, DEVICE_FORMAT " shared", 878 di->pcii.vendor_id, di->pcii.device_id, 879 di->pcii.bus, di->pcii.device, di->pcii.function); 880 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 881 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 882 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 883 B_USER_CLONEABLE_AREA); 884 if (di->shared_area < 0) { 885 /* return the error */ 886 result = di->shared_area; 887 goto done; 888 } 889 890 /* save a few dereferences */ 891 si = di->si; 892 893 /* create the DMA command buffer area */ 894 //fixme? for R4.5 a workaround for cloning would be needed! 895 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 896 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 897 /* create the area that will hold the DMA command buffer */ 898 si->unaligned_dma_area = 899 create_area("NV DMA cmd buffer", 900 (void **)&unaligned_dma_buffer, 901 B_ANY_KERNEL_ADDRESS, 902 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 903 B_FULL_LOCK | B_CONTIGUOUS, /* both properties needed: GPU always needs access */ 904 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 905 /* on error, abort */ 906 if (si->unaligned_dma_area < 0) 907 { 908 /* free the already created shared_info area, and return the error */ 909 result = si->unaligned_dma_area; 910 goto free_shared; 911 } 912 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 913 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 914 * even on older CPU's. */ 915 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 916 si->dma_buffer_pci = (void*) 917 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 918 919 /* map the net DMA command buffer into vmem, using Write Combining */ 920 si->dma_area = map_physical_memory( 921 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 922 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 923 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 924 /* if failed with write combining try again without */ 925 if (si->dma_area < 0) { 926 si->dma_area = map_physical_memory( 927 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 928 B_ANY_KERNEL_BLOCK_ADDRESS, 929 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 930 } 931 /* if there was an error, delete our other areas and pass on error*/ 932 if (si->dma_area < 0) 933 { 934 /* free the already created areas, and return the error */ 935 result = si->dma_area; 936 goto free_shared_and_uadma; 937 } 938 939 /* save the vendor and device IDs */ 940 si->vendor_id = di->pcii.vendor_id; 941 si->device_id = di->pcii.device_id; 942 si->revision = di->pcii.revision; 943 si->bus = di->pcii.bus; 944 si->device = di->pcii.device; 945 si->function = di->pcii.function; 946 947 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 948 si->accelerant_in_use = false; 949 /* preset singlehead card to prevent early INT routine calls (once installed) to 950 * wrongly identify the INT request coming from us! */ 951 si->ps.secondary_head = false; 952 953 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 954 * unified memory architecture (UMA) */ 955 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 956 { 957 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 958 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 959 si->ps.memory_size = 1024 * 1024 * 960 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 961 /* last 64kB RAM is used for the BIOS (or something else?) */ 962 si->ps.memory_size -= (64 * 1024); 963 break; 964 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 965 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 966 si->ps.memory_size = 1024 * 1024 * 967 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 968 /* last 64kB RAM is used for the BIOS (or something else?) */ 969 si->ps.memory_size -= (64 * 1024); 970 break; 971 default: 972 /* all other cards have own RAM: the amount of which is determined in the 973 * accelerant. */ 974 break; 975 } 976 977 /* map the device */ 978 result = map_device(di); 979 if (result < 0) goto free_shared_and_alldma; 980 981 /* we will be returning OK status for sure now */ 982 result = B_OK; 983 984 /* disable and clear any pending interrupts */ 985 //fixme: 986 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 987 disable_vbi_all(di->regs); 988 989 /* preset we can't use INT related functions */ 990 si->ps.int_assigned = false; 991 992 /* create a semaphore for vertical blank management */ 993 si->vblank = create_sem(0, di->name); 994 if (si->vblank < 0) goto mark_as_open; 995 996 /* change the owner of the semaphores to the opener's team */ 997 /* this is required because apps can't aquire kernel semaphores */ 998 thid = find_thread(NULL); 999 get_thread_info(thid, &thinfo); 1000 set_sem_owner(si->vblank, thinfo.team); 1001 1002 /* If there is a valid interrupt line assigned then set up interrupts */ 1003 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1004 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1005 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1006 { 1007 /* delete the semaphore as it won't be used */ 1008 delete_sem(si->vblank); 1009 si->vblank = -1; 1010 } 1011 else 1012 { 1013 /* otherwise install our interrupt handler */ 1014 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1015 /* bail if we couldn't install the handler */ 1016 if (result != B_OK) 1017 { 1018 /* delete the semaphore as it won't be used */ 1019 delete_sem(si->vblank); 1020 si->vblank = -1; 1021 } 1022 else 1023 { 1024 /* inform accelerant(s) we can use INT related functions */ 1025 si->ps.int_assigned = true; 1026 } 1027 } 1028 1029 mark_as_open: 1030 /* mark the device open */ 1031 di->is_open++; 1032 1033 /* send the cookie to the opener */ 1034 *cookie = di; 1035 1036 goto done; 1037 1038 1039 free_shared_and_alldma: 1040 /* clean up our aligned DMA area */ 1041 delete_area(si->dma_area); 1042 si->dma_area = -1; 1043 si->dma_buffer = NULL; 1044 1045 free_shared_and_uadma: 1046 /* clean up our unaligned DMA area */ 1047 delete_area(si->unaligned_dma_area); 1048 si->unaligned_dma_area = -1; 1049 si->dma_buffer_pci = NULL; 1050 1051 free_shared: 1052 /* clean up our shared area */ 1053 delete_area(di->shared_area); 1054 di->shared_area = -1; 1055 di->si = NULL; 1056 1057 done: 1058 /* end of critical section */ 1059 RELEASE_BEN(pd->kernel); 1060 1061 /* all done, return the status */ 1062 return result; 1063 } 1064 1065 1066 static status_t 1067 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1068 { 1069 *len = 0; 1070 return B_NOT_ALLOWED; 1071 } 1072 1073 1074 static status_t 1075 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1076 { 1077 *len = 0; 1078 return B_NOT_ALLOWED; 1079 } 1080 1081 1082 static status_t 1083 close_hook(void* dev) 1084 { 1085 /* we don't do anything on close: there might be dup'd fd */ 1086 return B_NO_ERROR; 1087 } 1088 1089 1090 static status_t 1091 free_hook(void* dev) 1092 { 1093 device_info *di = (device_info *)dev; 1094 shared_info *si = di->si; 1095 vuint32 *regs = di->regs; 1096 1097 /* lock the driver */ 1098 AQUIRE_BEN(pd->kernel); 1099 1100 /* if opened multiple times, decrement the open count and exit */ 1101 if (di->is_open > 1) 1102 goto unlock_and_exit; 1103 1104 /* disable and clear any pending interrupts */ 1105 //fixme: 1106 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1107 disable_vbi_all(regs); 1108 1109 if (si->ps.int_assigned) { 1110 /* remove interrupt handler */ 1111 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1112 1113 /* delete the semaphores, ignoring any errors ('cause the owning 1114 team may have died on us) */ 1115 delete_sem(si->vblank); 1116 si->vblank = -1; 1117 } 1118 1119 /* free regs and framebuffer areas */ 1120 unmap_device(di); 1121 1122 /* clean up our aligned DMA area */ 1123 delete_area(si->dma_area); 1124 si->dma_area = -1; 1125 si->dma_buffer = NULL; 1126 1127 /* clean up our unaligned DMA area */ 1128 delete_area(si->unaligned_dma_area); 1129 si->unaligned_dma_area = -1; 1130 si->dma_buffer_pci = NULL; 1131 1132 /* clean up our shared area */ 1133 delete_area(di->shared_area); 1134 di->shared_area = -1; 1135 di->si = NULL; 1136 1137 unlock_and_exit: 1138 /* mark the device available */ 1139 di->is_open--; 1140 /* unlock the driver */ 1141 RELEASE_BEN(pd->kernel); 1142 /* all done */ 1143 return B_OK; 1144 } 1145 1146 1147 static status_t 1148 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1149 { 1150 device_info *di = (device_info *)dev; 1151 status_t result = B_DEV_INVALID_IOCTL; 1152 uint32 tmpUlong; 1153 1154 switch (msg) { 1155 /* the only PUBLIC ioctl */ 1156 case B_GET_ACCELERANT_SIGNATURE: 1157 { 1158 strcpy((char* )buf, sSettings.accelerant); 1159 result = B_OK; 1160 break; 1161 } 1162 1163 /* PRIVATE ioctl from here on */ 1164 case NV_GET_PRIVATE_DATA: 1165 { 1166 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1167 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1168 gpd->shared_info_area = di->shared_area; 1169 result = B_OK; 1170 } 1171 break; 1172 } 1173 1174 case NV_GET_PCI: 1175 { 1176 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1177 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1178 pci_info *pcii = &(di->pcii); 1179 gsp->value = get_pci(gsp->offset, gsp->size); 1180 result = B_OK; 1181 } 1182 break; 1183 } 1184 1185 case NV_SET_PCI: 1186 { 1187 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1188 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1189 pci_info *pcii = &(di->pcii); 1190 set_pci(gsp->offset, gsp->size, gsp->value); 1191 result = B_OK; 1192 } 1193 break; 1194 } 1195 1196 case NV_DEVICE_NAME: 1197 { 1198 nv_device_name *dn = (nv_device_name *)buf; 1199 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1200 strcpy(dn->name, di->name); 1201 result = B_OK; 1202 } 1203 break; 1204 } 1205 1206 case NV_RUN_INTERRUPTS: 1207 { 1208 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1209 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1210 vuint32 *regs = di->regs; 1211 if (!(vi->crtc)) { 1212 if (vi->do_it) { 1213 enable_vbi_crtc1(regs); 1214 } else { 1215 disable_vbi_crtc1(regs); 1216 } 1217 } else { 1218 if (vi->do_it) { 1219 enable_vbi_crtc2(regs); 1220 } else { 1221 disable_vbi_crtc2(regs); 1222 } 1223 } 1224 result = B_OK; 1225 } 1226 break; 1227 } 1228 1229 case NV_GET_NTH_AGP_INFO: 1230 { 1231 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1232 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1233 nai->exist = false; 1234 nai->agp_bus = false; 1235 if (agp_bus) { 1236 nai->agp_bus = true; 1237 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1238 nai->exist = true; 1239 } 1240 } 1241 result = B_OK; 1242 } 1243 break; 1244 } 1245 1246 case NV_ENABLE_AGP: 1247 { 1248 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1249 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1250 if (agp_bus) { 1251 nca->agp_bus = true; 1252 (*agp_bus->enable_agp)(&(nca->cmd)); 1253 } else { 1254 nca->agp_bus = false; 1255 nca->cmd = 0; 1256 } 1257 result = B_OK; 1258 } 1259 break; 1260 } 1261 1262 case NV_ISA_OUT: 1263 { 1264 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1265 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1266 pci_info *pcii = &(di->pcii); 1267 1268 /* lock the driver: 1269 * no other graphics card may have ISA I/O enabled when we enter */ 1270 AQUIRE_BEN(pd->kernel); 1271 1272 /* enable ISA I/O access */ 1273 tmpUlong = get_pci(PCI_command, 2); 1274 tmpUlong |= PCI_command_io; 1275 set_pci(PCI_command, 2, tmpUlong); 1276 1277 if (io_isa->size == 1) 1278 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1279 else 1280 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1281 result = B_OK; 1282 1283 /* disable ISA I/O access */ 1284 tmpUlong = get_pci(PCI_command, 2); 1285 tmpUlong &= ~PCI_command_io; 1286 set_pci(PCI_command, 2, tmpUlong); 1287 1288 /* end of critical section */ 1289 RELEASE_BEN(pd->kernel); 1290 } 1291 break; 1292 } 1293 1294 case NV_ISA_IN: 1295 { 1296 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1297 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1298 pci_info *pcii = &(di->pcii); 1299 1300 /* lock the driver: 1301 * no other graphics card may have ISA I/O enabled when we enter */ 1302 AQUIRE_BEN(pd->kernel); 1303 1304 /* enable ISA I/O access */ 1305 tmpUlong = get_pci(PCI_command, 2); 1306 tmpUlong |= PCI_command_io; 1307 set_pci(PCI_command, 2, tmpUlong); 1308 1309 if (io_isa->size == 1) 1310 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1311 else 1312 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1313 result = B_OK; 1314 1315 /* disable ISA I/O access */ 1316 tmpUlong = get_pci(PCI_command, 2); 1317 tmpUlong &= ~PCI_command_io; 1318 set_pci(PCI_command, 2, tmpUlong); 1319 1320 /* end of critical section */ 1321 RELEASE_BEN(pd->kernel); 1322 } 1323 break; 1324 } 1325 } 1326 1327 return result; 1328 } 1329 1330 1331 // #pragma mark - driver API 1332 1333 1334 status_t 1335 init_hardware(void) 1336 { 1337 long index = 0; 1338 pci_info pcii; 1339 bool found = false; 1340 1341 /* choke if we can't find the PCI bus */ 1342 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1343 return B_ERROR; 1344 1345 /* choke if we can't find the ISA bus */ 1346 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1347 { 1348 put_module(B_PCI_MODULE_NAME); 1349 return B_ERROR; 1350 } 1351 1352 /* while there are more pci devices */ 1353 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1354 int vendor = 0; 1355 1356 /* if we match a supported vendor */ 1357 while (SupportedDevices[vendor].vendor) { 1358 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1359 uint16 *devices = SupportedDevices[vendor].devices; 1360 /* while there are more supported devices */ 1361 while (*devices) { 1362 /* if we match a supported device */ 1363 if (*devices == pcii.device_id ) { 1364 1365 found = true; 1366 goto done; 1367 } 1368 /* next supported device */ 1369 devices++; 1370 } 1371 } 1372 vendor++; 1373 } 1374 /* next pci_info struct, please */ 1375 index++; 1376 } 1377 1378 done: 1379 /* put away the module manager */ 1380 put_module(B_PCI_MODULE_NAME); 1381 return found ? B_OK : B_ERROR; 1382 } 1383 1384 1385 status_t 1386 init_driver(void) 1387 { 1388 void *settings; 1389 1390 // get driver/accelerant settings 1391 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1392 if (settings != NULL) { 1393 const char *item; 1394 char *end; 1395 uint32 value; 1396 1397 // for driver 1398 item = get_driver_parameter(settings, "accelerant", "", ""); 1399 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1400 strcpy (sSettings.accelerant, item); 1401 1402 item = get_driver_parameter(settings, "primary", "", ""); 1403 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1404 strcpy(sSettings.primary, item); 1405 1406 sSettings.dumprom = get_driver_boolean_parameter(settings, 1407 "dumprom", false, false); 1408 1409 // for accelerant 1410 item = get_driver_parameter(settings, "logmask", 1411 "0x00000000", "0x00000000"); 1412 value = strtoul(item, &end, 0); 1413 if (*end == '\0') 1414 sSettings.logmask = value; 1415 1416 item = get_driver_parameter(settings, "memory", "0", "0"); 1417 value = strtoul(item, &end, 0); 1418 if (*end == '\0') 1419 sSettings.memory = value; 1420 1421 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1422 value = strtoul(item, &end, 0); 1423 if (*end == '\0') 1424 sSettings.tv_output = value; 1425 1426 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1427 "hardcursor", false, false); 1428 sSettings.usebios = get_driver_boolean_parameter(settings, 1429 "usebios", false, false); 1430 sSettings.switchhead = get_driver_boolean_parameter(settings, 1431 "switchhead", false, false); 1432 sSettings.force_pci = get_driver_boolean_parameter(settings, 1433 "force_pci", false, false); 1434 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1435 "unhide_fw", false, false); 1436 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1437 "pgm_panel", false, false); 1438 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1439 "dma_acc", false, false); 1440 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1441 "vga_on_tv", false, false); 1442 sSettings.force_sync = get_driver_boolean_parameter(settings, 1443 "force_sync", false, false); 1444 sSettings.force_ws = get_driver_boolean_parameter(settings, 1445 "force_ws", false, false); 1446 1447 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1448 value = strtoul(item, &end, 0); 1449 if (*end == '\0') 1450 sSettings.gpu_clk = value; 1451 1452 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1453 value = strtoul(item, &end, 0); 1454 if (*end == '\0') 1455 sSettings.ram_clk = value; 1456 1457 unload_driver_settings(settings); 1458 } 1459 1460 /* get a handle for the pci bus */ 1461 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1462 return B_ERROR; 1463 1464 /* get a handle for the isa bus */ 1465 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1466 put_module(B_PCI_MODULE_NAME); 1467 return B_ERROR; 1468 } 1469 1470 /* get a handle for the agp bus if it exists */ 1471 get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus); 1472 1473 /* driver private data */ 1474 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1475 if (!pd) { 1476 put_module(B_PCI_MODULE_NAME); 1477 return B_ERROR; 1478 } 1479 /* initialize the benaphore */ 1480 INIT_BEN(pd->kernel); 1481 /* find all of our supported devices */ 1482 probe_devices(); 1483 return B_OK; 1484 } 1485 1486 1487 const char ** 1488 publish_devices(void) 1489 { 1490 /* return the list of supported devices */ 1491 return (const char **)pd->device_names; 1492 } 1493 1494 1495 device_hooks * 1496 find_device(const char *name) 1497 { 1498 int index = 0; 1499 while (pd->device_names[index]) { 1500 if (strcmp(name, pd->device_names[index]) == 0) 1501 return &graphics_device_hooks; 1502 index++; 1503 } 1504 return NULL; 1505 1506 } 1507 1508 1509 void 1510 uninit_driver(void) 1511 { 1512 /* free the driver data */ 1513 DELETE_BEN(pd->kernel); 1514 free(pd); 1515 pd = NULL; 1516 1517 /* put the pci module away */ 1518 put_module(B_PCI_MODULE_NAME); 1519 put_module(B_ISA_MODULE_NAME); 1520 1521 /* put the agp module away if it's there */ 1522 if (agp_bus) 1523 put_module(B_AGP_MODULE_NAME); 1524 } 1525 1526