1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-10/2007. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_gart_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 109 0x0041, /* Nvidia GeForce FX 6800 */ 110 0x0042, /* Nvidia GeForce FX 6800LE */ 111 0x0043, /* Nvidia GeForce 6800 XE */ 112 0x0045, /* Nvidia GeForce FX 6800 GT */ 113 0x0046, /* Nvidia GeForce FX 6800 GT */ 114 0x0047, /* Nvidia GeForce 6800 GS */ 115 0x0048, /* Nvidia GeForce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia GeForce 6800 GS */ 126 0x00c1, /* Nvidia GeForce FX 6800 */ 127 0x00c2, /* Nvidia GeForce FX 6800LE */ 128 0x00c3, /* Nvidia GeForce FX 6800 XT */ 129 0x00c8, /* Nvidia GeForce FX 6800 Go */ 130 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 137 0x00f3, /* Nvidia GeForce 6200 */ 138 0x00f4, /* Nvidia GeForce 6600 LE */ 139 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia GeForce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 149 0x0100, /* Nvidia GeForce256 SDR */ 150 0x0101, /* Nvidia GeForce256 DDR */ 151 0x0102, /* Nvidia GeForce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia GeForce2 MX/MX400 */ 154 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia GeForce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia GeForce FX 6600 GT */ 158 #if 0 159 // TODO: investigate! Other cards might be affected, see tickets #1530 160 // and #1712. 161 0x0141, /* Nvidia GeForce FX 6600 */ 162 #endif 163 0x0142, /* Nvidia GeForce FX 6600LE */ 164 0x0143, /* Nvidia GeForce 6600 VE */ 165 0x0144, /* Nvidia GeForce FX 6600 Go */ 166 0x0145, /* Nvidia GeForce FX 6610 XL */ 167 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 168 0x0147, /* Nvidia GeForce FX 6700 XL */ 169 0x0148, /* Nvidia GeForce FX 6600 Go */ 170 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 171 0x014b, /* Nvidia unknown FX */ 172 0x014c, /* Nvidia Quadro FX 540 MXM */ 173 0x014d, /* Nvidia unknown FX */ 174 0x014e, /* Nvidia Quadro FX 540 */ 175 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 176 0x0150, /* Nvidia GeForce2 GTS/Pro */ 177 0x0151, /* Nvidia GeForce2 Ti DDR */ 178 0x0152, /* Nvidia GeForce2 Ultra */ 179 0x0153, /* Nvidia Quadro2 Pro */ 180 0x0160, /* Nvidia GeForce 6500 Go */ 181 0x0161, /* Nvidia GeForce 6200 TurboCache */ 182 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 183 0x0163, /* Nvidia GeForce 6200LE */ 184 0x0164, /* Nvidia GeForce FX 6200 Go */ 185 0x0165, /* Nvidia Quadro FX NVS 285 */ 186 0x0166, /* Nvidia GeForce 6400 Go */ 187 0x0167, /* Nvidia GeForce 6200 Go */ 188 0x0168, /* Nvidia GeForce 6400 Go */ 189 0x0169, /* Nvidia GeForce 6250 Go */ 190 0x016a, /* Nvidia Geforce 7100 GS */ 191 0x016b, /* Nvidia unknown FX Go */ 192 0x016c, /* Nvidia unknown FX Go */ 193 0x016d, /* Nvidia unknown FX Go */ 194 0x016e, /* Nvidia unknown FX */ 195 0x0170, /* Nvidia GeForce4 MX 460 */ 196 0x0171, /* Nvidia GeForce4 MX 440 */ 197 0x0172, /* Nvidia GeForce4 MX 420 */ 198 0x0173, /* Nvidia GeForce4 MX 440SE */ 199 0x0174, /* Nvidia GeForce4 440 Go */ 200 0x0175, /* Nvidia GeForce4 420 Go */ 201 0x0176, /* Nvidia GeForce4 420 Go 32M */ 202 0x0177, /* Nvidia GeForce4 460 Go */ 203 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 204 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 205 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 206 0x017c, /* Nvidia Quadro4 500 GoGL */ 207 0x017d, /* Nvidia GeForce4 410 Go 16M */ 208 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 209 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 210 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 211 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 212 0x0186, /* Nvidia GeForce4 448 Go */ 213 0x0187, /* Nvidia GeForce4 488 Go */ 214 0x0188, /* Nvidia Quadro4 580 XGL */ 215 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 216 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 217 0x018b, /* Nvidia Quadro4 380 XGL */ 218 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 219 0x018d, /* Nvidia GeForce4 448 Go */ 220 0x0191, /* Nvidia GeForce 8800 GTX */ 221 0x0193, /* Nvidia GeForce 8800 GTS */ 222 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 223 0x01d1, /* Nvidia GeForce 7300 LE */ 224 0x01d3, /* Nvidia GeForce 7300 SE */ 225 0x01d8, /* Nvidia GeForce 7400 GO */ 226 0x01dd, /* Nvidia GeForce 7500 LE */ 227 0x01df, /* Nvidia GeForce 7300 GS */ 228 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 229 0x0200, /* Nvidia GeForce3 */ 230 0x0201, /* Nvidia GeForce3 Ti 200 */ 231 0x0202, /* Nvidia GeForce3 Ti 500 */ 232 0x0203, /* Nvidia Quadro DCC */ 233 0x0211, /* Nvidia GeForce FX 6800 */ 234 0x0212, /* Nvidia GeForce FX 6800LE */ 235 0x0215, /* Nvidia GeForce FX 6800 GT */ 236 0x0218, /* Nvidia GeForce 6800 XT */ 237 0x0220, /* Nvidia unknown FX */ 238 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 239 0x0222, /* Nvidia unknown FX */ 240 0x0228, /* Nvidia unknown FX Go */ 241 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 242 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 243 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 244 0x0245, /* Nvidia Quadro NVS 210S / GeForce 6150LE */ 245 0x0250, /* Nvidia GeForce4 Ti 4600 */ 246 0x0251, /* Nvidia GeForce4 Ti 4400 */ 247 0x0252, /* Nvidia GeForce4 Ti 4600 */ 248 0x0253, /* Nvidia GeForce4 Ti 4200 */ 249 0x0258, /* Nvidia Quadro4 900 XGL */ 250 0x0259, /* Nvidia Quadro4 750 XGL */ 251 0x025b, /* Nvidia Quadro4 700 XGL */ 252 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 253 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 254 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 255 0x0286, /* Nvidia GeForce4 4200 Go */ 256 0x0288, /* Nvidia Quadro4 980 XGL */ 257 0x0289, /* Nvidia Quadro4 780 XGL */ 258 0x028c, /* Nvidia Quadro4 700 GoGL */ 259 0x0290, /* Nvidia GeForce 7900 GTX */ 260 0x0291, /* Nvidia GeForce 7900 GT */ 261 0x0293, /* Nvidia GeForce 7900 GX2 */ 262 0x0294, /* Nvidia GeForce 7950 GX2 */ 263 0x0295, /* Nvidia GeForce 7950 GT */ 264 0x0298, /* Nvidia GeForce Go 7900 GS */ 265 0x0299, /* Nvidia GeForce Go 7900 GTX */ 266 0x029c, /* Nvidia Quadro FX 5500 */ 267 0x029f, /* Nvidia Quadro FX 4500 X2 */ 268 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 269 0x02e1, /* Nvidia GeForce 7600 GS */ 270 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 271 0x0302, /* Nvidia GeForce FX 5800 */ 272 0x0308, /* Nvidia Quadro FX 2000 */ 273 0x0309, /* Nvidia Quadro FX 1000 */ 274 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 275 0x0312, /* Nvidia GeForce FX 5600 */ 276 0x0313, /* Nvidia unknown FX */ 277 0x0314, /* Nvidia GeForce FX 5600XT */ 278 0x0316, /* Nvidia unknown FX Go */ 279 0x0317, /* Nvidia unknown FX Go */ 280 0x031a, /* Nvidia GeForce FX 5600 Go */ 281 0x031b, /* Nvidia GeForce FX 5650 Go */ 282 0x031c, /* Nvidia Quadro FX 700 Go */ 283 0x031d, /* Nvidia unknown FX Go */ 284 0x031e, /* Nvidia unknown FX Go */ 285 0x031f, /* Nvidia unknown FX Go */ 286 0x0320, /* Nvidia GeForce FX 5200 */ 287 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 288 0x0322, /* Nvidia GeForce FX 5200 */ 289 0x0323, /* Nvidia GeForce FX 5200LE */ 290 0x0324, /* Nvidia GeForce FX 5200 Go */ 291 0x0325, /* Nvidia GeForce FX 5250 Go */ 292 0x0326, /* Nvidia GeForce FX 5500 */ 293 0x0327, /* Nvidia GeForce FX 5100 */ 294 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 295 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 296 0x032a, /* Nvidia Quadro NVS 280 PCI */ 297 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 298 0x032c, /* Nvidia GeForce FX 5300 Go */ 299 0x032d, /* Nvidia GeForce FX 5100 Go */ 300 0x032e, /* Nvidia unknown FX Go */ 301 0x032f, /* Nvidia unknown FX Go */ 302 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 303 0x0331, /* Nvidia GeForce FX 5900 */ 304 0x0332, /* Nvidia GeForce FX 5900 XT */ 305 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 306 0x0334, /* Nvidia GeForce FX 5900 ZT */ 307 0x0338, /* Nvidia Quadro FX 3000 */ 308 0x033f, /* Nvidia Quadro FX 700 */ 309 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 310 0x0342, /* Nvidia GeForce FX 5700 */ 311 0x0343, /* Nvidia GeForce FX 5700LE */ 312 0x0344, /* Nvidia GeForce FX 5700VE */ 313 0x0345, /* Nvidia unknown FX */ 314 0x0347, /* Nvidia GeForce FX 5700 Go */ 315 0x0348, /* Nvidia GeForce FX 5700 Go */ 316 0x0349, /* Nvidia unknown FX Go */ 317 0x034b, /* Nvidia unknown FX Go */ 318 0x034c, /* Nvidia Quadro FX 1000 Go */ 319 0x034e, /* Nvidia Quadro FX 1100 */ 320 0x034f, /* Nvidia unknown FX */ 321 0x0391, /* Nvidia GeForce 7600 GT */ 322 0x0392, /* Nvidia GeForce 7600 GS */ 323 0x0393, /* Nvidia GeForce 7300 GT */ 324 0x0394, /* Nvidia GeForce 7600 LE */ 325 0x0398, /* Nvidia GeForce 7600 GO */ 326 0x03d0, /* Nvidia GeForce 6100 nForce 430 */ 327 0x03d1, /* Nvidia GeForce 6100 nForce 405 */ 328 0x03d2, /* Nvidia GeForce 6100 nForce 400 */ 329 #if 0 330 // TODO: these cards are not yet supported 331 0x0400, /* Nvidia GeForce 8600 GTS */ 332 0x0402, /* Nvidia GeForce 8600 GT */ 333 0x0407, /* Nvidia GeForce 8600M GT */ 334 0x0421, /* Nvidia GeForce 8500 GT */ 335 0x0422, /* Nvidia GeForce 8400 GS */ 336 0x0423, /* Nvidia GeForce 8300 GS */ 337 #endif 338 0 339 }; 340 341 static uint16 elsa_device_list[] = { 342 0x0c60, /* Elsa Gladiac Geforce2 MX */ 343 0 344 }; 345 346 static uint16 nvstbsgs_device_list[] = { 347 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 348 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 349 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 350 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 351 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 352 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 353 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 354 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 355 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 356 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 357 0 358 }; 359 360 static uint16 varisys_device_list[] = { 361 0x3503, /* Varisys GeForce4 MX440 */ 362 0x3505, /* Varisys GeForce4 Ti 4200 */ 363 0 364 }; 365 366 static struct { 367 uint16 vendor; 368 uint16 *devices; 369 } SupportedDevices[] = { 370 {VENDOR_ID_NVIDIA, nvidia_device_list}, 371 {VENDOR_ID_ELSA, elsa_device_list}, 372 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 373 {VENDOR_ID_VARISYS, varisys_device_list}, 374 {0x0000, NULL} 375 }; 376 377 static nv_settings sSettings = { // see comments in nvidia.settings 378 /* for driver */ 379 DRIVER_PREFIX ".accelerant", 380 "none", // primary 381 false, // dumprom 382 /* for accelerant */ 383 0x00000000, // logmask 384 0, // memory 385 0, // tv_output 386 true, // usebios 387 true, // hardcursor 388 false, // switchhead 389 false, // force_pci 390 false, // unhide_fw 391 true, // pgm_panel 392 true, // dma_acc 393 false, // vga_on_tv 394 false, // force_sync 395 false, // force_ws 396 0, // gpu_clk 397 0, // ram_clk 398 }; 399 400 401 static void 402 dumprom(void *rom, uint32 size, pci_info pcii) 403 { 404 int fd; 405 uint32 cnt; 406 char fname[64]; 407 408 /* determine the romfile name: we need split-up per card in the system */ 409 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 410 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 411 412 fd = open (fname, O_WRONLY | O_CREAT, 0666); 413 if (fd < 0) return; 414 415 /* apparantly max. 32kb may be written at once; 416 * the ROM size is a multiple of that anyway. */ 417 for (cnt = 0; (cnt < size); cnt += 32768) 418 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 419 close (fd); 420 } 421 422 423 /*! return 1 if vblank interrupt has occured */ 424 static int 425 caused_vbi_crtc1(vuint32 * regs) 426 { 427 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 428 } 429 430 431 /*! clear the vblank interrupt */ 432 static void 433 clear_vbi_crtc1(vuint32 * regs) 434 { 435 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 436 } 437 438 439 static void 440 enable_vbi_crtc1(vuint32 * regs) 441 { 442 /* clear the vblank interrupt */ 443 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 444 /* enable nVidia interrupt source vblank */ 445 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 446 /* enable nVidia interrupt system hardware (b0-1) */ 447 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 448 } 449 450 451 static void 452 disable_vbi_crtc1(vuint32 * regs) 453 { 454 /* disable nVidia interrupt source vblank */ 455 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 456 /* clear the vblank interrupt */ 457 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 458 } 459 460 461 /*! return 1 if vblank interrupt has occured */ 462 static int 463 caused_vbi_crtc2(vuint32 * regs) 464 { 465 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 466 } 467 468 469 /*! clear the vblank interrupt */ 470 static void 471 clear_vbi_crtc2(vuint32 * regs) 472 { 473 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 474 } 475 476 477 static void 478 enable_vbi_crtc2(vuint32 * regs) 479 { 480 /* clear the vblank interrupt */ 481 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 482 /* enable nVidia interrupt source vblank */ 483 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 484 /* enable nVidia interrupt system hardware (b0-1) */ 485 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 486 } 487 488 489 static void 490 disable_vbi_crtc2(vuint32 * regs) 491 { 492 /* disable nVidia interrupt source vblank */ 493 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 494 /* clear the vblank interrupt */ 495 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 496 } 497 498 499 //fixme: 500 //dangerous code, on singlehead cards better not try accessing secondary head 501 //registers (card might react in unpredictable ways, though there's only a small 502 //chance we actually run into this). 503 //fix requires (some) card recognition code to be moved from accelerant to 504 //kerneldriver... 505 static void 506 disable_vbi_all(vuint32 * regs) 507 { 508 /* disable nVidia interrupt source vblank */ 509 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 510 /* clear the vblank interrupt */ 511 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 512 513 /* disable nVidia interrupt source vblank */ 514 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 515 /* clear the vblank interrupt */ 516 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 517 518 /* disable nVidia interrupt system hardware (b0-1) */ 519 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 520 } 521 522 523 static status_t 524 map_device(device_info *di) 525 { 526 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 527 shared_info *si = di->si; 528 uint32 tmpUlong, tmpROMshadow; 529 pci_info *pcii = &(di->pcii); 530 system_info sysinfo; 531 532 /* variables for making copy of ROM */ 533 uint8* rom_temp; 534 area_id rom_area = -1; 535 536 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 537 int registers = 0; 538 int frame_buffer = 1; 539 540 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 541 tmpUlong = get_pci(PCI_command, 2); 542 /* enable PCI access */ 543 tmpUlong |= PCI_command_memory; 544 /* enable busmastering */ 545 tmpUlong |= PCI_command_master; 546 /* disable ISA I/O access */ 547 tmpUlong &= ~PCI_command_io; 548 set_pci(PCI_command, 2, tmpUlong); 549 550 /*work out which version of BeOS is running*/ 551 get_system_info(&sysinfo); 552 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 553 { 554 si->use_clone_bugfix = 1; 555 } 556 else 557 { 558 si->use_clone_bugfix = 0; 559 } 560 561 /* work out a name for the register mapping */ 562 sprintf(buffer, DEVICE_FORMAT " regs", 563 di->pcii.vendor_id, di->pcii.device_id, 564 di->pcii.bus, di->pcii.device, di->pcii.function); 565 566 /* get a virtual memory address for the registers*/ 567 si->regs_area = map_physical_memory( 568 buffer, 569 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 570 (void *) di->pcii.u.h0.base_registers_pci[registers], 571 di->pcii.u.h0.base_register_sizes[registers], 572 B_ANY_KERNEL_ADDRESS, 573 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 574 (void **)&(di->regs)); 575 si->clone_bugfix_regs = (uint32 *) di->regs; 576 577 /* if mapping registers to vmem failed then pass on error */ 578 if (si->regs_area < 0) return si->regs_area; 579 580 /* work out a name for the ROM mapping*/ 581 sprintf(buffer, DEVICE_FORMAT " rom", 582 di->pcii.vendor_id, di->pcii.device_id, 583 di->pcii.bus, di->pcii.device, di->pcii.function); 584 585 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 586 /* warning: 587 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 588 * NV18, NV28 and NV34 keep working. 589 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 590 * however the actual ROM content (so the used part) is intact (confirmed). */ 591 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 592 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 593 set_pci(NVCFG_ROMSHADOW, 4, 0); 594 595 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 596 tmpUlong = get_pci(PCI_rom_base, 4); 597 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 598 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 599 //legacy space will get us into trouble if we aren't the primary graphics card!! 600 //(as legacy space always has the primary card's ROM 'mapped'!) 601 if (tmpUlong) { 602 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 603 tmpUlong |= 0x00000001; 604 set_pci(PCI_rom_base, 4, tmpUlong); 605 606 rom_area = map_physical_memory( 607 buffer, 608 (void *)di->pcii.u.h0.rom_base_pci, 609 di->pcii.u.h0.rom_size, 610 B_ANY_KERNEL_ADDRESS, 611 B_READ_AREA, 612 (void **)&(rom_temp) 613 ); 614 615 /* check if we got the BIOS and signature (might fail on laptops..) */ 616 if (rom_area >= 0) { 617 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 618 /* apparantly no ROM is mapped here */ 619 delete_area(rom_area); 620 rom_area = -1; 621 /* force using ISA legacy map as fall-back */ 622 tmpUlong = 0x00000000; 623 } 624 } else { 625 /* mapping failed: force using ISA legacy map as fall-back */ 626 tmpUlong = 0x00000000; 627 } 628 } 629 630 if (!tmpUlong) { 631 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 632 rom_area = map_physical_memory(buffer, (void *)0x000c0000, 633 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 634 } 635 636 /* if mapping ROM to vmem failed then clean up and pass on error */ 637 if (rom_area < 0) { 638 delete_area(si->regs_area); 639 si->regs_area = -1; 640 return rom_area; 641 } 642 643 /* dump ROM to file if selected in nvidia.settings 644 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 645 if (sSettings.dumprom) 646 dumprom(rom_temp, 65536, di->pcii); 647 648 /* make a copy of ROM for future reference */ 649 memcpy(si->rom_mirror, rom_temp, 65536); 650 651 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 652 tmpUlong = get_pci(PCI_rom_base, 4); 653 tmpUlong &= 0xfffffffe; 654 set_pci(PCI_rom_base, 4, tmpUlong); 655 delete_area(rom_area); 656 657 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 658 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 659 660 /* work out a name for the framebuffer mapping*/ 661 sprintf(buffer, DEVICE_FORMAT " framebuffer", 662 di->pcii.vendor_id, di->pcii.device_id, 663 di->pcii.bus, di->pcii.device, di->pcii.function); 664 665 /* map the framebuffer into vmem, using Write Combining*/ 666 si->fb_area = map_physical_memory(buffer, 667 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 668 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 669 di->pcii.u.h0.base_register_sizes[frame_buffer], 670 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 671 B_READ_AREA | B_WRITE_AREA, 672 &(si->framebuffer)); 673 674 /*if failed with write combining try again without*/ 675 if (si->fb_area < 0) { 676 si->fb_area = map_physical_memory(buffer, 677 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 678 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 679 di->pcii.u.h0.base_register_sizes[frame_buffer], 680 B_ANY_KERNEL_BLOCK_ADDRESS, 681 B_READ_AREA | B_WRITE_AREA, 682 &(si->framebuffer)); 683 } 684 685 /* if there was an error, delete our other areas and pass on error*/ 686 if (si->fb_area < 0) { 687 delete_area(si->regs_area); 688 si->regs_area = -1; 689 return si->fb_area; 690 } 691 692 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 693 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 694 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 695 696 // remember settings for use here and in accelerant 697 si->settings = sSettings; 698 699 /* in any case, return the result */ 700 return si->fb_area; 701 } 702 703 704 static void 705 unmap_device(device_info *di) 706 { 707 shared_info *si = di->si; 708 uint32 tmpUlong; 709 pci_info *pcii = &(di->pcii); 710 711 /* disable memory mapped IO */ 712 tmpUlong = get_pci(PCI_command, 4); 713 tmpUlong &= 0xfffffffc; 714 set_pci(PCI_command, 4, tmpUlong); 715 /* delete the areas */ 716 if (si->regs_area >= 0) 717 delete_area(si->regs_area); 718 if (si->fb_area >= 0) 719 delete_area(si->fb_area); 720 si->regs_area = si->fb_area = -1; 721 si->framebuffer = NULL; 722 di->regs = NULL; 723 } 724 725 726 static void 727 probe_devices(void) 728 { 729 uint32 pci_index = 0; 730 uint32 count = 0; 731 device_info *di = pd->di; 732 char tmp_name[B_OS_NAME_LENGTH]; 733 734 /* while there are more pci devices */ 735 while (count < MAX_DEVICES 736 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 737 int vendor = 0; 738 739 /* if we match a supported vendor */ 740 while (SupportedDevices[vendor].vendor) { 741 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 742 uint16 *devices = SupportedDevices[vendor].devices; 743 /* while there are more supported devices */ 744 while (*devices) { 745 /* if we match a supported device */ 746 if (*devices == di->pcii.device_id ) { 747 /* publish the device name */ 748 sprintf(tmp_name, DEVICE_FORMAT, 749 di->pcii.vendor_id, di->pcii.device_id, 750 di->pcii.bus, di->pcii.device, di->pcii.function); 751 /* tweak the exported name to show first in the alphabetically ordered /dev/ 752 * hierarchy folder, so the system will use it as primary adaptor if requested 753 * via nvidia.settings. */ 754 if (strcmp(tmp_name, sSettings.primary) == 0) 755 sprintf(tmp_name, "-%s", sSettings.primary); 756 /* add /dev/ hierarchy path */ 757 sprintf(di->name, "graphics/%s", tmp_name); 758 /* remember the name */ 759 pd->device_names[count] = di->name; 760 /* mark the driver as available for R/W open */ 761 di->is_open = 0; 762 /* mark areas as not yet created */ 763 di->shared_area = -1; 764 /* mark pointer to shared data as invalid */ 765 di->si = NULL; 766 /* inc pointer to device info */ 767 di++; 768 /* inc count */ 769 count++; 770 /* break out of these while loops */ 771 goto next_device; 772 } 773 /* next supported device */ 774 devices++; 775 } 776 } 777 vendor++; 778 } 779 next_device: 780 /* next pci_info struct, please */ 781 pci_index++; 782 } 783 /* propagate count */ 784 pd->count = count; 785 /* terminate list of device names with a null pointer */ 786 pd->device_names[pd->count] = NULL; 787 } 788 789 790 static uint32 791 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 792 { 793 uint32 handled = B_HANDLED_INTERRUPT; 794 /* release the vblank semaphore */ 795 if (si->vblank >= 0) { 796 int32 blocked; 797 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 798 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 799 handled = B_INVOKE_SCHEDULER; 800 } 801 } 802 return handled; 803 } 804 805 806 static int32 807 nv_interrupt(void *data) 808 { 809 int32 handled = B_UNHANDLED_INTERRUPT; 810 device_info *di = (device_info *)data; 811 shared_info *si = di->si; 812 int32 *flags = &(si->flags); 813 vuint32 *regs; 814 815 /* is someone already handling an interrupt for this device? */ 816 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 817 818 /* get regs */ 819 regs = di->regs; 820 821 /* was it a VBI? */ 822 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 823 if (si->ps.secondary_head) { 824 //fixme: 825 //rewrite once we use one driver instance 'per head' (instead of 'per card') 826 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 827 /* clear the interrupt(s) */ 828 clear_vbi_crtc1(regs); 829 clear_vbi_crtc2(regs); 830 /* release the semaphore */ 831 handled = thread_interrupt_work(flags, regs, si); 832 } 833 } else { 834 if (caused_vbi_crtc1(regs)) { 835 /* clear the interrupt */ 836 clear_vbi_crtc1(regs); 837 /* release the semaphore */ 838 handled = thread_interrupt_work(flags, regs, si); 839 } 840 } 841 842 /* note that we're not in the handler any more */ 843 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 844 845 exit0: 846 return handled; 847 } 848 849 850 // #pragma mark - device hooks 851 852 853 static status_t 854 open_hook(const char* name, uint32 flags, void** cookie) 855 { 856 int32 index = 0; 857 device_info *di; 858 shared_info *si; 859 thread_id thid; 860 thread_info thinfo; 861 status_t result = B_OK; 862 char shared_name[B_OS_NAME_LENGTH]; 863 physical_entry map[1]; 864 size_t net_buf_size; 865 void *unaligned_dma_buffer; 866 867 /* find the device name in the list of devices */ 868 /* we're never passed a name we didn't publish */ 869 while (pd->device_names[index] 870 && (strcmp(name, pd->device_names[index]) != 0)) 871 index++; 872 873 /* for convienience */ 874 di = &(pd->di[index]); 875 876 /* make sure no one else has write access to the common data */ 877 AQUIRE_BEN(pd->kernel); 878 879 /* if it's already open for writing */ 880 if (di->is_open) { 881 /* mark it open another time */ 882 goto mark_as_open; 883 } 884 /* create the shared_info area */ 885 sprintf(shared_name, DEVICE_FORMAT " shared", 886 di->pcii.vendor_id, di->pcii.device_id, 887 di->pcii.bus, di->pcii.device, di->pcii.function); 888 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 889 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 890 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 891 B_USER_CLONEABLE_AREA); 892 if (di->shared_area < 0) { 893 /* return the error */ 894 result = di->shared_area; 895 goto done; 896 } 897 898 /* save a few dereferences */ 899 si = di->si; 900 901 /* create the DMA command buffer area */ 902 //fixme? for R4.5 a workaround for cloning would be needed! 903 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 904 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 905 /* create the area that will hold the DMA command buffer */ 906 si->unaligned_dma_area = 907 create_area("NV DMA cmd buffer", 908 (void **)&unaligned_dma_buffer, 909 B_ANY_KERNEL_ADDRESS, 910 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 911 B_FULL_LOCK | B_CONTIGUOUS, /* both properties needed: GPU always needs access */ 912 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 913 /* on error, abort */ 914 if (si->unaligned_dma_area < 0) 915 { 916 /* free the already created shared_info area, and return the error */ 917 result = si->unaligned_dma_area; 918 goto free_shared; 919 } 920 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 921 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 922 * even on older CPU's. */ 923 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 924 si->dma_buffer_pci = (void*) 925 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 926 927 /* map the net DMA command buffer into vmem, using Write Combining */ 928 si->dma_area = map_physical_memory( 929 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 930 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 931 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 932 /* if failed with write combining try again without */ 933 if (si->dma_area < 0) { 934 si->dma_area = map_physical_memory( 935 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 936 B_ANY_KERNEL_BLOCK_ADDRESS, 937 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 938 } 939 /* if there was an error, delete our other areas and pass on error*/ 940 if (si->dma_area < 0) 941 { 942 /* free the already created areas, and return the error */ 943 result = si->dma_area; 944 goto free_shared_and_uadma; 945 } 946 947 /* save the vendor and device IDs */ 948 si->vendor_id = di->pcii.vendor_id; 949 si->device_id = di->pcii.device_id; 950 si->revision = di->pcii.revision; 951 si->bus = di->pcii.bus; 952 si->device = di->pcii.device; 953 si->function = di->pcii.function; 954 955 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 956 si->accelerant_in_use = false; 957 /* preset singlehead card to prevent early INT routine calls (once installed) to 958 * wrongly identify the INT request coming from us! */ 959 si->ps.secondary_head = false; 960 961 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 962 * unified memory architecture (UMA) */ 963 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 964 { 965 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 966 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 967 si->ps.memory_size = 1024 * 1024 * 968 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 969 /* last 64kB RAM is used for the BIOS (or something else?) */ 970 si->ps.memory_size -= (64 * 1024); 971 break; 972 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 973 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 974 si->ps.memory_size = 1024 * 1024 * 975 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 976 /* last 64kB RAM is used for the BIOS (or something else?) */ 977 si->ps.memory_size -= (64 * 1024); 978 break; 979 default: 980 /* all other cards have own RAM: the amount of which is determined in the 981 * accelerant. */ 982 break; 983 } 984 985 /* map the device */ 986 result = map_device(di); 987 if (result < 0) goto free_shared_and_alldma; 988 989 /* we will be returning OK status for sure now */ 990 result = B_OK; 991 992 /* disable and clear any pending interrupts */ 993 //fixme: 994 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 995 disable_vbi_all(di->regs); 996 997 /* preset we can't use INT related functions */ 998 si->ps.int_assigned = false; 999 1000 /* create a semaphore for vertical blank management */ 1001 si->vblank = create_sem(0, di->name); 1002 if (si->vblank < 0) goto mark_as_open; 1003 1004 /* change the owner of the semaphores to the opener's team */ 1005 /* this is required because apps can't aquire kernel semaphores */ 1006 thid = find_thread(NULL); 1007 get_thread_info(thid, &thinfo); 1008 set_sem_owner(si->vblank, thinfo.team); 1009 1010 /* If there is a valid interrupt line assigned then set up interrupts */ 1011 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1012 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1013 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1014 { 1015 /* delete the semaphore as it won't be used */ 1016 delete_sem(si->vblank); 1017 si->vblank = -1; 1018 } 1019 else 1020 { 1021 /* otherwise install our interrupt handler */ 1022 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1023 /* bail if we couldn't install the handler */ 1024 if (result != B_OK) 1025 { 1026 /* delete the semaphore as it won't be used */ 1027 delete_sem(si->vblank); 1028 si->vblank = -1; 1029 } 1030 else 1031 { 1032 /* inform accelerant(s) we can use INT related functions */ 1033 si->ps.int_assigned = true; 1034 } 1035 } 1036 1037 mark_as_open: 1038 /* mark the device open */ 1039 di->is_open++; 1040 1041 /* send the cookie to the opener */ 1042 *cookie = di; 1043 1044 goto done; 1045 1046 1047 free_shared_and_alldma: 1048 /* clean up our aligned DMA area */ 1049 delete_area(si->dma_area); 1050 si->dma_area = -1; 1051 si->dma_buffer = NULL; 1052 1053 free_shared_and_uadma: 1054 /* clean up our unaligned DMA area */ 1055 delete_area(si->unaligned_dma_area); 1056 si->unaligned_dma_area = -1; 1057 si->dma_buffer_pci = NULL; 1058 1059 free_shared: 1060 /* clean up our shared area */ 1061 delete_area(di->shared_area); 1062 di->shared_area = -1; 1063 di->si = NULL; 1064 1065 done: 1066 /* end of critical section */ 1067 RELEASE_BEN(pd->kernel); 1068 1069 /* all done, return the status */ 1070 return result; 1071 } 1072 1073 1074 static status_t 1075 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1076 { 1077 *len = 0; 1078 return B_NOT_ALLOWED; 1079 } 1080 1081 1082 static status_t 1083 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1084 { 1085 *len = 0; 1086 return B_NOT_ALLOWED; 1087 } 1088 1089 1090 static status_t 1091 close_hook(void* dev) 1092 { 1093 /* we don't do anything on close: there might be dup'd fd */ 1094 return B_NO_ERROR; 1095 } 1096 1097 1098 static status_t 1099 free_hook(void* dev) 1100 { 1101 device_info *di = (device_info *)dev; 1102 shared_info *si = di->si; 1103 vuint32 *regs = di->regs; 1104 1105 /* lock the driver */ 1106 AQUIRE_BEN(pd->kernel); 1107 1108 /* if opened multiple times, decrement the open count and exit */ 1109 if (di->is_open > 1) 1110 goto unlock_and_exit; 1111 1112 /* disable and clear any pending interrupts */ 1113 //fixme: 1114 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1115 disable_vbi_all(regs); 1116 1117 if (si->ps.int_assigned) { 1118 /* remove interrupt handler */ 1119 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1120 1121 /* delete the semaphores, ignoring any errors ('cause the owning 1122 team may have died on us) */ 1123 delete_sem(si->vblank); 1124 si->vblank = -1; 1125 } 1126 1127 /* free regs and framebuffer areas */ 1128 unmap_device(di); 1129 1130 /* clean up our aligned DMA area */ 1131 delete_area(si->dma_area); 1132 si->dma_area = -1; 1133 si->dma_buffer = NULL; 1134 1135 /* clean up our unaligned DMA area */ 1136 delete_area(si->unaligned_dma_area); 1137 si->unaligned_dma_area = -1; 1138 si->dma_buffer_pci = NULL; 1139 1140 /* clean up our shared area */ 1141 delete_area(di->shared_area); 1142 di->shared_area = -1; 1143 di->si = NULL; 1144 1145 unlock_and_exit: 1146 /* mark the device available */ 1147 di->is_open--; 1148 /* unlock the driver */ 1149 RELEASE_BEN(pd->kernel); 1150 /* all done */ 1151 return B_OK; 1152 } 1153 1154 1155 static status_t 1156 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1157 { 1158 device_info *di = (device_info *)dev; 1159 status_t result = B_DEV_INVALID_IOCTL; 1160 uint32 tmpUlong; 1161 1162 switch (msg) { 1163 /* the only PUBLIC ioctl */ 1164 case B_GET_ACCELERANT_SIGNATURE: 1165 { 1166 strcpy((char* )buf, sSettings.accelerant); 1167 result = B_OK; 1168 break; 1169 } 1170 1171 /* PRIVATE ioctl from here on */ 1172 case NV_GET_PRIVATE_DATA: 1173 { 1174 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1175 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1176 gpd->shared_info_area = di->shared_area; 1177 result = B_OK; 1178 } 1179 break; 1180 } 1181 1182 case NV_GET_PCI: 1183 { 1184 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1185 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1186 pci_info *pcii = &(di->pcii); 1187 gsp->value = get_pci(gsp->offset, gsp->size); 1188 result = B_OK; 1189 } 1190 break; 1191 } 1192 1193 case NV_SET_PCI: 1194 { 1195 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1196 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1197 pci_info *pcii = &(di->pcii); 1198 set_pci(gsp->offset, gsp->size, gsp->value); 1199 result = B_OK; 1200 } 1201 break; 1202 } 1203 1204 case NV_DEVICE_NAME: 1205 { 1206 nv_device_name *dn = (nv_device_name *)buf; 1207 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1208 strcpy(dn->name, di->name); 1209 result = B_OK; 1210 } 1211 break; 1212 } 1213 1214 case NV_RUN_INTERRUPTS: 1215 { 1216 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1217 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1218 vuint32 *regs = di->regs; 1219 if (!(vi->crtc)) { 1220 if (vi->do_it) { 1221 enable_vbi_crtc1(regs); 1222 } else { 1223 disable_vbi_crtc1(regs); 1224 } 1225 } else { 1226 if (vi->do_it) { 1227 enable_vbi_crtc2(regs); 1228 } else { 1229 disable_vbi_crtc2(regs); 1230 } 1231 } 1232 result = B_OK; 1233 } 1234 break; 1235 } 1236 1237 case NV_GET_NTH_AGP_INFO: 1238 { 1239 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1240 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1241 nai->exist = false; 1242 nai->agp_bus = false; 1243 if (agp_bus) { 1244 nai->agp_bus = true; 1245 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1246 nai->exist = true; 1247 } 1248 } 1249 result = B_OK; 1250 } 1251 break; 1252 } 1253 1254 case NV_ENABLE_AGP: 1255 { 1256 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1257 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1258 if (agp_bus) { 1259 nca->agp_bus = true; 1260 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1261 } else { 1262 nca->agp_bus = false; 1263 nca->cmd = 0; 1264 } 1265 result = B_OK; 1266 } 1267 break; 1268 } 1269 1270 case NV_ISA_OUT: 1271 { 1272 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1273 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1274 pci_info *pcii = &(di->pcii); 1275 1276 /* lock the driver: 1277 * no other graphics card may have ISA I/O enabled when we enter */ 1278 AQUIRE_BEN(pd->kernel); 1279 1280 /* enable ISA I/O access */ 1281 tmpUlong = get_pci(PCI_command, 2); 1282 tmpUlong |= PCI_command_io; 1283 set_pci(PCI_command, 2, tmpUlong); 1284 1285 if (io_isa->size == 1) 1286 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1287 else 1288 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1289 result = B_OK; 1290 1291 /* disable ISA I/O access */ 1292 tmpUlong = get_pci(PCI_command, 2); 1293 tmpUlong &= ~PCI_command_io; 1294 set_pci(PCI_command, 2, tmpUlong); 1295 1296 /* end of critical section */ 1297 RELEASE_BEN(pd->kernel); 1298 } 1299 break; 1300 } 1301 1302 case NV_ISA_IN: 1303 { 1304 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1305 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1306 pci_info *pcii = &(di->pcii); 1307 1308 /* lock the driver: 1309 * no other graphics card may have ISA I/O enabled when we enter */ 1310 AQUIRE_BEN(pd->kernel); 1311 1312 /* enable ISA I/O access */ 1313 tmpUlong = get_pci(PCI_command, 2); 1314 tmpUlong |= PCI_command_io; 1315 set_pci(PCI_command, 2, tmpUlong); 1316 1317 if (io_isa->size == 1) 1318 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1319 else 1320 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1321 result = B_OK; 1322 1323 /* disable ISA I/O access */ 1324 tmpUlong = get_pci(PCI_command, 2); 1325 tmpUlong &= ~PCI_command_io; 1326 set_pci(PCI_command, 2, tmpUlong); 1327 1328 /* end of critical section */ 1329 RELEASE_BEN(pd->kernel); 1330 } 1331 break; 1332 } 1333 } 1334 1335 return result; 1336 } 1337 1338 1339 // #pragma mark - driver API 1340 1341 1342 status_t 1343 init_hardware(void) 1344 { 1345 long index = 0; 1346 pci_info pcii; 1347 bool found = false; 1348 1349 /* choke if we can't find the PCI bus */ 1350 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1351 return B_ERROR; 1352 1353 /* choke if we can't find the ISA bus */ 1354 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1355 { 1356 put_module(B_PCI_MODULE_NAME); 1357 return B_ERROR; 1358 } 1359 1360 /* while there are more pci devices */ 1361 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1362 int vendor = 0; 1363 1364 /* if we match a supported vendor */ 1365 while (SupportedDevices[vendor].vendor) { 1366 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1367 uint16 *devices = SupportedDevices[vendor].devices; 1368 /* while there are more supported devices */ 1369 while (*devices) { 1370 /* if we match a supported device */ 1371 if (*devices == pcii.device_id ) { 1372 1373 found = true; 1374 goto done; 1375 } 1376 /* next supported device */ 1377 devices++; 1378 } 1379 } 1380 vendor++; 1381 } 1382 /* next pci_info struct, please */ 1383 index++; 1384 } 1385 1386 done: 1387 /* put away the module manager */ 1388 put_module(B_PCI_MODULE_NAME); 1389 return found ? B_OK : B_ERROR; 1390 } 1391 1392 1393 status_t 1394 init_driver(void) 1395 { 1396 void *settings; 1397 1398 // get driver/accelerant settings 1399 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1400 if (settings != NULL) { 1401 const char *item; 1402 char *end; 1403 uint32 value; 1404 1405 // for driver 1406 item = get_driver_parameter(settings, "accelerant", "", ""); 1407 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1408 strcpy (sSettings.accelerant, item); 1409 1410 item = get_driver_parameter(settings, "primary", "", ""); 1411 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1412 strcpy(sSettings.primary, item); 1413 1414 sSettings.dumprom = get_driver_boolean_parameter(settings, 1415 "dumprom", false, false); 1416 1417 // for accelerant 1418 item = get_driver_parameter(settings, "logmask", 1419 "0x00000000", "0x00000000"); 1420 value = strtoul(item, &end, 0); 1421 if (*end == '\0') 1422 sSettings.logmask = value; 1423 1424 item = get_driver_parameter(settings, "memory", "0", "0"); 1425 value = strtoul(item, &end, 0); 1426 if (*end == '\0') 1427 sSettings.memory = value; 1428 1429 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1430 value = strtoul(item, &end, 0); 1431 if (*end == '\0') 1432 sSettings.tv_output = value; 1433 1434 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1435 "hardcursor", false, false); 1436 sSettings.usebios = get_driver_boolean_parameter(settings, 1437 "usebios", false, false); 1438 sSettings.switchhead = get_driver_boolean_parameter(settings, 1439 "switchhead", false, false); 1440 sSettings.force_pci = get_driver_boolean_parameter(settings, 1441 "force_pci", false, false); 1442 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1443 "unhide_fw", false, false); 1444 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1445 "pgm_panel", false, false); 1446 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1447 "dma_acc", false, false); 1448 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1449 "vga_on_tv", false, false); 1450 sSettings.force_sync = get_driver_boolean_parameter(settings, 1451 "force_sync", false, false); 1452 sSettings.force_ws = get_driver_boolean_parameter(settings, 1453 "force_ws", false, false); 1454 1455 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1456 value = strtoul(item, &end, 0); 1457 if (*end == '\0') 1458 sSettings.gpu_clk = value; 1459 1460 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1461 value = strtoul(item, &end, 0); 1462 if (*end == '\0') 1463 sSettings.ram_clk = value; 1464 1465 unload_driver_settings(settings); 1466 } 1467 1468 /* get a handle for the pci bus */ 1469 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1470 return B_ERROR; 1471 1472 /* get a handle for the isa bus */ 1473 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1474 put_module(B_PCI_MODULE_NAME); 1475 return B_ERROR; 1476 } 1477 1478 /* get a handle for the agp bus if it exists */ 1479 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1480 1481 /* driver private data */ 1482 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1483 if (!pd) { 1484 put_module(B_PCI_MODULE_NAME); 1485 return B_ERROR; 1486 } 1487 /* initialize the benaphore */ 1488 INIT_BEN(pd->kernel); 1489 /* find all of our supported devices */ 1490 probe_devices(); 1491 return B_OK; 1492 } 1493 1494 1495 const char ** 1496 publish_devices(void) 1497 { 1498 /* return the list of supported devices */ 1499 return (const char **)pd->device_names; 1500 } 1501 1502 1503 device_hooks * 1504 find_device(const char *name) 1505 { 1506 int index = 0; 1507 while (pd->device_names[index]) { 1508 if (strcmp(name, pd->device_names[index]) == 0) 1509 return &graphics_device_hooks; 1510 index++; 1511 } 1512 return NULL; 1513 1514 } 1515 1516 1517 void 1518 uninit_driver(void) 1519 { 1520 /* free the driver data */ 1521 DELETE_BEN(pd->kernel); 1522 free(pd); 1523 pd = NULL; 1524 1525 /* put the pci module away */ 1526 put_module(B_PCI_MODULE_NAME); 1527 put_module(B_ISA_MODULE_NAME); 1528 1529 /* put the agp module away if it's there */ 1530 if (agp_bus) 1531 put_module(B_AGP_GART_MODULE_NAME); 1532 } 1533 1534