1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-9/2009. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_gart_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 109 0x0041, /* Nvidia GeForce FX 6800 */ 110 0x0042, /* Nvidia GeForce FX 6800LE */ 111 0x0043, /* Nvidia GeForce 6800 XE */ 112 0x0045, /* Nvidia GeForce FX 6800 GT */ 113 0x0046, /* Nvidia GeForce FX 6800 GT */ 114 0x0047, /* Nvidia GeForce 6800 GS */ 115 0x0048, /* Nvidia GeForce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia GeForce 6800 GS */ 126 0x00c1, /* Nvidia GeForce FX 6800 */ 127 0x00c2, /* Nvidia GeForce FX 6800LE */ 128 0x00c3, /* Nvidia GeForce FX 6800 XT */ 129 0x00c8, /* Nvidia GeForce FX 6800 Go */ 130 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 137 0x00f3, /* Nvidia GeForce 6200 */ 138 0x00f4, /* Nvidia GeForce 6600 LE */ 139 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia GeForce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 149 0x0100, /* Nvidia GeForce256 SDR */ 150 0x0101, /* Nvidia GeForce256 DDR */ 151 0x0102, /* Nvidia GeForce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia GeForce2 MX/MX400 */ 154 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia GeForce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia GeForce FX 6600 GT */ 158 0x0141, /* Nvidia GeForce FX 6600 */ 159 0x0142, /* Nvidia GeForce FX 6600LE */ 160 0x0143, /* Nvidia GeForce 6600 VE */ 161 0x0144, /* Nvidia GeForce FX 6600 Go */ 162 0x0145, /* Nvidia GeForce FX 6610 XL */ 163 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia GeForce FX 6700 XL */ 165 0x0148, /* Nvidia GeForce FX 6600 Go */ 166 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia GeForce2 GTS/Pro */ 173 0x0151, /* Nvidia GeForce2 Ti DDR */ 174 0x0152, /* Nvidia GeForce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia GeForce 6500 Go */ 177 0x0161, /* Nvidia GeForce 6200 TurboCache */ 178 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 179 0x0163, /* Nvidia GeForce 6200LE */ 180 0x0164, /* Nvidia GeForce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia GeForce 6400 Go */ 183 0x0167, /* Nvidia GeForce 6200 Go */ 184 0x0168, /* Nvidia GeForce 6400 Go */ 185 0x0169, /* Nvidia GeForce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia GeForce4 MX 460 */ 192 0x0171, /* Nvidia GeForce4 MX 440 */ 193 0x0172, /* Nvidia GeForce4 MX 420 */ 194 0x0173, /* Nvidia GeForce4 MX 440SE */ 195 0x0174, /* Nvidia GeForce4 440 Go */ 196 0x0175, /* Nvidia GeForce4 420 Go */ 197 0x0176, /* Nvidia GeForce4 420 Go 32M */ 198 0x0177, /* Nvidia GeForce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia GeForce4 410 Go 16M */ 204 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia GeForce4 448 Go */ 209 0x0187, /* Nvidia GeForce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia GeForce4 448 Go */ 216 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 217 0x01d1, /* Nvidia GeForce 7300 LE */ 218 0x01d3, /* Nvidia GeForce 7300 SE */ 219 0x01d7, /* Nvidia Quadro NVS 110M/GeForce 7300 Go */ 220 0x01d8, /* Nvidia GeForce 7400 GO */ 221 0x01dd, /* Nvidia GeForce 7500 LE */ 222 0x01df, /* Nvidia GeForce 7300 GS */ 223 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 224 0x0200, /* Nvidia GeForce3 */ 225 0x0201, /* Nvidia GeForce3 Ti 200 */ 226 0x0202, /* Nvidia GeForce3 Ti 500 */ 227 0x0203, /* Nvidia Quadro DCC */ 228 0x0211, /* Nvidia GeForce FX 6800 */ 229 0x0212, /* Nvidia GeForce FX 6800LE */ 230 0x0215, /* Nvidia GeForce FX 6800 GT */ 231 0x0218, /* Nvidia GeForce 6800 XT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 239 0x0244, /* Nvidia GeForce Go 6150 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / GeForce 6150LE */ 241 0x0247, /* Nvidia GeForce 6100 Go (NFORCE4 Integr.GPU) */ 242 0x0250, /* Nvidia GeForce4 Ti 4600 */ 243 0x0251, /* Nvidia GeForce4 Ti 4400 */ 244 0x0252, /* Nvidia GeForce4 Ti 4600 */ 245 0x0253, /* Nvidia GeForce4 Ti 4200 */ 246 0x0258, /* Nvidia Quadro4 900 XGL */ 247 0x0259, /* Nvidia Quadro4 750 XGL */ 248 0x025b, /* Nvidia Quadro4 700 XGL */ 249 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 250 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 251 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 252 0x0286, /* Nvidia GeForce4 4200 Go */ 253 0x0288, /* Nvidia Quadro4 980 XGL */ 254 0x0289, /* Nvidia Quadro4 780 XGL */ 255 0x028c, /* Nvidia Quadro4 700 GoGL */ 256 0x0290, /* Nvidia GeForce 7900 GTX */ 257 0x0291, /* Nvidia GeForce 7900 GT */ 258 0x0293, /* Nvidia GeForce 7900 GX2 */ 259 0x0294, /* Nvidia GeForce 7950 GX2 */ 260 0x0295, /* Nvidia GeForce 7950 GT */ 261 0x0298, /* Nvidia GeForce Go 7900 GS */ 262 0x0299, /* Nvidia GeForce Go 7900 GTX */ 263 0x029c, /* Nvidia Quadro FX 5500 */ 264 0x029f, /* Nvidia Quadro FX 4500 X2 */ 265 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 266 0x02e0, /* Nvidia GeForce 7600 GT */ 267 0x02e1, /* Nvidia GeForce 7600 GS */ 268 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 269 0x0302, /* Nvidia GeForce FX 5800 */ 270 0x0308, /* Nvidia Quadro FX 2000 */ 271 0x0309, /* Nvidia Quadro FX 1000 */ 272 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 273 0x0312, /* Nvidia GeForce FX 5600 */ 274 0x0313, /* Nvidia unknown FX */ 275 0x0314, /* Nvidia GeForce FX 5600XT */ 276 0x0316, /* Nvidia unknown FX Go */ 277 0x0317, /* Nvidia unknown FX Go */ 278 0x031a, /* Nvidia GeForce FX 5600 Go */ 279 0x031b, /* Nvidia GeForce FX 5650 Go */ 280 0x031c, /* Nvidia Quadro FX 700 Go */ 281 0x031d, /* Nvidia unknown FX Go */ 282 0x031e, /* Nvidia unknown FX Go */ 283 0x031f, /* Nvidia unknown FX Go */ 284 0x0320, /* Nvidia GeForce FX 5200 */ 285 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 286 0x0322, /* Nvidia GeForce FX 5200 */ 287 0x0323, /* Nvidia GeForce FX 5200LE */ 288 0x0324, /* Nvidia GeForce FX 5200 Go */ 289 0x0325, /* Nvidia GeForce FX 5250 Go */ 290 0x0326, /* Nvidia GeForce FX 5500 */ 291 0x0327, /* Nvidia GeForce FX 5100 */ 292 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 293 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 294 0x032a, /* Nvidia Quadro NVS 280 PCI */ 295 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 296 0x032c, /* Nvidia GeForce FX 5300 Go */ 297 0x032d, /* Nvidia GeForce FX 5100 Go */ 298 0x032e, /* Nvidia unknown FX Go */ 299 0x032f, /* Nvidia unknown FX Go */ 300 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 301 0x0331, /* Nvidia GeForce FX 5900 */ 302 0x0332, /* Nvidia GeForce FX 5900 XT */ 303 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 304 0x0334, /* Nvidia GeForce FX 5900 ZT */ 305 0x0338, /* Nvidia Quadro FX 3000 */ 306 0x033f, /* Nvidia Quadro FX 700 */ 307 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 308 0x0342, /* Nvidia GeForce FX 5700 */ 309 0x0343, /* Nvidia GeForce FX 5700LE */ 310 0x0344, /* Nvidia GeForce FX 5700VE */ 311 0x0345, /* Nvidia unknown FX */ 312 0x0347, /* Nvidia GeForce FX 5700 Go */ 313 0x0348, /* Nvidia GeForce FX 5700 Go */ 314 0x0349, /* Nvidia unknown FX Go */ 315 0x034b, /* Nvidia unknown FX Go */ 316 0x034c, /* Nvidia Quadro FX 1000 Go */ 317 0x034e, /* Nvidia Quadro FX 1100 */ 318 0x034f, /* Nvidia unknown FX */ 319 0x0391, /* Nvidia GeForce 7600 GT */ 320 0x0392, /* Nvidia GeForce 7600 GS */ 321 0x0393, /* Nvidia GeForce 7300 GT */ 322 0x0394, /* Nvidia GeForce 7600 LE */ 323 0x0398, /* Nvidia GeForce 7600 GO */ 324 0x03d0, /* Nvidia GeForce 6100 nForce 430 */ 325 0x03d1, /* Nvidia GeForce 6100 nForce 405 */ 326 0x03d2, /* Nvidia GeForce 6100 nForce 400 */ 327 0 328 }; 329 330 static uint16 elsa_device_list[] = { 331 0x0c60, /* Elsa Gladiac Geforce2 MX */ 332 0 333 }; 334 335 static uint16 nvstbsgs_device_list[] = { 336 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 337 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 338 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 339 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 340 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 341 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 342 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 343 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 344 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 345 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 346 0 347 }; 348 349 static uint16 varisys_device_list[] = { 350 0x3503, /* Varisys GeForce4 MX440 */ 351 0x3505, /* Varisys GeForce4 Ti 4200 */ 352 0 353 }; 354 355 static struct { 356 uint16 vendor; 357 uint16 *devices; 358 } SupportedDevices[] = { 359 {VENDOR_ID_NVIDIA, nvidia_device_list}, 360 {VENDOR_ID_ELSA, elsa_device_list}, 361 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 362 {VENDOR_ID_VARISYS, varisys_device_list}, 363 {0x0000, NULL} 364 }; 365 366 static nv_settings sSettings = { // see comments in nvidia.settings 367 /* for driver */ 368 DRIVER_PREFIX ".accelerant", 369 "none", // primary 370 false, // dumprom 371 /* for accelerant */ 372 0x00000000, // logmask 373 0, // memory 374 0, // tv_output 375 true, // usebios 376 true, // hardcursor 377 false, // switchhead 378 false, // force_pci 379 false, // unhide_fw 380 false, // pgm_panel 381 true, // dma_acc 382 false, // vga_on_tv 383 false, // force_sync 384 false, // force_ws 385 false, // block_acc 386 0, // gpu_clk 387 0, // ram_clk 388 }; 389 390 391 static void 392 dumprom(void *rom, uint32 size, pci_info pcii) 393 { 394 int fd; 395 uint32 cnt; 396 char fname[64]; 397 398 /* determine the romfile name: we need split-up per card in the system */ 399 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 400 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 401 402 fd = open (fname, O_WRONLY | O_CREAT, 0666); 403 if (fd < 0) return; 404 405 /* apparantly max. 32kb may be written at once; 406 * the ROM size is a multiple of that anyway. */ 407 for (cnt = 0; (cnt < size); cnt += 32768) 408 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 409 close (fd); 410 } 411 412 413 /*! return 1 if vblank interrupt has occured */ 414 static int 415 caused_vbi_crtc1(vuint32 * regs) 416 { 417 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 418 } 419 420 421 /*! clear the vblank interrupt */ 422 static void 423 clear_vbi_crtc1(vuint32 * regs) 424 { 425 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 426 } 427 428 429 static void 430 enable_vbi_crtc1(vuint32 * regs) 431 { 432 /* clear the vblank interrupt */ 433 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 434 /* enable nVidia interrupt source vblank */ 435 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 436 /* enable nVidia interrupt system hardware (b0-1) */ 437 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 438 } 439 440 441 static void 442 disable_vbi_crtc1(vuint32 * regs) 443 { 444 /* disable nVidia interrupt source vblank */ 445 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 446 /* clear the vblank interrupt */ 447 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 448 } 449 450 451 /*! return 1 if vblank interrupt has occured */ 452 static int 453 caused_vbi_crtc2(vuint32 * regs) 454 { 455 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 456 } 457 458 459 /*! clear the vblank interrupt */ 460 static void 461 clear_vbi_crtc2(vuint32 * regs) 462 { 463 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 464 } 465 466 467 static void 468 enable_vbi_crtc2(vuint32 * regs) 469 { 470 /* clear the vblank interrupt */ 471 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 472 /* enable nVidia interrupt source vblank */ 473 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 474 /* enable nVidia interrupt system hardware (b0-1) */ 475 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 476 } 477 478 479 static void 480 disable_vbi_crtc2(vuint32 * regs) 481 { 482 /* disable nVidia interrupt source vblank */ 483 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 484 /* clear the vblank interrupt */ 485 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 486 } 487 488 489 //fixme: 490 //dangerous code, on singlehead cards better not try accessing secondary head 491 //registers (card might react in unpredictable ways, though there's only a small 492 //chance we actually run into this). 493 //fix requires (some) card recognition code to be moved from accelerant to 494 //kerneldriver... 495 static void 496 disable_vbi_all(vuint32 * regs) 497 { 498 /* disable nVidia interrupt source vblank */ 499 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 500 /* clear the vblank interrupt */ 501 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 502 503 /* disable nVidia interrupt source vblank */ 504 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 505 /* clear the vblank interrupt */ 506 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 507 508 /* disable nVidia interrupt system hardware (b0-1) */ 509 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 510 } 511 512 513 static status_t 514 map_device(device_info *di) 515 { 516 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 517 shared_info *si = di->si; 518 uint32 tmpUlong, tmpROMshadow; 519 pci_info *pcii = &(di->pcii); 520 system_info sysinfo; 521 522 /* variables for making copy of ROM */ 523 uint8* rom_temp; 524 area_id rom_area = -1; 525 526 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 527 int registers = 0; 528 int frame_buffer = 1; 529 530 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 531 tmpUlong = get_pci(PCI_command, 2); 532 /* enable PCI access */ 533 tmpUlong |= PCI_command_memory; 534 /* enable busmastering */ 535 tmpUlong |= PCI_command_master; 536 /* disable ISA I/O access */ 537 tmpUlong &= ~PCI_command_io; 538 set_pci(PCI_command, 2, tmpUlong); 539 540 /*work out which version of BeOS is running*/ 541 get_system_info(&sysinfo); 542 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 543 { 544 si->use_clone_bugfix = 1; 545 } 546 else 547 { 548 si->use_clone_bugfix = 0; 549 } 550 551 /* work out a name for the register mapping */ 552 sprintf(buffer, DEVICE_FORMAT " regs", 553 di->pcii.vendor_id, di->pcii.device_id, 554 di->pcii.bus, di->pcii.device, di->pcii.function); 555 556 /* get a virtual memory address for the registers*/ 557 si->regs_area = map_physical_memory( 558 buffer, 559 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 560 (void *) di->pcii.u.h0.base_registers_pci[registers], 561 di->pcii.u.h0.base_register_sizes[registers], 562 B_ANY_KERNEL_ADDRESS, 563 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 564 (void **)&(di->regs)); 565 si->clone_bugfix_regs = (uint32 *) di->regs; 566 567 /* if mapping registers to vmem failed then pass on error */ 568 if (si->regs_area < 0) return si->regs_area; 569 570 /* work out a name for the ROM mapping*/ 571 sprintf(buffer, DEVICE_FORMAT " rom", 572 di->pcii.vendor_id, di->pcii.device_id, 573 di->pcii.bus, di->pcii.device, di->pcii.function); 574 575 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 576 /* warning: 577 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 578 * NV18, NV28 and NV34 keep working. 579 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 580 * however the actual ROM content (so the used part) is intact (confirmed). */ 581 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 582 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 583 set_pci(NVCFG_ROMSHADOW, 4, 0); 584 585 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 586 tmpUlong = get_pci(PCI_rom_base, 4); 587 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 588 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 589 //legacy space will get us into trouble if we aren't the primary graphics card!! 590 //(as legacy space always has the primary card's ROM 'mapped'!) 591 if (tmpUlong) { 592 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 593 tmpUlong |= 0x00000001; 594 set_pci(PCI_rom_base, 4, tmpUlong); 595 596 rom_area = map_physical_memory( 597 buffer, 598 (void *)di->pcii.u.h0.rom_base_pci, 599 di->pcii.u.h0.rom_size, 600 B_ANY_KERNEL_ADDRESS, 601 B_READ_AREA, 602 (void **)&(rom_temp) 603 ); 604 605 /* check if we got the BIOS and signature (might fail on laptops..) */ 606 if (rom_area >= 0) { 607 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 608 /* apparantly no ROM is mapped here */ 609 delete_area(rom_area); 610 rom_area = -1; 611 /* force using ISA legacy map as fall-back */ 612 tmpUlong = 0x00000000; 613 } 614 } else { 615 /* mapping failed: force using ISA legacy map as fall-back */ 616 tmpUlong = 0x00000000; 617 } 618 } 619 620 if (!tmpUlong) { 621 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 622 rom_area = map_physical_memory(buffer, (void *)0x000c0000, 623 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 624 } 625 626 /* if mapping ROM to vmem failed then clean up and pass on error */ 627 if (rom_area < 0) { 628 delete_area(si->regs_area); 629 si->regs_area = -1; 630 return rom_area; 631 } 632 633 /* dump ROM to file if selected in nvidia.settings 634 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 635 if (sSettings.dumprom) 636 dumprom(rom_temp, 65536, di->pcii); 637 638 /* make a copy of ROM for future reference */ 639 memcpy(si->rom_mirror, rom_temp, 65536); 640 641 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 642 tmpUlong = get_pci(PCI_rom_base, 4); 643 tmpUlong &= 0xfffffffe; 644 set_pci(PCI_rom_base, 4, tmpUlong); 645 delete_area(rom_area); 646 647 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 648 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 649 650 /* work out a name for the framebuffer mapping*/ 651 sprintf(buffer, DEVICE_FORMAT " framebuffer", 652 di->pcii.vendor_id, di->pcii.device_id, 653 di->pcii.bus, di->pcii.device, di->pcii.function); 654 655 /* map the framebuffer into vmem, using Write Combining*/ 656 si->fb_area = map_physical_memory(buffer, 657 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 658 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 659 di->pcii.u.h0.base_register_sizes[frame_buffer], 660 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 661 B_READ_AREA | B_WRITE_AREA, 662 &(si->framebuffer)); 663 664 /*if failed with write combining try again without*/ 665 if (si->fb_area < 0) { 666 si->fb_area = map_physical_memory(buffer, 667 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 668 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 669 di->pcii.u.h0.base_register_sizes[frame_buffer], 670 B_ANY_KERNEL_BLOCK_ADDRESS, 671 B_READ_AREA | B_WRITE_AREA, 672 &(si->framebuffer)); 673 } 674 675 /* if there was an error, delete our other areas and pass on error*/ 676 if (si->fb_area < 0) { 677 delete_area(si->regs_area); 678 si->regs_area = -1; 679 return si->fb_area; 680 } 681 682 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 683 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 684 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 685 686 /* note the amount of memory mapped by the kerneldriver so we can make sure we 687 * don't attempt to adress more later on */ 688 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 689 690 // remember settings for use here and in accelerant 691 si->settings = sSettings; 692 693 /* in any case, return the result */ 694 return si->fb_area; 695 } 696 697 698 static void 699 unmap_device(device_info *di) 700 { 701 shared_info *si = di->si; 702 uint32 tmpUlong; 703 pci_info *pcii = &(di->pcii); 704 705 /* disable memory mapped IO */ 706 tmpUlong = get_pci(PCI_command, 4); 707 tmpUlong &= 0xfffffffc; 708 set_pci(PCI_command, 4, tmpUlong); 709 /* delete the areas */ 710 if (si->regs_area >= 0) 711 delete_area(si->regs_area); 712 if (si->fb_area >= 0) 713 delete_area(si->fb_area); 714 si->regs_area = si->fb_area = -1; 715 si->framebuffer = NULL; 716 di->regs = NULL; 717 } 718 719 720 static void 721 probe_devices(void) 722 { 723 uint32 pci_index = 0; 724 uint32 count = 0; 725 device_info *di = pd->di; 726 char tmp_name[B_OS_NAME_LENGTH]; 727 728 /* while there are more pci devices */ 729 while (count < MAX_DEVICES 730 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 731 int vendor = 0; 732 733 /* if we match a supported vendor */ 734 while (SupportedDevices[vendor].vendor) { 735 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 736 uint16 *devices = SupportedDevices[vendor].devices; 737 /* while there are more supported devices */ 738 while (*devices) { 739 /* if we match a supported device */ 740 if (*devices == di->pcii.device_id ) { 741 /* publish the device name */ 742 sprintf(tmp_name, DEVICE_FORMAT, 743 di->pcii.vendor_id, di->pcii.device_id, 744 di->pcii.bus, di->pcii.device, di->pcii.function); 745 /* tweak the exported name to show first in the alphabetically ordered /dev/ 746 * hierarchy folder, so the system will use it as primary adaptor if requested 747 * via nvidia.settings. */ 748 if (strcmp(tmp_name, sSettings.primary) == 0) 749 sprintf(tmp_name, "-%s", sSettings.primary); 750 /* add /dev/ hierarchy path */ 751 sprintf(di->name, "graphics/%s", tmp_name); 752 /* remember the name */ 753 pd->device_names[count] = di->name; 754 /* mark the driver as available for R/W open */ 755 di->is_open = 0; 756 /* mark areas as not yet created */ 757 di->shared_area = -1; 758 /* mark pointer to shared data as invalid */ 759 di->si = NULL; 760 /* inc pointer to device info */ 761 di++; 762 /* inc count */ 763 count++; 764 /* break out of these while loops */ 765 goto next_device; 766 } 767 /* next supported device */ 768 devices++; 769 } 770 } 771 vendor++; 772 } 773 next_device: 774 /* next pci_info struct, please */ 775 pci_index++; 776 } 777 /* propagate count */ 778 pd->count = count; 779 /* terminate list of device names with a null pointer */ 780 pd->device_names[pd->count] = NULL; 781 } 782 783 784 static uint32 785 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 786 { 787 uint32 handled = B_HANDLED_INTERRUPT; 788 /* release the vblank semaphore */ 789 if (si->vblank >= 0) { 790 int32 blocked; 791 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 792 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 793 handled = B_INVOKE_SCHEDULER; 794 } 795 } 796 return handled; 797 } 798 799 800 static int32 801 nv_interrupt(void *data) 802 { 803 int32 handled = B_UNHANDLED_INTERRUPT; 804 device_info *di = (device_info *)data; 805 shared_info *si = di->si; 806 int32 *flags = &(si->flags); 807 vuint32 *regs; 808 809 /* is someone already handling an interrupt for this device? */ 810 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 811 812 /* get regs */ 813 regs = di->regs; 814 815 /* was it a VBI? */ 816 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 817 if (si->ps.secondary_head) { 818 //fixme: 819 //rewrite once we use one driver instance 'per head' (instead of 'per card') 820 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 821 /* clear the interrupt(s) */ 822 clear_vbi_crtc1(regs); 823 clear_vbi_crtc2(regs); 824 /* release the semaphore */ 825 handled = thread_interrupt_work(flags, regs, si); 826 } 827 } else { 828 if (caused_vbi_crtc1(regs)) { 829 /* clear the interrupt */ 830 clear_vbi_crtc1(regs); 831 /* release the semaphore */ 832 handled = thread_interrupt_work(flags, regs, si); 833 } 834 } 835 836 /* note that we're not in the handler any more */ 837 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 838 839 exit0: 840 return handled; 841 } 842 843 844 // #pragma mark - device hooks 845 846 847 static status_t 848 open_hook(const char* name, uint32 flags, void** cookie) 849 { 850 int32 index = 0; 851 device_info *di; 852 shared_info *si; 853 thread_id thid; 854 thread_info thinfo; 855 status_t result = B_OK; 856 char shared_name[B_OS_NAME_LENGTH]; 857 physical_entry map[1]; 858 size_t net_buf_size; 859 void *unaligned_dma_buffer; 860 uint32 mem_size; 861 862 /* find the device name in the list of devices */ 863 /* we're never passed a name we didn't publish */ 864 while (pd->device_names[index] 865 && (strcmp(name, pd->device_names[index]) != 0)) 866 index++; 867 868 /* for convienience */ 869 di = &(pd->di[index]); 870 871 /* make sure no one else has write access to the common data */ 872 AQUIRE_BEN(pd->kernel); 873 874 /* if it's already open for writing */ 875 if (di->is_open) { 876 /* mark it open another time */ 877 goto mark_as_open; 878 } 879 /* create the shared_info area */ 880 sprintf(shared_name, DEVICE_FORMAT " shared", 881 di->pcii.vendor_id, di->pcii.device_id, 882 di->pcii.bus, di->pcii.device, di->pcii.function); 883 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 884 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 885 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 886 B_USER_CLONEABLE_AREA); 887 if (di->shared_area < 0) { 888 /* return the error */ 889 result = di->shared_area; 890 goto done; 891 } 892 893 /* save a few dereferences */ 894 si = di->si; 895 896 /* create the DMA command buffer area */ 897 //fixme? for R4.5 a workaround for cloning would be needed! 898 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 899 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 900 /* create the area that will hold the DMA command buffer */ 901 si->unaligned_dma_area = 902 create_area("NV DMA cmd buffer", 903 (void **)&unaligned_dma_buffer, 904 B_ANY_KERNEL_ADDRESS, 905 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 906 B_CONTIGUOUS, /* GPU always needs access */ 907 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 908 /* on error, abort */ 909 if (si->unaligned_dma_area < 0) 910 { 911 /* free the already created shared_info area, and return the error */ 912 result = si->unaligned_dma_area; 913 goto free_shared; 914 } 915 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 916 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 917 * even on older CPU's. */ 918 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 919 si->dma_buffer_pci = (void*) 920 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 921 922 /* map the net DMA command buffer into vmem, using Write Combining */ 923 si->dma_area = map_physical_memory( 924 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 925 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 926 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 927 /* if failed with write combining try again without */ 928 if (si->dma_area < 0) { 929 si->dma_area = map_physical_memory( 930 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 931 B_ANY_KERNEL_BLOCK_ADDRESS, 932 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 933 } 934 /* if there was an error, delete our other areas and pass on error*/ 935 if (si->dma_area < 0) 936 { 937 /* free the already created areas, and return the error */ 938 result = si->dma_area; 939 goto free_shared_and_uadma; 940 } 941 942 /* save the vendor and device IDs */ 943 si->vendor_id = di->pcii.vendor_id; 944 si->device_id = di->pcii.device_id; 945 si->revision = di->pcii.revision; 946 si->bus = di->pcii.bus; 947 si->device = di->pcii.device; 948 si->function = di->pcii.function; 949 950 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 951 si->accelerant_in_use = false; 952 /* preset singlehead card to prevent early INT routine calls (once installed) to 953 * wrongly identify the INT request coming from us! */ 954 si->ps.secondary_head = false; 955 956 /* map the device */ 957 result = map_device(di); 958 if (result < 0) goto free_shared_and_alldma; 959 960 /* we will be returning OK status for sure now */ 961 result = B_OK; 962 963 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 964 * unified memory architecture (UMA) */ 965 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 966 { 967 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 968 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 969 mem_size = 1024 * 1024 * 970 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 971 /* don't attempt to adress memory not mapped by the kerneldriver */ 972 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 973 /* last 64kB RAM is used for the BIOS (or something else?) */ 974 si->ps.memory_size -= (64 * 1024); 975 break; 976 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 977 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 978 mem_size = 1024 * 1024 * 979 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 980 /* don't attempt to adress memory not mapped by the kerneldriver */ 981 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 982 /* last 64kB RAM is used for the BIOS (or something else?) */ 983 si->ps.memory_size -= (64 * 1024); 984 break; 985 default: 986 /* all other cards have own RAM: the amount of which is determined in the 987 * accelerant. */ 988 break; 989 } 990 991 /* disable and clear any pending interrupts */ 992 //fixme: 993 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 994 disable_vbi_all(di->regs); 995 996 /* preset we can't use INT related functions */ 997 si->ps.int_assigned = false; 998 999 /* create a semaphore for vertical blank management */ 1000 si->vblank = create_sem(0, di->name); 1001 if (si->vblank < 0) goto mark_as_open; 1002 1003 /* change the owner of the semaphores to the opener's team */ 1004 /* this is required because apps can't aquire kernel semaphores */ 1005 thid = find_thread(NULL); 1006 get_thread_info(thid, &thinfo); 1007 set_sem_owner(si->vblank, thinfo.team); 1008 1009 /* If there is a valid interrupt line assigned then set up interrupts */ 1010 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1011 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1012 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1013 { 1014 /* delete the semaphore as it won't be used */ 1015 delete_sem(si->vblank); 1016 si->vblank = -1; 1017 } 1018 else 1019 { 1020 /* otherwise install our interrupt handler */ 1021 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1022 /* bail if we couldn't install the handler */ 1023 if (result != B_OK) 1024 { 1025 /* delete the semaphore as it won't be used */ 1026 delete_sem(si->vblank); 1027 si->vblank = -1; 1028 } 1029 else 1030 { 1031 /* inform accelerant(s) we can use INT related functions */ 1032 si->ps.int_assigned = true; 1033 } 1034 } 1035 1036 mark_as_open: 1037 /* mark the device open */ 1038 di->is_open++; 1039 1040 /* send the cookie to the opener */ 1041 *cookie = di; 1042 1043 goto done; 1044 1045 1046 free_shared_and_alldma: 1047 /* clean up our aligned DMA area */ 1048 delete_area(si->dma_area); 1049 si->dma_area = -1; 1050 si->dma_buffer = NULL; 1051 1052 free_shared_and_uadma: 1053 /* clean up our unaligned DMA area */ 1054 delete_area(si->unaligned_dma_area); 1055 si->unaligned_dma_area = -1; 1056 si->dma_buffer_pci = NULL; 1057 1058 free_shared: 1059 /* clean up our shared area */ 1060 delete_area(di->shared_area); 1061 di->shared_area = -1; 1062 di->si = NULL; 1063 1064 done: 1065 /* end of critical section */ 1066 RELEASE_BEN(pd->kernel); 1067 1068 /* all done, return the status */ 1069 return result; 1070 } 1071 1072 1073 static status_t 1074 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1075 { 1076 *len = 0; 1077 return B_NOT_ALLOWED; 1078 } 1079 1080 1081 static status_t 1082 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1083 { 1084 *len = 0; 1085 return B_NOT_ALLOWED; 1086 } 1087 1088 1089 static status_t 1090 close_hook(void* dev) 1091 { 1092 /* we don't do anything on close: there might be dup'd fd */ 1093 return B_NO_ERROR; 1094 } 1095 1096 1097 static status_t 1098 free_hook(void* dev) 1099 { 1100 device_info *di = (device_info *)dev; 1101 shared_info *si = di->si; 1102 vuint32 *regs = di->regs; 1103 1104 /* lock the driver */ 1105 AQUIRE_BEN(pd->kernel); 1106 1107 /* if opened multiple times, decrement the open count and exit */ 1108 if (di->is_open > 1) 1109 goto unlock_and_exit; 1110 1111 /* disable and clear any pending interrupts */ 1112 //fixme: 1113 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1114 disable_vbi_all(regs); 1115 1116 if (si->ps.int_assigned) { 1117 /* remove interrupt handler */ 1118 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1119 1120 /* delete the semaphores, ignoring any errors ('cause the owning 1121 team may have died on us) */ 1122 delete_sem(si->vblank); 1123 si->vblank = -1; 1124 } 1125 1126 /* free regs and framebuffer areas */ 1127 unmap_device(di); 1128 1129 /* clean up our aligned DMA area */ 1130 delete_area(si->dma_area); 1131 si->dma_area = -1; 1132 si->dma_buffer = NULL; 1133 1134 /* clean up our unaligned DMA area */ 1135 delete_area(si->unaligned_dma_area); 1136 si->unaligned_dma_area = -1; 1137 si->dma_buffer_pci = NULL; 1138 1139 /* clean up our shared area */ 1140 delete_area(di->shared_area); 1141 di->shared_area = -1; 1142 di->si = NULL; 1143 1144 unlock_and_exit: 1145 /* mark the device available */ 1146 di->is_open--; 1147 /* unlock the driver */ 1148 RELEASE_BEN(pd->kernel); 1149 /* all done */ 1150 return B_OK; 1151 } 1152 1153 1154 static status_t 1155 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1156 { 1157 device_info *di = (device_info *)dev; 1158 status_t result = B_DEV_INVALID_IOCTL; 1159 uint32 tmpUlong; 1160 1161 switch (msg) { 1162 /* the only PUBLIC ioctl */ 1163 case B_GET_ACCELERANT_SIGNATURE: 1164 { 1165 strcpy((char* )buf, sSettings.accelerant); 1166 result = B_OK; 1167 break; 1168 } 1169 1170 /* PRIVATE ioctl from here on */ 1171 case NV_GET_PRIVATE_DATA: 1172 { 1173 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1174 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1175 gpd->shared_info_area = di->shared_area; 1176 result = B_OK; 1177 } 1178 break; 1179 } 1180 1181 case NV_GET_PCI: 1182 { 1183 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1184 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1185 pci_info *pcii = &(di->pcii); 1186 gsp->value = get_pci(gsp->offset, gsp->size); 1187 result = B_OK; 1188 } 1189 break; 1190 } 1191 1192 case NV_SET_PCI: 1193 { 1194 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1195 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1196 pci_info *pcii = &(di->pcii); 1197 set_pci(gsp->offset, gsp->size, gsp->value); 1198 result = B_OK; 1199 } 1200 break; 1201 } 1202 1203 case NV_DEVICE_NAME: 1204 { 1205 nv_device_name *dn = (nv_device_name *)buf; 1206 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1207 strcpy(dn->name, di->name); 1208 result = B_OK; 1209 } 1210 break; 1211 } 1212 1213 case NV_RUN_INTERRUPTS: 1214 { 1215 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1216 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1217 vuint32 *regs = di->regs; 1218 if (!(vi->crtc)) { 1219 if (vi->do_it) { 1220 enable_vbi_crtc1(regs); 1221 } else { 1222 disable_vbi_crtc1(regs); 1223 } 1224 } else { 1225 if (vi->do_it) { 1226 enable_vbi_crtc2(regs); 1227 } else { 1228 disable_vbi_crtc2(regs); 1229 } 1230 } 1231 result = B_OK; 1232 } 1233 break; 1234 } 1235 1236 case NV_GET_NTH_AGP_INFO: 1237 { 1238 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1239 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1240 nai->exist = false; 1241 nai->agp_bus = false; 1242 if (agp_bus) { 1243 nai->agp_bus = true; 1244 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1245 nai->exist = true; 1246 } 1247 } 1248 result = B_OK; 1249 } 1250 break; 1251 } 1252 1253 case NV_ENABLE_AGP: 1254 { 1255 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1256 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1257 if (agp_bus) { 1258 nca->agp_bus = true; 1259 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1260 } else { 1261 nca->agp_bus = false; 1262 nca->cmd = 0; 1263 } 1264 result = B_OK; 1265 } 1266 break; 1267 } 1268 1269 case NV_ISA_OUT: 1270 { 1271 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1272 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1273 pci_info *pcii = &(di->pcii); 1274 1275 /* lock the driver: 1276 * no other graphics card may have ISA I/O enabled when we enter */ 1277 AQUIRE_BEN(pd->kernel); 1278 1279 /* enable ISA I/O access */ 1280 tmpUlong = get_pci(PCI_command, 2); 1281 tmpUlong |= PCI_command_io; 1282 set_pci(PCI_command, 2, tmpUlong); 1283 1284 if (io_isa->size == 1) 1285 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1286 else 1287 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1288 result = B_OK; 1289 1290 /* disable ISA I/O access */ 1291 tmpUlong = get_pci(PCI_command, 2); 1292 tmpUlong &= ~PCI_command_io; 1293 set_pci(PCI_command, 2, tmpUlong); 1294 1295 /* end of critical section */ 1296 RELEASE_BEN(pd->kernel); 1297 } 1298 break; 1299 } 1300 1301 case NV_ISA_IN: 1302 { 1303 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1304 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1305 pci_info *pcii = &(di->pcii); 1306 1307 /* lock the driver: 1308 * no other graphics card may have ISA I/O enabled when we enter */ 1309 AQUIRE_BEN(pd->kernel); 1310 1311 /* enable ISA I/O access */ 1312 tmpUlong = get_pci(PCI_command, 2); 1313 tmpUlong |= PCI_command_io; 1314 set_pci(PCI_command, 2, tmpUlong); 1315 1316 if (io_isa->size == 1) 1317 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1318 else 1319 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1320 result = B_OK; 1321 1322 /* disable ISA I/O access */ 1323 tmpUlong = get_pci(PCI_command, 2); 1324 tmpUlong &= ~PCI_command_io; 1325 set_pci(PCI_command, 2, tmpUlong); 1326 1327 /* end of critical section */ 1328 RELEASE_BEN(pd->kernel); 1329 } 1330 break; 1331 } 1332 } 1333 1334 return result; 1335 } 1336 1337 1338 // #pragma mark - driver API 1339 1340 1341 status_t 1342 init_hardware(void) 1343 { 1344 long index = 0; 1345 pci_info pcii; 1346 bool found = false; 1347 1348 /* choke if we can't find the PCI bus */ 1349 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1350 return B_ERROR; 1351 1352 /* choke if we can't find the ISA bus */ 1353 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1354 { 1355 put_module(B_PCI_MODULE_NAME); 1356 return B_ERROR; 1357 } 1358 1359 /* while there are more pci devices */ 1360 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1361 int vendor = 0; 1362 1363 /* if we match a supported vendor */ 1364 while (SupportedDevices[vendor].vendor) { 1365 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1366 uint16 *devices = SupportedDevices[vendor].devices; 1367 /* while there are more supported devices */ 1368 while (*devices) { 1369 /* if we match a supported device */ 1370 if (*devices == pcii.device_id ) { 1371 1372 found = true; 1373 goto done; 1374 } 1375 /* next supported device */ 1376 devices++; 1377 } 1378 } 1379 vendor++; 1380 } 1381 /* next pci_info struct, please */ 1382 index++; 1383 } 1384 1385 done: 1386 /* put away the module manager */ 1387 put_module(B_PCI_MODULE_NAME); 1388 return found ? B_OK : B_ERROR; 1389 } 1390 1391 1392 status_t 1393 init_driver(void) 1394 { 1395 void *settings; 1396 1397 // get driver/accelerant settings 1398 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1399 if (settings != NULL) { 1400 const char *item; 1401 char *end; 1402 uint32 value; 1403 1404 // for driver 1405 item = get_driver_parameter(settings, "accelerant", "", ""); 1406 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1407 strcpy (sSettings.accelerant, item); 1408 1409 item = get_driver_parameter(settings, "primary", "", ""); 1410 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1411 strcpy(sSettings.primary, item); 1412 1413 sSettings.dumprom = get_driver_boolean_parameter(settings, 1414 "dumprom", false, false); 1415 1416 // for accelerant 1417 item = get_driver_parameter(settings, "logmask", 1418 "0x00000000", "0x00000000"); 1419 value = strtoul(item, &end, 0); 1420 if (*end == '\0') 1421 sSettings.logmask = value; 1422 1423 item = get_driver_parameter(settings, "memory", "0", "0"); 1424 value = strtoul(item, &end, 0); 1425 if (*end == '\0') 1426 sSettings.memory = value; 1427 1428 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1429 value = strtoul(item, &end, 0); 1430 if (*end == '\0') 1431 sSettings.tv_output = value; 1432 1433 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1434 "hardcursor", true, true); 1435 sSettings.usebios = get_driver_boolean_parameter(settings, 1436 "usebios", true, true); 1437 sSettings.switchhead = get_driver_boolean_parameter(settings, 1438 "switchhead", false, false); 1439 sSettings.force_pci = get_driver_boolean_parameter(settings, 1440 "force_pci", false, false); 1441 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1442 "unhide_fw", false, false); 1443 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1444 "pgm_panel", false, false); 1445 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1446 "dma_acc", true, true); 1447 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1448 "vga_on_tv", false, false); 1449 sSettings.force_sync = get_driver_boolean_parameter(settings, 1450 "force_sync", false, false); 1451 sSettings.force_ws = get_driver_boolean_parameter(settings, 1452 "force_ws", false, false); 1453 sSettings.block_acc = get_driver_boolean_parameter(settings, 1454 "block_acc", false, false); 1455 1456 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1457 value = strtoul(item, &end, 0); 1458 if (*end == '\0') 1459 sSettings.gpu_clk = value; 1460 1461 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1462 value = strtoul(item, &end, 0); 1463 if (*end == '\0') 1464 sSettings.ram_clk = value; 1465 1466 unload_driver_settings(settings); 1467 } 1468 1469 /* get a handle for the pci bus */ 1470 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1471 return B_ERROR; 1472 1473 /* get a handle for the isa bus */ 1474 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1475 put_module(B_PCI_MODULE_NAME); 1476 return B_ERROR; 1477 } 1478 1479 /* get a handle for the agp bus if it exists */ 1480 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1481 1482 /* driver private data */ 1483 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1484 if (!pd) { 1485 put_module(B_PCI_MODULE_NAME); 1486 return B_ERROR; 1487 } 1488 /* initialize the benaphore */ 1489 INIT_BEN(pd->kernel); 1490 /* find all of our supported devices */ 1491 probe_devices(); 1492 return B_OK; 1493 } 1494 1495 1496 const char ** 1497 publish_devices(void) 1498 { 1499 /* return the list of supported devices */ 1500 return (const char **)pd->device_names; 1501 } 1502 1503 1504 device_hooks * 1505 find_device(const char *name) 1506 { 1507 int index = 0; 1508 while (pd->device_names[index]) { 1509 if (strcmp(name, pd->device_names[index]) == 0) 1510 return &graphics_device_hooks; 1511 index++; 1512 } 1513 return NULL; 1514 1515 } 1516 1517 1518 void 1519 uninit_driver(void) 1520 { 1521 /* free the driver data */ 1522 DELETE_BEN(pd->kernel); 1523 free(pd); 1524 pd = NULL; 1525 1526 /* put the pci module away */ 1527 put_module(B_PCI_MODULE_NAME); 1528 put_module(B_ISA_MODULE_NAME); 1529 1530 /* put the agp module away if it's there */ 1531 if (agp_bus) 1532 put_module(B_AGP_GART_MODULE_NAME); 1533 } 1534 1535