1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-10/2005. 8 */ 9 10 /* standard kernel driver stuff */ 11 #include <KernelExport.h> 12 #include <ISA.h> 13 #include <PCI.h> 14 #include <OS.h> 15 #include <driver_settings.h> 16 #include <malloc.h> 17 #include <stdlib.h> // for strtoXX 18 #include "AGP.h" 19 20 /* this is for the standardized portion of the driver API */ 21 /* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ 22 #include <graphic_driver.h> 23 24 /* this is for sprintf() */ 25 #include <stdio.h> 26 27 /* this is for string compares */ 28 #include <string.h> 29 30 /* The private interface between the accelerant and the kernel driver. */ 31 #include "DriverInterface.h" 32 #include "nv_macros.h" 33 34 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 35 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 36 37 #define MAX_DEVICES 8 38 39 #ifndef __HAIKU__ 40 # undef B_USER_CLONEABLE_AREA 41 # define B_USER_CLONEABLE_AREA 0 42 #endif 43 44 #define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed 45 46 /* Tell the kernel what revision of the driver API we support */ 47 int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 48 49 /* these structures are private to the kernel driver */ 50 typedef struct device_info device_info; 51 52 typedef struct { 53 timer te; /* timer entry for add_timer() */ 54 device_info *di; /* pointer to the owning device */ 55 bigtime_t when_target; /* when we're supposed to wake up */ 56 } timer_info; 57 58 struct device_info { 59 uint32 is_open; /* a count of how many times the devices has been opened */ 60 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 61 shared_info *si; /* a pointer to the shared area, for convenience */ 62 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 63 pci_info pcii; /* a convenience copy of the pci info for this device */ 64 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 65 }; 66 67 typedef struct { 68 uint32 count; /* number of devices actually found */ 69 benaphore kernel; /* for serializing opens/closes */ 70 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 71 device_info di[MAX_DEVICES]; /* device specific stuff */ 72 } DeviceData; 73 74 /* prototypes for our private functions */ 75 static status_t open_hook (const char* name, uint32 flags, void** cookie); 76 static status_t close_hook (void* dev); 77 static status_t free_hook (void* dev); 78 static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); 79 static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); 80 static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); 81 static status_t map_device(device_info *di); 82 static void unmap_device(device_info *di); 83 static void probe_devices(void); 84 static int32 nv_interrupt(void *data); 85 86 static DeviceData *pd; 87 static isa_module_info *isa_bus = NULL; 88 static pci_module_info *pci_bus = NULL; 89 static agp_module_info *agp_bus = NULL; 90 static device_hooks graphics_device_hooks = { 91 open_hook, 92 close_hook, 93 free_hook, 94 control_hook, 95 read_hook, 96 write_hook, 97 NULL, 98 NULL, 99 NULL, 100 NULL 101 }; 102 103 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 104 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 105 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 106 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 107 108 static uint16 nvidia_device_list[] = { 109 0x0020, /* Nvidia TNT1 */ 110 0x0028, /* Nvidia TNT2 (pro) */ 111 0x0029, /* Nvidia TNT2 Ultra */ 112 0x002a, /* Nvidia TNT2 */ 113 0x002b, /* Nvidia TNT2 */ 114 0x002c, /* Nvidia Vanta (Lt) */ 115 0x002d, /* Nvidia TNT2-M64 (Pro) */ 116 0x002e, /* Nvidia NV06 Vanta */ 117 0x002f, /* Nvidia NV06 Vanta */ 118 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 119 0x0041, /* Nvidia GeForce FX 6800 */ 120 0x0042, /* Nvidia GeForce FX 6800LE */ 121 0x0043, /* Nvidia unknown FX */ 122 0x0045, /* Nvidia GeForce FX 6800 GT */ 123 0x004d, /* Nvidia Quadro FX 4400 */ 124 0x004e, /* Nvidia Quadro FX 4000 */ 125 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 126 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 127 0x00a0, /* Nvidia Aladdin TNT2 */ 128 0x00c0, /* Nvidia unknown FX */ 129 0x00c1, /* Nvidia GeForce FX 6800 */ 130 0x00c2, /* Nvidia GeForce FX 6800LE */ 131 0x00c8, /* Nvidia GeForce FX 6800 Go */ 132 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 133 0x00cc, /* Nvidia Quadro FX 1400 Go */ 134 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 135 0x00ce, /* Nvidia Quadro FX 1400 */ 136 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 137 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 138 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 139 0x00f3, /* Nvidia GeForce 6200 */ 140 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 141 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 142 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 143 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 144 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 145 0x00fd, /* Nvidia Quadro PCX PCIe */ 146 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 147 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 148 0x0100, /* Nvidia GeForce256 SDR */ 149 0x0101, /* Nvidia GeForce256 DDR */ 150 0x0102, /* Nvidia GeForce256 Ultra */ 151 0x0103, /* Nvidia Quadro */ 152 0x0110, /* Nvidia GeForce2 MX/MX400 */ 153 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 154 0x0112, /* Nvidia GeForce2 Go */ 155 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 156 0x0140, /* Nvidia GeForce FX 6600 GT */ 157 0x0141, /* Nvidia GeForce FX 6600 */ 158 0x0144, /* Nvidia GeForce FX 6600 Go */ 159 0x0145, /* Nvidia GeForce FX 6610 XL */ 160 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 161 0x0148, /* Nvidia GeForce FX 6600 Go */ 162 0x014e, /* Nvidia Quadro FX 540 */ 163 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 164 0x0150, /* Nvidia GeForce2 GTS/Pro */ 165 0x0151, /* Nvidia GeForce2 Ti DDR */ 166 0x0152, /* Nvidia GeForce2 Ultra */ 167 0x0153, /* Nvidia Quadro2 Pro */ 168 0x0160, /* Nvidia GeForce 6500 Go */ 169 0x0161, /* Nvidia GeForce 6200 TurboCache */ 170 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 171 0x0163, /* Nvidia GeForce 6200LE */ 172 0x0164, /* Nvidia GeForce FX 6200 Go */ 173 0x0165, /* Nvidia Quadro FX NVS 285 */ 174 0x0166, /* Nvidia GeForce 6400 Go */ 175 0x0167, /* Nvidia GeForce 6200 Go */ 176 0x0168, /* Nvidia GeForce 6400 Go */ 177 0x0169, /* Nvidia GeForce 6250 Go */ 178 0x016e, /* Nvidia unknown FX */ 179 0x0170, /* Nvidia GeForce4 MX 460 */ 180 0x0171, /* Nvidia GeForce4 MX 440 */ 181 0x0172, /* Nvidia GeForce4 MX 420 */ 182 0x0173, /* Nvidia GeForce4 MX 440SE */ 183 0x0174, /* Nvidia GeForce4 440 Go */ 184 0x0175, /* Nvidia GeForce4 420 Go */ 185 0x0176, /* Nvidia GeForce4 420 Go 32M */ 186 0x0177, /* Nvidia GeForce4 460 Go */ 187 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 188 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 189 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 190 0x017c, /* Nvidia Quadro4 500 GoGL */ 191 0x017d, /* Nvidia GeForce4 410 Go 16M */ 192 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 193 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 194 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 195 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 196 0x0186, /* Nvidia GeForce4 448 Go */ 197 0x0187, /* Nvidia GeForce4 488 Go */ 198 0x0188, /* Nvidia Quadro4 580 XGL */ 199 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 200 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 201 0x018b, /* Nvidia Quadro4 380 XGL */ 202 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 203 0x018d, /* Nvidia GeForce4 448 Go */ 204 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 205 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 206 0x0200, /* Nvidia GeForce3 */ 207 0x0201, /* Nvidia GeForce3 Ti 200 */ 208 0x0202, /* Nvidia GeForce3 Ti 500 */ 209 0x0203, /* Nvidia Quadro DCC */ 210 0x0211, /* Nvidia GeForce FX 6800 */ 211 0x0212, /* Nvidia GeForce FX 6800LE */ 212 0x0215, /* Nvidia GeForce FX 6800 GT */ 213 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 214 0x0250, /* Nvidia GeForce4 Ti 4600 */ 215 0x0251, /* Nvidia GeForce4 Ti 4400 */ 216 0x0252, /* Nvidia GeForce4 Ti 4600 */ 217 0x0253, /* Nvidia GeForce4 Ti 4200 */ 218 0x0258, /* Nvidia Quadro4 900 XGL */ 219 0x0259, /* Nvidia Quadro4 750 XGL */ 220 0x025b, /* Nvidia Quadro4 700 XGL */ 221 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 222 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 223 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 224 0x0286, /* Nvidia GeForce4 4200 Go */ 225 0x0288, /* Nvidia Quadro4 980 XGL */ 226 0x0289, /* Nvidia Quadro4 780 XGL */ 227 0x028c, /* Nvidia Quadro4 700 GoGL */ 228 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 229 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 230 0x0302, /* Nvidia GeForce FX 5800 */ 231 0x0308, /* Nvidia Quadro FX 2000 */ 232 0x0309, /* Nvidia Quadro FX 1000 */ 233 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 234 0x0312, /* Nvidia GeForce FX 5600 */ 235 0x0313, /* Nvidia unknown FX */ 236 0x0314, /* Nvidia GeForce FX 5600XT */ 237 0x0316, /* Nvidia unknown FX Go */ 238 0x0317, /* Nvidia unknown FX Go */ 239 0x031a, /* Nvidia GeForce FX 5600 Go */ 240 0x031b, /* Nvidia GeForce FX 5650 Go */ 241 0x031c, /* Nvidia Quadro FX 700 Go */ 242 0x031d, /* Nvidia unknown FX Go */ 243 0x031e, /* Nvidia unknown FX Go */ 244 0x031f, /* Nvidia unknown FX Go */ 245 0x0320, /* Nvidia GeForce FX 5200 */ 246 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 247 0x0322, /* Nvidia GeForce FX 5200 */ 248 0x0323, /* Nvidia GeForce FX 5200LE */ 249 0x0324, /* Nvidia GeForce FX 5200 Go */ 250 0x0325, /* Nvidia GeForce FX 5250 Go */ 251 0x0326, /* Nvidia GeForce FX 5500 */ 252 0x0327, /* Nvidia GeForce FX 5100 */ 253 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 254 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 255 0x032a, /* Nvidia Quadro NVS 280 PCI */ 256 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 257 0x032c, /* Nvidia GeForce FX 5300 Go */ 258 0x032d, /* Nvidia GeForce FX 5100 Go */ 259 0x032e, /* Nvidia unknown FX Go */ 260 0x032f, /* Nvidia unknown FX Go */ 261 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 262 0x0331, /* Nvidia GeForce FX 5900 */ 263 0x0332, /* Nvidia GeForce FX 5900 XT */ 264 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 265 0x0334, /* Nvidia GeForce FX 5900 ZT */ 266 0x0338, /* Nvidia Quadro FX 3000 */ 267 0x033f, /* Nvidia Quadro FX 700 */ 268 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 269 0x0342, /* Nvidia GeForce FX 5700 */ 270 0x0343, /* Nvidia GeForce FX 5700LE */ 271 0x0344, /* Nvidia GeForce FX 5700VE */ 272 0x0347, /* Nvidia GeForce FX 5700 Go */ 273 0x0348, /* Nvidia GeForce FX 5700 Go */ 274 0x034c, /* Nvidia Quadro FX 1000 Go */ 275 0x034e, /* Nvidia Quadro FX 1100 */ 276 0x034f, /* Nvidia unknown FX */ 277 0 278 }; 279 /* 280 not yet included nVidia ID's that are unknown, but used according to nvidia: 281 0x0049 //nv40 282 0x0098 // go >>> now known, setup 283 0x0142 //nv43 >>> now known, setup 284 0x0143 //nv43 285 0x0147 //nv43 >>> now known, setup 286 0x0149 //nv43 >>> now known, setup 287 0x014b //nv43 288 0x014c //nv43 289 0x014d //nv43 290 0x016b //nv44 go 291 0x016c //nv44 go 292 0x016d //nv44 go 293 0x0210 //nv48 >>> checkout nv# 294 0x021d //nv48 (existing? not in nvidia list) 295 0x021e //nv48 (existing? not in nvidia list) 296 0x0220 //nv44 297 0x0222 //nv44 298 0x0228 //nv44 go 299 0x0329 // go 300 0x0345 //nv36 301 0x0349 //nv36 go 302 0x034b //nv36 go. 303 */ 304 305 static uint16 elsa_device_list[] = { 306 0x0c60, /* Elsa Gladiac Geforce2 MX */ 307 0 308 }; 309 310 static uint16 nvstbsgs_device_list[] = { 311 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 312 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 313 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 314 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 315 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 316 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 317 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 318 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 319 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 320 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 321 0 322 }; 323 324 static uint16 varisys_device_list[] = { 325 0x3503, /* Varisys GeForce4 MX440 */ 326 0x3505, /* Varisys GeForce4 Ti 4200 */ 327 0 328 }; 329 330 static struct { 331 uint16 vendor; 332 uint16 *devices; 333 } SupportedDevices[] = { 334 {VENDOR_ID_NVIDIA, nvidia_device_list}, 335 {VENDOR_ID_ELSA, elsa_device_list}, 336 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 337 {VENDOR_ID_VARISYS, varisys_device_list}, 338 {0x0000, NULL} 339 }; 340 341 static nv_settings current_settings = { // see comments in nv.settings 342 // for driver 343 DRIVER_PREFIX ".accelerant", 344 false, // dumprom 345 // for accelerant 346 0x00000000, // logmask 347 0, // memory 348 0, // tv_output 349 true, // usebios 350 true, // hardcursor 351 false, // switchhead 352 false, // force_pci 353 false, // unhide_fw 354 true, // pgm_panel 355 true, // dma_acc 356 false, // vga_on_tv 357 }; 358 359 static void dumprom (void *rom, uint32 size) 360 { 361 int fd; 362 uint32 cnt; 363 364 fd = open ("/boot/home/" DRIVER_PREFIX ".rom", O_WRONLY | O_CREAT, 0666); 365 if (fd < 0) return; 366 367 /* apparantly max. 32kb may be written at once; 368 * the ROM size is a multiple of that anyway. */ 369 for (cnt = 0; (cnt < size); cnt += 32768) 370 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 371 close (fd); 372 } 373 374 /* return 1 if vblank interrupt has occured */ 375 static int caused_vbi(vuint32 * regs) 376 { 377 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 378 } 379 380 /* clear the vblank interrupt */ 381 static void clear_vbi(vuint32 * regs) 382 { 383 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 384 } 385 386 static void enable_vbi(vuint32 * regs) 387 { 388 /* clear the vblank interrupt */ 389 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 390 /* enable nVidia interrupt source vblank */ 391 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 392 /* enable nVidia interrupt system hardware (b0-1) */ 393 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 394 } 395 396 static void disable_vbi(vuint32 * regs) 397 { 398 /* disable nVidia interrupt source vblank */ 399 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 400 /* clear the vblank interrupt */ 401 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 402 /* disable nVidia interrupt system hardware (b0-1) */ 403 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 404 } 405 406 /* 407 init_hardware() - Returns B_OK if one is 408 found, otherwise returns B_ERROR so the driver will be unloaded. 409 */ 410 status_t 411 init_hardware(void) { 412 long pci_index = 0; 413 pci_info pcii; 414 bool found_one = false; 415 416 /* choke if we can't find the PCI bus */ 417 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 418 return B_ERROR; 419 420 /* choke if we can't find the ISA bus */ 421 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 422 { 423 put_module(B_PCI_MODULE_NAME); 424 return B_ERROR; 425 } 426 427 /* while there are more pci devices */ 428 while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { 429 int vendor = 0; 430 431 /* if we match a supported vendor */ 432 while (SupportedDevices[vendor].vendor) { 433 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 434 uint16 *devices = SupportedDevices[vendor].devices; 435 /* while there are more supported devices */ 436 while (*devices) { 437 /* if we match a supported device */ 438 if (*devices == pcii.device_id ) { 439 440 found_one = true; 441 goto done; 442 } 443 /* next supported device */ 444 devices++; 445 } 446 } 447 vendor++; 448 } 449 /* next pci_info struct, please */ 450 pci_index++; 451 } 452 453 done: 454 /* put away the module manager */ 455 put_module(B_PCI_MODULE_NAME); 456 return (found_one ? B_OK : B_ERROR); 457 } 458 459 status_t 460 init_driver(void) { 461 void *settings_handle; 462 463 // get driver/accelerant settings, apsed 464 settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); 465 if (settings_handle != NULL) { 466 const char *item; 467 char *end; 468 uint32 value; 469 470 // for driver 471 item = get_driver_parameter (settings_handle, "accelerant", "", ""); 472 if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { 473 strcpy (current_settings.accelerant, item); 474 } 475 current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); 476 477 // for accelerant 478 item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); 479 value = strtoul (item, &end, 0); 480 if (*end == '\0') current_settings.logmask = value; 481 482 item = get_driver_parameter (settings_handle, "memory", "0", "0"); 483 value = strtoul (item, &end, 0); 484 if (*end == '\0') current_settings.memory = value; 485 486 item = get_driver_parameter (settings_handle, "tv_output", "0", "0"); 487 value = strtoul (item, &end, 0); 488 if (*end == '\0') current_settings.tv_output = value; 489 490 current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); 491 current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); 492 current_settings.switchhead = get_driver_boolean_parameter (settings_handle, "switchhead", false, false); 493 current_settings.force_pci = get_driver_boolean_parameter (settings_handle, "force_pci", false, false); 494 current_settings.unhide_fw = get_driver_boolean_parameter (settings_handle, "unhide_fw", false, false); 495 current_settings.pgm_panel = get_driver_boolean_parameter (settings_handle, "pgm_panel", false, false); 496 current_settings.dma_acc = get_driver_boolean_parameter (settings_handle, "dma_acc", false, false); 497 current_settings.vga_on_tv = get_driver_boolean_parameter (settings_handle, "vga_on_tv", false, false); 498 499 unload_driver_settings (settings_handle); 500 } 501 502 /* get a handle for the pci bus */ 503 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 504 return B_ERROR; 505 506 /* get a handle for the isa bus */ 507 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 508 { 509 put_module(B_PCI_MODULE_NAME); 510 return B_ERROR; 511 } 512 513 /* get a handle for the agp bus if it exists */ 514 get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus); 515 516 /* driver private data */ 517 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 518 if (!pd) { 519 put_module(B_PCI_MODULE_NAME); 520 return B_ERROR; 521 } 522 /* initialize the benaphore */ 523 INIT_BEN(pd->kernel); 524 /* find all of our supported devices */ 525 probe_devices(); 526 return B_OK; 527 } 528 529 const char ** 530 publish_devices(void) { 531 /* return the list of supported devices */ 532 return (const char **)pd->device_names; 533 } 534 535 device_hooks * 536 find_device(const char *name) { 537 int index = 0; 538 while (pd->device_names[index]) { 539 if (strcmp(name, pd->device_names[index]) == 0) 540 return &graphics_device_hooks; 541 index++; 542 } 543 return NULL; 544 545 } 546 547 void uninit_driver(void) { 548 549 /* free the driver data */ 550 DELETE_BEN(pd->kernel); 551 free(pd); 552 pd = NULL; 553 554 /* put the pci module away */ 555 put_module(B_PCI_MODULE_NAME); 556 put_module(B_ISA_MODULE_NAME); 557 558 /* put the agp module away if it's there */ 559 if (agp_bus) put_module(B_AGP_MODULE_NAME); 560 } 561 562 static status_t map_device(device_info *di) 563 { 564 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 565 shared_info *si = di->si; 566 uint32 tmpUlong; 567 pci_info *pcii = &(di->pcii); 568 system_info sysinfo; 569 570 /*storage for the physical to virtual table (used for dma buffer)*/ 571 // physical_entry physical_memory[2]; 572 // #define G400_DMA_BUFFER_SIZE 1024*1024 573 574 /* variables for making copy of ROM */ 575 uint8* rom_temp; 576 area_id rom_area; 577 578 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 579 int registers = 0; 580 int frame_buffer = 1; 581 // int pseudo_dma = 2; 582 583 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 584 tmpUlong = get_pci(PCI_command, 2); 585 /* enable PCI access */ 586 tmpUlong |= PCI_command_memory; 587 /* enable busmastering */ 588 tmpUlong |= PCI_command_master; 589 /* disable ISA I/O access */ 590 tmpUlong &= ~PCI_command_io; 591 set_pci(PCI_command, 2, tmpUlong); 592 593 /*work out which version of BeOS is running*/ 594 get_system_info(&sysinfo); 595 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 596 { 597 si->use_clone_bugfix = 1; 598 } 599 else 600 { 601 si->use_clone_bugfix = 0; 602 } 603 604 /* work out a name for the register mapping */ 605 sprintf(buffer, DEVICE_FORMAT " regs", 606 di->pcii.vendor_id, di->pcii.device_id, 607 di->pcii.bus, di->pcii.device, di->pcii.function); 608 609 /* get a virtual memory address for the registers*/ 610 si->regs_area = map_physical_memory( 611 buffer, 612 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 613 (void *) di->pcii.u.h0.base_registers_pci[registers], 614 di->pcii.u.h0.base_register_sizes[registers], 615 B_ANY_KERNEL_ADDRESS, 616 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 617 (void **)&(di->regs)); 618 si->clone_bugfix_regs = (uint32 *) di->regs; 619 620 /* if mapping registers to vmem failed then pass on error */ 621 if (si->regs_area < 0) return si->regs_area; 622 623 /* work out a name for the ROM mapping*/ 624 sprintf(buffer, DEVICE_FORMAT " rom", 625 di->pcii.vendor_id, di->pcii.device_id, 626 di->pcii.bus, di->pcii.device, di->pcii.function); 627 628 /* disable ROM shadowing, we want the guaranteed exact contents of the chip */ 629 /* warning: 630 * don't touch: (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 631 * NV18, NV28 and NV34 keep working. 632 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 633 * however the actual ROM content (so the used part) is intact (confirmed). */ 634 //set_pci(NVCFG_ROMSHADOW, 4, 0); 635 636 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 637 tmpUlong = get_pci(PCI_rom_base, 4); 638 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 639 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 640 //legacy space will get us into trouble if we aren't the primary graphics card!! 641 //(as legacy space always has the primary card's ROM 'mapped'!) 642 if (tmpUlong) 643 { 644 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 645 tmpUlong |= 0x00000001; 646 set_pci(PCI_rom_base, 4, tmpUlong); 647 648 rom_area = map_physical_memory( 649 buffer, 650 (void *)di->pcii.u.h0.rom_base_pci, 651 di->pcii.u.h0.rom_size, 652 B_ANY_KERNEL_ADDRESS, 653 B_READ_AREA, 654 (void **)&(rom_temp) 655 ); 656 657 /* check if we got the BIOS signature (might fail on laptops..) */ 658 if (rom_temp[0]!=0x55 || rom_temp[1]!=0xaa) 659 { 660 /* apparantly no ROM is mapped here */ 661 delete_area(rom_area); 662 rom_area = -1; 663 /* force using ISA legacy map as fall-back */ 664 tmpUlong = 0x00000000; 665 } 666 } 667 668 if (!tmpUlong) 669 { 670 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 671 rom_area = map_physical_memory( 672 buffer, 673 (void *)0x000c0000, 674 65536, 675 B_ANY_KERNEL_ADDRESS, 676 B_READ_AREA, 677 (void **)&(rom_temp) 678 ); 679 } 680 681 /* if mapping ROM to vmem failed then clean up and pass on error */ 682 if (rom_area < 0) { 683 delete_area(si->regs_area); 684 si->regs_area = -1; 685 return rom_area; 686 } 687 688 /* dump ROM to file if selected in nv.settings 689 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 690 if (current_settings.dumprom) dumprom (rom_temp, 65536); 691 /* make a copy of ROM for future reference */ 692 memcpy (si->rom_mirror, rom_temp, 65536); 693 694 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 695 tmpUlong = get_pci(PCI_rom_base, 4); 696 tmpUlong &= 0xfffffffe; 697 set_pci(PCI_rom_base, 4, tmpUlong); 698 delete_area(rom_area); 699 700 /* work out a name for the framebuffer mapping*/ 701 sprintf(buffer, DEVICE_FORMAT " framebuffer", 702 di->pcii.vendor_id, di->pcii.device_id, 703 di->pcii.bus, di->pcii.device, di->pcii.function); 704 705 /* map the framebuffer into vmem, using Write Combining*/ 706 si->fb_area = map_physical_memory( 707 buffer, 708 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 709 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 710 di->pcii.u.h0.base_register_sizes[frame_buffer], 711 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 712 B_READ_AREA | B_WRITE_AREA, 713 &(si->framebuffer)); 714 715 /*if failed with write combining try again without*/ 716 if (si->fb_area < 0) { 717 si->fb_area = map_physical_memory( 718 buffer, 719 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 720 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 721 di->pcii.u.h0.base_register_sizes[frame_buffer], 722 B_ANY_KERNEL_BLOCK_ADDRESS, 723 B_READ_AREA | B_WRITE_AREA, 724 &(si->framebuffer)); 725 } 726 727 /* if there was an error, delete our other areas and pass on error*/ 728 if (si->fb_area < 0) 729 { 730 delete_area(si->regs_area); 731 si->regs_area = -1; 732 return si->fb_area; 733 } 734 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 735 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 736 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 737 738 // remember settings for use here and in accelerant 739 si->settings = current_settings; 740 741 /* in any case, return the result */ 742 return si->fb_area; 743 } 744 745 static void unmap_device(device_info *di) { 746 shared_info *si = di->si; 747 uint32 tmpUlong; 748 pci_info *pcii = &(di->pcii); 749 750 /* disable memory mapped IO */ 751 tmpUlong = get_pci(PCI_command, 4); 752 tmpUlong &= 0xfffffffc; 753 set_pci(PCI_command, 4, tmpUlong); 754 /* delete the areas */ 755 if (si->regs_area >= 0) delete_area(si->regs_area); 756 if (si->fb_area >= 0) delete_area(si->fb_area); 757 si->regs_area = si->fb_area = -1; 758 si->framebuffer = NULL; 759 di->regs = NULL; 760 } 761 762 static void probe_devices(void) { 763 uint32 pci_index = 0; 764 uint32 count = 0; 765 device_info *di = pd->di; 766 767 /* while there are more pci devices */ 768 while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { 769 int vendor = 0; 770 771 /* if we match a supported vendor */ 772 while (SupportedDevices[vendor].vendor) { 773 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 774 uint16 *devices = SupportedDevices[vendor].devices; 775 /* while there are more supported devices */ 776 while (*devices) { 777 /* if we match a supported device */ 778 if (*devices == di->pcii.device_id ) { 779 /* publish the device name */ 780 sprintf(di->name, "graphics/" DEVICE_FORMAT, 781 di->pcii.vendor_id, di->pcii.device_id, 782 di->pcii.bus, di->pcii.device, di->pcii.function); 783 784 /* remember the name */ 785 pd->device_names[count] = di->name; 786 /* mark the driver as available for R/W open */ 787 di->is_open = 0; 788 /* mark areas as not yet created */ 789 di->shared_area = -1; 790 /* mark pointer to shared data as invalid */ 791 di->si = NULL; 792 /* inc pointer to device info */ 793 di++; 794 /* inc count */ 795 count++; 796 /* break out of these while loops */ 797 goto next_device; 798 } 799 /* next supported device */ 800 devices++; 801 } 802 } 803 vendor++; 804 } 805 next_device: 806 /* next pci_info struct, please */ 807 pci_index++; 808 } 809 /* propagate count */ 810 pd->count = count; 811 /* terminate list of device names with a null pointer */ 812 pd->device_names[pd->count] = NULL; 813 } 814 815 static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) { 816 uint32 handled = B_HANDLED_INTERRUPT; 817 /* release the vblank semaphore */ 818 if (si->vblank >= 0) { 819 int32 blocked; 820 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 821 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 822 handled = B_INVOKE_SCHEDULER; 823 } 824 } 825 return handled; 826 } 827 828 static int32 829 nv_interrupt(void *data) 830 { 831 int32 handled = B_UNHANDLED_INTERRUPT; 832 device_info *di = (device_info *)data; 833 shared_info *si = di->si; 834 int32 *flags = &(si->flags); 835 vuint32 *regs; 836 837 /* is someone already handling an interrupt for this device? */ 838 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) { 839 goto exit0; 840 } 841 /* get regs */ 842 regs = di->regs; 843 844 /* was it a VBI? */ 845 if (caused_vbi(regs)) { 846 /*clear the interrupt*/ 847 clear_vbi(regs); 848 /*release the semaphore*/ 849 handled = thread_interrupt_work(flags, regs, si); 850 } 851 852 /* note that we're not in the handler any more */ 853 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 854 855 exit0: 856 return handled; 857 } 858 859 static status_t open_hook (const char* name, uint32 flags, void** cookie) { 860 int32 index = 0; 861 device_info *di; 862 shared_info *si; 863 thread_id thid; 864 thread_info thinfo; 865 status_t result = B_OK; 866 char shared_name[B_OS_NAME_LENGTH]; 867 physical_entry map[1]; 868 size_t net_buf_size; 869 void *unaligned_dma_buffer; 870 871 /* find the device name in the list of devices */ 872 /* we're never passed a name we didn't publish */ 873 while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; 874 875 /* for convienience */ 876 di = &(pd->di[index]); 877 878 /* make sure no one else has write access to the common data */ 879 AQUIRE_BEN(pd->kernel); 880 881 /* if it's already open for writing */ 882 if (di->is_open) { 883 /* mark it open another time */ 884 goto mark_as_open; 885 } 886 /* create the shared_info area */ 887 sprintf(shared_name, DEVICE_FORMAT " shared", 888 di->pcii.vendor_id, di->pcii.device_id, 889 di->pcii.bus, di->pcii.device, di->pcii.function); 890 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 891 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 892 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 893 B_USER_CLONEABLE_AREA); 894 if (di->shared_area < 0) { 895 /* return the error */ 896 result = di->shared_area; 897 goto done; 898 } 899 900 /* save a few dereferences */ 901 si = di->si; 902 903 /* create the DMA command buffer area */ 904 //fixme? for R4.5 a workaround for cloning would be needed! 905 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 906 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 907 /* create the area that will hold the DMA command buffer */ 908 si->unaligned_dma_area = 909 create_area("NV DMA cmd buffer", 910 (void **)&unaligned_dma_buffer, 911 B_ANY_KERNEL_ADDRESS, 912 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 913 B_FULL_LOCK | B_CONTIGUOUS, /* both properties needed: GPU always needs access */ 914 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 915 /* on error, abort */ 916 if (si->unaligned_dma_area < 0) 917 { 918 /* free the already created shared_info area, and return the error */ 919 result = si->unaligned_dma_area; 920 goto free_shared; 921 } 922 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 923 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 924 * even on older CPU's. */ 925 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 926 si->dma_buffer_pci = (void*) 927 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 928 929 /* map the net DMA command buffer into vmem, using Write Combining */ 930 si->dma_area = map_physical_memory( 931 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 932 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 933 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 934 /* if failed with write combining try again without */ 935 if (si->dma_area < 0) { 936 si->dma_area = map_physical_memory( 937 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 938 B_ANY_KERNEL_BLOCK_ADDRESS, 939 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 940 } 941 /* if there was an error, delete our other areas and pass on error*/ 942 if (si->dma_area < 0) 943 { 944 /* free the already created areas, and return the error */ 945 result = si->dma_area; 946 goto free_shared_and_uadma; 947 } 948 949 /* save the vendor and device IDs */ 950 si->vendor_id = di->pcii.vendor_id; 951 si->device_id = di->pcii.device_id; 952 si->revision = di->pcii.revision; 953 si->bus = di->pcii.bus; 954 si->device = di->pcii.device; 955 si->function = di->pcii.function; 956 957 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 958 * unified memory architecture (UMA) */ 959 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 960 { 961 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 962 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 963 si->ps.memory_size = 1024 * 1024 * 964 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 965 /* last 64kB RAM is used for the BIOS (or something else?) */ 966 si->ps.memory_size -= (64 * 1024); 967 break; 968 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 969 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 970 si->ps.memory_size = 1024 * 1024 * 971 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 972 /* last 64kB RAM is used for the BIOS (or something else?) */ 973 si->ps.memory_size -= (64 * 1024); 974 break; 975 default: 976 /* all other cards have own RAM: the amount of which is determined in the 977 * accelerant. */ 978 break; 979 } 980 981 /* map the device */ 982 result = map_device(di); 983 if (result < 0) goto free_shared_and_alldma; 984 985 /* we will be returning OK status for sure now */ 986 result = B_OK; 987 988 /* disable and clear any pending interrupts */ 989 disable_vbi(di->regs); 990 991 /* preset we can't use INT related functions */ 992 si->ps.int_assigned = false; 993 994 /* create a semaphore for vertical blank management */ 995 si->vblank = create_sem(0, di->name); 996 if (si->vblank < 0) goto mark_as_open; 997 998 /* change the owner of the semaphores to the opener's team */ 999 /* this is required because apps can't aquire kernel semaphores */ 1000 thid = find_thread(NULL); 1001 get_thread_info(thid, &thinfo); 1002 set_sem_owner(si->vblank, thinfo.team); 1003 1004 /* If there is a valid interrupt line assigned then set up interrupts */ 1005 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1006 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1007 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1008 { 1009 /* delete the semaphore as it won't be used */ 1010 delete_sem(si->vblank); 1011 si->vblank = -1; 1012 } 1013 else 1014 { 1015 /* otherwise install our interrupt handler */ 1016 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1017 /* bail if we couldn't install the handler */ 1018 if (result != B_OK) 1019 { 1020 /* delete the semaphore as it won't be used */ 1021 delete_sem(si->vblank); 1022 si->vblank = -1; 1023 } 1024 else 1025 { 1026 /* inform accelerant(s) we can use INT related functions */ 1027 si->ps.int_assigned = true; 1028 } 1029 } 1030 1031 mark_as_open: 1032 /* mark the device open */ 1033 di->is_open++; 1034 1035 /* send the cookie to the opener */ 1036 *cookie = di; 1037 1038 goto done; 1039 1040 1041 free_shared_and_alldma: 1042 /* clean up our aligned DMA area */ 1043 delete_area(si->dma_area); 1044 si->dma_area = -1; 1045 si->dma_buffer = NULL; 1046 1047 free_shared_and_uadma: 1048 /* clean up our unaligned DMA area */ 1049 delete_area(si->unaligned_dma_area); 1050 si->unaligned_dma_area = -1; 1051 si->dma_buffer_pci = NULL; 1052 1053 free_shared: 1054 /* clean up our shared area */ 1055 delete_area(di->shared_area); 1056 di->shared_area = -1; 1057 di->si = NULL; 1058 1059 done: 1060 /* end of critical section */ 1061 RELEASE_BEN(pd->kernel); 1062 1063 /* all done, return the status */ 1064 return result; 1065 } 1066 1067 /* ---------- 1068 read_hook - does nothing, gracefully 1069 ----- */ 1070 static status_t 1071 read_hook (void* dev, off_t pos, void* buf, size_t* len) 1072 { 1073 *len = 0; 1074 return B_NOT_ALLOWED; 1075 } 1076 1077 /* ---------- 1078 write_hook - does nothing, gracefully 1079 ----- */ 1080 static status_t 1081 write_hook (void* dev, off_t pos, const void* buf, size_t* len) 1082 { 1083 *len = 0; 1084 return B_NOT_ALLOWED; 1085 } 1086 1087 /* ---------- 1088 close_hook - does nothing, gracefully 1089 ----- */ 1090 static status_t 1091 close_hook (void* dev) 1092 { 1093 /* we don't do anything on close: there might be dup'd fd */ 1094 return B_NO_ERROR; 1095 } 1096 1097 /* ----------- 1098 free_hook - close down the device 1099 ----------- */ 1100 static status_t 1101 free_hook (void* dev) { 1102 device_info *di = (device_info *)dev; 1103 shared_info *si = di->si; 1104 vuint32 *regs = di->regs; 1105 1106 /* lock the driver */ 1107 AQUIRE_BEN(pd->kernel); 1108 1109 /* if opened multiple times, decrement the open count and exit */ 1110 if (di->is_open > 1) 1111 goto unlock_and_exit; 1112 1113 /* disable and clear any pending interrupts */ 1114 disable_vbi(regs); 1115 1116 if (si->ps.int_assigned) 1117 { 1118 /* remove interrupt handler */ 1119 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1120 1121 /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ 1122 delete_sem(si->vblank); 1123 si->vblank = -1; 1124 } 1125 1126 /* free regs and framebuffer areas */ 1127 unmap_device(di); 1128 1129 /* clean up our aligned DMA area */ 1130 delete_area(si->dma_area); 1131 si->dma_area = -1; 1132 si->dma_buffer = NULL; 1133 1134 /* clean up our unaligned DMA area */ 1135 delete_area(si->unaligned_dma_area); 1136 si->unaligned_dma_area = -1; 1137 si->dma_buffer_pci = NULL; 1138 1139 /* clean up our shared area */ 1140 delete_area(di->shared_area); 1141 di->shared_area = -1; 1142 di->si = NULL; 1143 1144 unlock_and_exit: 1145 /* mark the device available */ 1146 di->is_open--; 1147 /* unlock the driver */ 1148 RELEASE_BEN(pd->kernel); 1149 /* all done */ 1150 return B_OK; 1151 } 1152 1153 /* ----------- 1154 control_hook - where the real work is done 1155 ----------- */ 1156 static status_t 1157 control_hook (void* dev, uint32 msg, void *buf, size_t len) { 1158 device_info *di = (device_info *)dev; 1159 status_t result = B_DEV_INVALID_IOCTL; 1160 uint32 tmpUlong; 1161 1162 switch (msg) { 1163 /* the only PUBLIC ioctl */ 1164 case B_GET_ACCELERANT_SIGNATURE: { 1165 char *sig = (char *)buf; 1166 strcpy(sig, current_settings.accelerant); 1167 result = B_OK; 1168 } break; 1169 1170 /* PRIVATE ioctl from here on */ 1171 case NV_GET_PRIVATE_DATA: { 1172 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1173 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1174 gpd->shared_info_area = di->shared_area; 1175 result = B_OK; 1176 } 1177 } break; 1178 case NV_GET_PCI: { 1179 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1180 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1181 pci_info *pcii = &(di->pcii); 1182 gsp->value = get_pci(gsp->offset, gsp->size); 1183 result = B_OK; 1184 } 1185 } break; 1186 case NV_SET_PCI: { 1187 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1188 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1189 pci_info *pcii = &(di->pcii); 1190 set_pci(gsp->offset, gsp->size, gsp->value); 1191 result = B_OK; 1192 } 1193 } break; 1194 case NV_DEVICE_NAME: { // apsed 1195 nv_device_name *dn = (nv_device_name *)buf; 1196 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1197 strcpy(dn->name, di->name); 1198 result = B_OK; 1199 } 1200 } break; 1201 case NV_RUN_INTERRUPTS: { 1202 nv_set_bool_state *ri = (nv_set_bool_state *)buf; 1203 if (ri->magic == NV_PRIVATE_DATA_MAGIC) { 1204 vuint32 *regs = di->regs; 1205 if (ri->do_it) { 1206 enable_vbi(regs); 1207 } else { 1208 disable_vbi(regs); 1209 } 1210 result = B_OK; 1211 } 1212 } break; 1213 case NV_GET_NTH_AGP_INFO: { 1214 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1215 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1216 nai->exist = false; 1217 nai->agp_bus = false; 1218 if (agp_bus) { 1219 nai->agp_bus = true; 1220 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1221 nai->exist = true; 1222 } 1223 } 1224 result = B_OK; 1225 } 1226 } break; 1227 case NV_ENABLE_AGP: { 1228 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1229 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1230 if (agp_bus) { 1231 nca->agp_bus = true; 1232 (*agp_bus->enable_agp)(&(nca->cmd)); 1233 } else { 1234 nca->agp_bus = false; 1235 nca->cmd = 0; 1236 } 1237 result = B_OK; 1238 } 1239 } break; 1240 case NV_ISA_OUT: { 1241 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1242 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1243 pci_info *pcii = &(di->pcii); 1244 1245 /* lock the driver: 1246 * no other graphics card may have ISA I/O enabled when we enter */ 1247 AQUIRE_BEN(pd->kernel); 1248 1249 /* enable ISA I/O access */ 1250 tmpUlong = get_pci(PCI_command, 2); 1251 tmpUlong |= PCI_command_io; 1252 set_pci(PCI_command, 2, tmpUlong); 1253 1254 if (io_isa->size == 1) 1255 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1256 else 1257 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1258 result = B_OK; 1259 1260 /* disable ISA I/O access */ 1261 tmpUlong = get_pci(PCI_command, 2); 1262 tmpUlong &= ~PCI_command_io; 1263 set_pci(PCI_command, 2, tmpUlong); 1264 1265 /* end of critical section */ 1266 RELEASE_BEN(pd->kernel); 1267 } 1268 } break; 1269 case NV_ISA_IN: { 1270 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1271 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1272 pci_info *pcii = &(di->pcii); 1273 1274 /* lock the driver: 1275 * no other graphics card may have ISA I/O enabled when we enter */ 1276 AQUIRE_BEN(pd->kernel); 1277 1278 /* enable ISA I/O access */ 1279 tmpUlong = get_pci(PCI_command, 2); 1280 tmpUlong |= PCI_command_io; 1281 set_pci(PCI_command, 2, tmpUlong); 1282 1283 if (io_isa->size == 1) 1284 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1285 else 1286 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1287 result = B_OK; 1288 1289 /* disable ISA I/O access */ 1290 tmpUlong = get_pci(PCI_command, 2); 1291 tmpUlong &= ~PCI_command_io; 1292 set_pci(PCI_command, 2, tmpUlong); 1293 1294 /* end of critical section */ 1295 RELEASE_BEN(pd->kernel); 1296 } 1297 } break; 1298 } 1299 return result; 1300 } 1301