1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-6/2010. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_gart_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia Geforce FX 6800 Ultra */ 109 0x0041, /* Nvidia Geforce FX 6800 */ 110 0x0042, /* Nvidia Geforce FX 6800LE */ 111 0x0043, /* Nvidia Geforce 6800 XE */ 112 0x0045, /* Nvidia Geforce FX 6800 GT */ 113 0x0046, /* Nvidia Geforce FX 6800 GT */ 114 0x0047, /* Nvidia Geforce 6800 GS */ 115 0x0048, /* Nvidia Geforce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia Geforce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia Geforce 6800 GS */ 126 0x00c1, /* Nvidia Geforce FX 6800 */ 127 0x00c2, /* Nvidia Geforce FX 6800LE */ 128 0x00c3, /* Nvidia Geforce FX 6800 XT */ 129 0x00c8, /* Nvidia Geforce FX 6800 Go */ 130 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia Geforce FX 6600 AGP */ 137 0x00f3, /* Nvidia Geforce 6200 */ 138 0x00f4, /* Nvidia Geforce 6600 LE */ 139 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia Geforce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */ 149 0x0100, /* Nvidia Geforce256 SDR */ 150 0x0101, /* Nvidia Geforce256 DDR */ 151 0x0102, /* Nvidia Geforce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia Geforce2 MX/MX400 */ 154 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia Geforce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia Geforce FX 6600 GT */ 158 0x0141, /* Nvidia Geforce FX 6600 */ 159 0x0142, /* Nvidia Geforce FX 6600LE */ 160 0x0143, /* Nvidia Geforce 6600 VE */ 161 0x0144, /* Nvidia Geforce FX 6600 Go */ 162 0x0145, /* Nvidia Geforce FX 6610 XL */ 163 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia Geforce FX 6700 XL */ 165 0x0148, /* Nvidia Geforce FX 6600 Go */ 166 0x0149, /* Nvidia Geforce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia Geforce2 GTS/Pro */ 173 0x0151, /* Nvidia Geforce2 Ti DDR */ 174 0x0152, /* Nvidia Geforce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia Geforce 6500 Go */ 177 0x0161, /* Nvidia Geforce 6200 TurboCache */ 178 0x0162, /* Nvidia Geforce 6200SE TurboCache */ 179 0x0163, /* Nvidia Geforce 6200LE */ 180 0x0164, /* Nvidia Geforce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia Geforce 6400 Go */ 183 0x0167, /* Nvidia Geforce 6200 Go */ 184 0x0168, /* Nvidia Geforce 6400 Go */ 185 0x0169, /* Nvidia Geforce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia Geforce4 MX 460 */ 192 0x0171, /* Nvidia Geforce4 MX 440 */ 193 0x0172, /* Nvidia Geforce4 MX 420 */ 194 0x0173, /* Nvidia Geforce4 MX 440SE */ 195 0x0174, /* Nvidia Geforce4 440 Go */ 196 0x0175, /* Nvidia Geforce4 420 Go */ 197 0x0176, /* Nvidia Geforce4 420 Go 32M */ 198 0x0177, /* Nvidia Geforce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia Geforce4 410 Go 16M */ 204 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia Geforce4 448 Go */ 209 0x0187, /* Nvidia Geforce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia Geforce4 448 Go */ 216 0x01a0, /* Nvidia Geforce2 Integrated GPU */ 217 0x01d1, /* Nvidia Geforce 7300 LE */ 218 0x01d3, /* Nvidia Geforce 7300 SE */ 219 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */ 220 0x01d8, /* Nvidia Geforce 7400 GO */ 221 0x01dd, /* Nvidia Geforce 7500 LE */ 222 0x01df, /* Nvidia Geforce 7300 GS */ 223 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */ 224 0x0200, /* Nvidia Geforce3 */ 225 0x0201, /* Nvidia Geforce3 Ti 200 */ 226 0x0202, /* Nvidia Geforce3 Ti 500 */ 227 0x0203, /* Nvidia Quadro DCC */ 228 0x0211, /* Nvidia Geforce FX 6800 */ 229 0x0212, /* Nvidia Geforce FX 6800LE */ 230 0x0215, /* Nvidia Geforce FX 6800 GT */ 231 0x0218, /* Nvidia Geforce 6800 XT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */ 239 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */ 241 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */ 242 0x0250, /* Nvidia Geforce4 Ti 4600 */ 243 0x0251, /* Nvidia Geforce4 Ti 4400 */ 244 0x0252, /* Nvidia Geforce4 Ti 4600 */ 245 0x0253, /* Nvidia Geforce4 Ti 4200 */ 246 0x0258, /* Nvidia Quadro4 900 XGL */ 247 0x0259, /* Nvidia Quadro4 750 XGL */ 248 0x025b, /* Nvidia Quadro4 700 XGL */ 249 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */ 250 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */ 251 0x0282, /* Nvidia Geforce4 Ti 4800SE */ 252 0x0286, /* Nvidia Geforce4 4200 Go */ 253 0x0288, /* Nvidia Quadro4 980 XGL */ 254 0x0289, /* Nvidia Quadro4 780 XGL */ 255 0x028c, /* Nvidia Quadro4 700 GoGL */ 256 0x0290, /* Nvidia Geforce 7900 GTX */ 257 0x0291, /* Nvidia Geforce 7900 GT */ 258 0x0293, /* Nvidia Geforce 7900 GX2 */ 259 0x0294, /* Nvidia Geforce 7950 GX2 */ 260 0x0295, /* Nvidia Geforce 7950 GT */ 261 0x0298, /* Nvidia Geforce Go 7900 GS */ 262 0x0299, /* Nvidia Geforce Go 7900 GTX */ 263 0x029c, /* Nvidia Quadro FX 5500 */ 264 0x029f, /* Nvidia Quadro FX 4500 X2 */ 265 0x02a0, /* Nvidia Geforce3 Integrated GPU */ 266 0x02e0, /* Nvidia Geforce 7600 GT */ 267 0x02e1, /* Nvidia Geforce 7600 GS */ 268 0x02e2, /* Nvidia Geforce 7300 GT */ 269 0x0301, /* Nvidia Geforce FX 5800 Ultra */ 270 0x0302, /* Nvidia Geforce FX 5800 */ 271 0x0308, /* Nvidia Quadro FX 2000 */ 272 0x0309, /* Nvidia Quadro FX 1000 */ 273 0x0311, /* Nvidia Geforce FX 5600 Ultra */ 274 0x0312, /* Nvidia Geforce FX 5600 */ 275 0x0313, /* Nvidia unknown FX */ 276 0x0314, /* Nvidia Geforce FX 5600XT */ 277 0x0316, /* Nvidia unknown FX Go */ 278 0x0317, /* Nvidia unknown FX Go */ 279 0x031a, /* Nvidia Geforce FX 5600 Go */ 280 0x031b, /* Nvidia Geforce FX 5650 Go */ 281 0x031c, /* Nvidia Quadro FX 700 Go */ 282 0x031d, /* Nvidia unknown FX Go */ 283 0x031e, /* Nvidia unknown FX Go */ 284 0x031f, /* Nvidia unknown FX Go */ 285 0x0320, /* Nvidia Geforce FX 5200 */ 286 0x0321, /* Nvidia Geforce FX 5200 Ultra */ 287 0x0322, /* Nvidia Geforce FX 5200 */ 288 0x0323, /* Nvidia Geforce FX 5200LE */ 289 0x0324, /* Nvidia Geforce FX 5200 Go */ 290 0x0325, /* Nvidia Geforce FX 5250 Go */ 291 0x0326, /* Nvidia Geforce FX 5500 */ 292 0x0327, /* Nvidia Geforce FX 5100 */ 293 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */ 294 0x0329, /* Nvidia Geforce FX 5200 (PPC) */ 295 0x032a, /* Nvidia Quadro NVS 280 PCI */ 296 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 297 0x032c, /* Nvidia Geforce FX 5300 Go */ 298 0x032d, /* Nvidia Geforce FX 5100 Go */ 299 0x032e, /* Nvidia unknown FX Go */ 300 0x032f, /* Nvidia unknown FX Go */ 301 0x0330, /* Nvidia Geforce FX 5900 Ultra */ 302 0x0331, /* Nvidia Geforce FX 5900 */ 303 0x0332, /* Nvidia Geforce FX 5900 XT */ 304 0x0333, /* Nvidia Geforce FX 5950 Ultra */ 305 0x0334, /* Nvidia Geforce FX 5900 ZT */ 306 0x0338, /* Nvidia Quadro FX 3000 */ 307 0x033f, /* Nvidia Quadro FX 700 */ 308 0x0341, /* Nvidia Geforce FX 5700 Ultra */ 309 0x0342, /* Nvidia Geforce FX 5700 */ 310 0x0343, /* Nvidia Geforce FX 5700LE */ 311 0x0344, /* Nvidia Geforce FX 5700VE */ 312 0x0345, /* Nvidia unknown FX */ 313 0x0347, /* Nvidia Geforce FX 5700 Go */ 314 0x0348, /* Nvidia Geforce FX 5700 Go */ 315 0x0349, /* Nvidia unknown FX Go */ 316 0x034b, /* Nvidia unknown FX Go */ 317 0x034c, /* Nvidia Quadro FX 1000 Go */ 318 0x034e, /* Nvidia Quadro FX 1100 */ 319 0x034f, /* Nvidia unknown FX */ 320 0x0391, /* Nvidia Geforce 7600 GT */ 321 0x0392, /* Nvidia Geforce 7600 GS */ 322 0x0393, /* Nvidia Geforce 7300 GT */ 323 0x0394, /* Nvidia Geforce 7600 LE */ 324 0x0398, /* Nvidia Geforce 7600 GO */ 325 0x03d0, /* Nvidia Geforce 6100 nForce 430 */ 326 0x03d1, /* Nvidia Geforce 6100 nForce 405 */ 327 0x03d2, /* Nvidia Geforce 6100 nForce 400 */ 328 0x03d5, /* Nvidia Geforce 6100 nForce 420 */ 329 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */ 330 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */ 331 0 332 }; 333 334 static uint16 elsa_device_list[] = { 335 0x0c60, /* Elsa Gladiac Geforce2 MX */ 336 0 337 }; 338 339 static uint16 nvstbsgs_device_list[] = { 340 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 341 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 342 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 343 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 344 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 345 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 346 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 347 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 348 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 349 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 350 0 351 }; 352 353 static uint16 varisys_device_list[] = { 354 0x3503, /* Varisys Geforce4 MX440 */ 355 0x3505, /* Varisys Geforce4 Ti 4200 */ 356 0 357 }; 358 359 static struct { 360 uint16 vendor; 361 uint16 *devices; 362 } SupportedDevices[] = { 363 {VENDOR_ID_NVIDIA, nvidia_device_list}, 364 {VENDOR_ID_ELSA, elsa_device_list}, 365 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 366 {VENDOR_ID_VARISYS, varisys_device_list}, 367 {0x0000, NULL} 368 }; 369 370 static nv_settings sSettings = { // see comments in nvidia.settings 371 /* for driver */ 372 DRIVER_PREFIX ".accelerant", 373 "none", // primary 374 false, // dumprom 375 /* for accelerant */ 376 0x00000000, // logmask 377 0, // memory 378 0, // tv_output 379 true, // usebios 380 true, // hardcursor 381 false, // switchhead 382 false, // force_pci 383 false, // unhide_fw 384 false, // pgm_panel 385 true, // dma_acc 386 false, // vga_on_tv 387 false, // force_sync 388 false, // force_ws 389 false, // block_acc 390 0, // gpu_clk 391 0, // ram_clk 392 }; 393 394 395 static void 396 dumprom(void *rom, uint32 size, pci_info pcii) 397 { 398 int fd; 399 uint32 cnt; 400 char fname[64]; 401 402 /* determine the romfile name: we need split-up per card in the system */ 403 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 404 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 405 406 fd = open (fname, O_WRONLY | O_CREAT, 0666); 407 if (fd < 0) return; 408 409 /* apparantly max. 32kb may be written at once; 410 * the ROM size is a multiple of that anyway. */ 411 for (cnt = 0; (cnt < size); cnt += 32768) 412 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 413 close (fd); 414 } 415 416 417 /*! return 1 if vblank interrupt has occured */ 418 static int 419 caused_vbi_crtc1(vuint32 * regs) 420 { 421 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 422 } 423 424 425 /*! clear the vblank interrupt */ 426 static void 427 clear_vbi_crtc1(vuint32 * regs) 428 { 429 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 430 } 431 432 433 static void 434 enable_vbi_crtc1(vuint32 * regs) 435 { 436 /* clear the vblank interrupt */ 437 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 438 /* enable nVidia interrupt source vblank */ 439 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 440 /* enable nVidia interrupt system hardware (b0-1) */ 441 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 442 } 443 444 445 static void 446 disable_vbi_crtc1(vuint32 * regs) 447 { 448 /* disable nVidia interrupt source vblank */ 449 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 450 /* clear the vblank interrupt */ 451 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 452 } 453 454 455 /*! return 1 if vblank interrupt has occured */ 456 static int 457 caused_vbi_crtc2(vuint32 * regs) 458 { 459 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 460 } 461 462 463 /*! clear the vblank interrupt */ 464 static void 465 clear_vbi_crtc2(vuint32 * regs) 466 { 467 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 468 } 469 470 471 static void 472 enable_vbi_crtc2(vuint32 * regs) 473 { 474 /* clear the vblank interrupt */ 475 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 476 /* enable nVidia interrupt source vblank */ 477 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 478 /* enable nVidia interrupt system hardware (b0-1) */ 479 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 480 } 481 482 483 static void 484 disable_vbi_crtc2(vuint32 * regs) 485 { 486 /* disable nVidia interrupt source vblank */ 487 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 488 /* clear the vblank interrupt */ 489 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 490 } 491 492 493 //fixme: 494 //dangerous code, on singlehead cards better not try accessing secondary head 495 //registers (card might react in unpredictable ways, though there's only a small 496 //chance we actually run into this). 497 //fix requires (some) card recognition code to be moved from accelerant to 498 //kerneldriver... 499 static void 500 disable_vbi_all(vuint32 * regs) 501 { 502 /* disable nVidia interrupt source vblank */ 503 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 504 /* clear the vblank interrupt */ 505 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 506 507 /* disable nVidia interrupt source vblank */ 508 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 509 /* clear the vblank interrupt */ 510 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 511 512 /* disable nVidia interrupt system hardware (b0-1) */ 513 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 514 } 515 516 517 static status_t 518 map_device(device_info *di) 519 { 520 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 521 shared_info *si = di->si; 522 uint32 tmpUlong, tmpROMshadow; 523 pci_info *pcii = &(di->pcii); 524 system_info sysinfo; 525 526 /* variables for making copy of ROM */ 527 uint8* rom_temp; 528 area_id rom_area = -1; 529 530 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 531 int registers = 0; 532 int frame_buffer = 1; 533 534 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 535 tmpUlong = get_pci(PCI_command, 2); 536 /* enable PCI access */ 537 tmpUlong |= PCI_command_memory; 538 /* enable busmastering */ 539 tmpUlong |= PCI_command_master; 540 /* disable ISA I/O access */ 541 tmpUlong &= ~PCI_command_io; 542 set_pci(PCI_command, 2, tmpUlong); 543 544 /*work out which version of BeOS is running*/ 545 get_system_info(&sysinfo); 546 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 547 { 548 si->use_clone_bugfix = 1; 549 } 550 else 551 { 552 si->use_clone_bugfix = 0; 553 } 554 555 /* work out a name for the register mapping */ 556 sprintf(buffer, DEVICE_FORMAT " regs", 557 di->pcii.vendor_id, di->pcii.device_id, 558 di->pcii.bus, di->pcii.device, di->pcii.function); 559 560 /* get a virtual memory address for the registers*/ 561 si->regs_area = map_physical_memory( 562 buffer, 563 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 564 di->pcii.u.h0.base_registers_pci[registers], 565 di->pcii.u.h0.base_register_sizes[registers], 566 B_ANY_KERNEL_ADDRESS, 567 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 568 (void **)&(di->regs)); 569 si->clone_bugfix_regs = (uint32 *) di->regs; 570 571 /* if mapping registers to vmem failed then pass on error */ 572 if (si->regs_area < 0) return si->regs_area; 573 574 /* work out a name for the ROM mapping*/ 575 sprintf(buffer, DEVICE_FORMAT " rom", 576 di->pcii.vendor_id, di->pcii.device_id, 577 di->pcii.bus, di->pcii.device, di->pcii.function); 578 579 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 580 /* warning: 581 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 582 * NV18, NV28 and NV34 keep working. 583 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 584 * however the actual ROM content (so the used part) is intact (confirmed). */ 585 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 586 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 587 set_pci(NVCFG_ROMSHADOW, 4, 0); 588 589 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 590 tmpUlong = get_pci(PCI_rom_base, 4); 591 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 592 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 593 //legacy space will get us into trouble if we aren't the primary graphics card!! 594 //(as legacy space always has the primary card's ROM 'mapped'!) 595 if (tmpUlong) { 596 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 597 tmpUlong |= 0x00000001; 598 set_pci(PCI_rom_base, 4, tmpUlong); 599 600 rom_area = map_physical_memory( 601 buffer, 602 di->pcii.u.h0.rom_base_pci, 603 di->pcii.u.h0.rom_size, 604 B_ANY_KERNEL_ADDRESS, 605 B_READ_AREA, 606 (void **)&(rom_temp) 607 ); 608 609 /* check if we got the BIOS and signature (might fail on laptops..) */ 610 if (rom_area >= 0) { 611 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 612 /* apparantly no ROM is mapped here */ 613 delete_area(rom_area); 614 rom_area = -1; 615 /* force using ISA legacy map as fall-back */ 616 tmpUlong = 0x00000000; 617 } 618 } else { 619 /* mapping failed: force using ISA legacy map as fall-back */ 620 tmpUlong = 0x00000000; 621 } 622 } 623 624 if (!tmpUlong) { 625 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 626 rom_area = map_physical_memory(buffer, 0x000c0000, 627 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 628 } 629 630 /* if mapping ROM to vmem failed then clean up and pass on error */ 631 if (rom_area < 0) { 632 delete_area(si->regs_area); 633 si->regs_area = -1; 634 return rom_area; 635 } 636 637 /* dump ROM to file if selected in nvidia.settings 638 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 639 if (sSettings.dumprom) 640 dumprom(rom_temp, 65536, di->pcii); 641 642 /* make a copy of ROM for future reference */ 643 memcpy(si->rom_mirror, rom_temp, 65536); 644 645 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 646 tmpUlong = get_pci(PCI_rom_base, 4); 647 tmpUlong &= 0xfffffffe; 648 set_pci(PCI_rom_base, 4, tmpUlong); 649 delete_area(rom_area); 650 651 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 652 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 653 654 /* work out a name for the framebuffer mapping*/ 655 sprintf(buffer, DEVICE_FORMAT " framebuffer", 656 di->pcii.vendor_id, di->pcii.device_id, 657 di->pcii.bus, di->pcii.device, di->pcii.function); 658 659 /* map the framebuffer into vmem, using Write Combining*/ 660 si->fb_area = map_physical_memory(buffer, 661 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 662 di->pcii.u.h0.base_registers_pci[frame_buffer], 663 di->pcii.u.h0.base_register_sizes[frame_buffer], 664 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 665 B_READ_AREA | B_WRITE_AREA, 666 &(si->framebuffer)); 667 668 /*if failed with write combining try again without*/ 669 if (si->fb_area < 0) { 670 si->fb_area = map_physical_memory(buffer, 671 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 672 di->pcii.u.h0.base_registers_pci[frame_buffer], 673 di->pcii.u.h0.base_register_sizes[frame_buffer], 674 B_ANY_KERNEL_BLOCK_ADDRESS, 675 B_READ_AREA | B_WRITE_AREA, 676 &(si->framebuffer)); 677 } 678 679 /* if there was an error, delete our other areas and pass on error*/ 680 if (si->fb_area < 0) { 681 delete_area(si->regs_area); 682 si->regs_area = -1; 683 return si->fb_area; 684 } 685 686 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 687 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 688 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 689 690 /* note the amount of memory mapped by the kerneldriver so we can make sure we 691 * don't attempt to adress more later on */ 692 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 693 694 // remember settings for use here and in accelerant 695 si->settings = sSettings; 696 697 /* in any case, return the result */ 698 return si->fb_area; 699 } 700 701 702 static void 703 unmap_device(device_info *di) 704 { 705 shared_info *si = di->si; 706 uint32 tmpUlong; 707 pci_info *pcii = &(di->pcii); 708 709 /* disable memory mapped IO */ 710 tmpUlong = get_pci(PCI_command, 4); 711 tmpUlong &= 0xfffffffc; 712 set_pci(PCI_command, 4, tmpUlong); 713 /* delete the areas */ 714 if (si->regs_area >= 0) 715 delete_area(si->regs_area); 716 if (si->fb_area >= 0) 717 delete_area(si->fb_area); 718 si->regs_area = si->fb_area = -1; 719 si->framebuffer = NULL; 720 di->regs = NULL; 721 } 722 723 724 static void 725 probe_devices(void) 726 { 727 uint32 pci_index = 0; 728 uint32 count = 0; 729 device_info *di = pd->di; 730 char tmp_name[B_OS_NAME_LENGTH]; 731 732 /* while there are more pci devices */ 733 while (count < MAX_DEVICES 734 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 735 int vendor = 0; 736 737 /* if we match a supported vendor */ 738 while (SupportedDevices[vendor].vendor) { 739 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 740 uint16 *devices = SupportedDevices[vendor].devices; 741 /* while there are more supported devices */ 742 while (*devices) { 743 /* if we match a supported device */ 744 if (*devices == di->pcii.device_id ) { 745 /* publish the device name */ 746 sprintf(tmp_name, DEVICE_FORMAT, 747 di->pcii.vendor_id, di->pcii.device_id, 748 di->pcii.bus, di->pcii.device, di->pcii.function); 749 /* tweak the exported name to show first in the alphabetically ordered /dev/ 750 * hierarchy folder, so the system will use it as primary adaptor if requested 751 * via nvidia.settings. */ 752 if (strcmp(tmp_name, sSettings.primary) == 0) 753 sprintf(tmp_name, "-%s", sSettings.primary); 754 /* add /dev/ hierarchy path */ 755 sprintf(di->name, "graphics/%s", tmp_name); 756 /* remember the name */ 757 pd->device_names[count] = di->name; 758 /* mark the driver as available for R/W open */ 759 di->is_open = 0; 760 /* mark areas as not yet created */ 761 di->shared_area = -1; 762 /* mark pointer to shared data as invalid */ 763 di->si = NULL; 764 /* inc pointer to device info */ 765 di++; 766 /* inc count */ 767 count++; 768 /* break out of these while loops */ 769 goto next_device; 770 } 771 /* next supported device */ 772 devices++; 773 } 774 } 775 vendor++; 776 } 777 next_device: 778 /* next pci_info struct, please */ 779 pci_index++; 780 } 781 /* propagate count */ 782 pd->count = count; 783 /* terminate list of device names with a null pointer */ 784 pd->device_names[pd->count] = NULL; 785 } 786 787 788 static uint32 789 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 790 { 791 uint32 handled = B_HANDLED_INTERRUPT; 792 /* release the vblank semaphore */ 793 if (si->vblank >= 0) { 794 int32 blocked; 795 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 796 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 797 handled = B_INVOKE_SCHEDULER; 798 } 799 } 800 return handled; 801 } 802 803 804 static int32 805 nv_interrupt(void *data) 806 { 807 int32 handled = B_UNHANDLED_INTERRUPT; 808 device_info *di = (device_info *)data; 809 shared_info *si = di->si; 810 int32 *flags = &(si->flags); 811 vuint32 *regs; 812 813 /* is someone already handling an interrupt for this device? */ 814 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 815 816 /* get regs */ 817 regs = di->regs; 818 819 /* was it a VBI? */ 820 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 821 if (si->ps.secondary_head) { 822 //fixme: 823 //rewrite once we use one driver instance 'per head' (instead of 'per card') 824 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 825 /* clear the interrupt(s) */ 826 clear_vbi_crtc1(regs); 827 clear_vbi_crtc2(regs); 828 /* release the semaphore */ 829 handled = thread_interrupt_work(flags, regs, si); 830 } 831 } else { 832 if (caused_vbi_crtc1(regs)) { 833 /* clear the interrupt */ 834 clear_vbi_crtc1(regs); 835 /* release the semaphore */ 836 handled = thread_interrupt_work(flags, regs, si); 837 } 838 } 839 840 /* note that we're not in the handler any more */ 841 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 842 843 exit0: 844 return handled; 845 } 846 847 848 // #pragma mark - device hooks 849 850 851 static status_t 852 open_hook(const char* name, uint32 flags, void** cookie) 853 { 854 int32 index = 0; 855 device_info *di; 856 shared_info *si; 857 thread_id thid; 858 thread_info thinfo; 859 status_t result = B_OK; 860 char shared_name[B_OS_NAME_LENGTH]; 861 physical_entry map[1]; 862 size_t net_buf_size; 863 void *unaligned_dma_buffer; 864 uint32 mem_size; 865 866 /* find the device name in the list of devices */ 867 /* we're never passed a name we didn't publish */ 868 while (pd->device_names[index] 869 && (strcmp(name, pd->device_names[index]) != 0)) 870 index++; 871 872 /* for convienience */ 873 di = &(pd->di[index]); 874 875 /* make sure no one else has write access to the common data */ 876 AQUIRE_BEN(pd->kernel); 877 878 /* if it's already open for writing */ 879 if (di->is_open) { 880 /* mark it open another time */ 881 goto mark_as_open; 882 } 883 /* create the shared_info area */ 884 sprintf(shared_name, DEVICE_FORMAT " shared", 885 di->pcii.vendor_id, di->pcii.device_id, 886 di->pcii.bus, di->pcii.device, di->pcii.function); 887 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 888 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 889 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 890 B_USER_CLONEABLE_AREA); 891 if (di->shared_area < 0) { 892 /* return the error */ 893 result = di->shared_area; 894 goto done; 895 } 896 897 /* save a few dereferences */ 898 si = di->si; 899 900 /* create the DMA command buffer area */ 901 //fixme? for R4.5 a workaround for cloning would be needed! 902 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 903 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 904 /* create the area that will hold the DMA command buffer */ 905 si->unaligned_dma_area = 906 create_area("NV DMA cmd buffer", 907 (void **)&unaligned_dma_buffer, 908 B_ANY_KERNEL_ADDRESS, 909 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 910 B_32_BIT_CONTIGUOUS, /* GPU always needs access */ 911 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 912 // TODO: Physical aligning can be done without waste using the 913 // private create_area_etc(). 914 /* on error, abort */ 915 if (si->unaligned_dma_area < 0) 916 { 917 /* free the already created shared_info area, and return the error */ 918 result = si->unaligned_dma_area; 919 goto free_shared; 920 } 921 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 922 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 923 * even on older CPU's. */ 924 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 925 si->dma_buffer_pci = (void*) 926 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); 927 928 /* map the net DMA command buffer into vmem, using Write Combining */ 929 si->dma_area = map_physical_memory( 930 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, 931 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 932 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 933 /* if failed with write combining try again without */ 934 if (si->dma_area < 0) { 935 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer", 936 (addr_t)si->dma_buffer_pci, net_buf_size, 937 B_ANY_KERNEL_BLOCK_ADDRESS, 938 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 939 } 940 /* if there was an error, delete our other areas and pass on error*/ 941 if (si->dma_area < 0) 942 { 943 /* free the already created areas, and return the error */ 944 result = si->dma_area; 945 goto free_shared_and_uadma; 946 } 947 948 /* save the vendor and device IDs */ 949 si->vendor_id = di->pcii.vendor_id; 950 si->device_id = di->pcii.device_id; 951 si->revision = di->pcii.revision; 952 si->bus = di->pcii.bus; 953 si->device = di->pcii.device; 954 si->function = di->pcii.function; 955 956 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 957 si->accelerant_in_use = false; 958 /* preset singlehead card to prevent early INT routine calls (once installed) to 959 * wrongly identify the INT request coming from us! */ 960 si->ps.secondary_head = false; 961 962 /* map the device */ 963 result = map_device(di); 964 if (result < 0) goto free_shared_and_alldma; 965 966 /* we will be returning OK status for sure now */ 967 result = B_OK; 968 969 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 970 * unified memory architecture (UMA) */ 971 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 972 { 973 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */ 974 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 975 mem_size = 1024 * 1024 * 976 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 977 /* don't attempt to adress memory not mapped by the kerneldriver */ 978 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 979 /* last 64kB RAM is used for the BIOS (or something else?) */ 980 si->ps.memory_size -= (64 * 1024); 981 break; 982 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */ 983 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 984 mem_size = 1024 * 1024 * 985 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 986 /* don't attempt to adress memory not mapped by the kerneldriver */ 987 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 988 /* last 64kB RAM is used for the BIOS (or something else?) */ 989 si->ps.memory_size -= (64 * 1024); 990 break; 991 default: 992 /* all other cards have own RAM: the amount of which is determined in the 993 * accelerant. */ 994 break; 995 } 996 997 /* disable and clear any pending interrupts */ 998 //fixme: 999 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1000 disable_vbi_all(di->regs); 1001 1002 /* preset we can't use INT related functions */ 1003 si->ps.int_assigned = false; 1004 1005 /* create a semaphore for vertical blank management */ 1006 si->vblank = create_sem(0, di->name); 1007 if (si->vblank < 0) goto mark_as_open; 1008 1009 /* change the owner of the semaphores to the opener's team */ 1010 /* this is required because apps can't aquire kernel semaphores */ 1011 thid = find_thread(NULL); 1012 get_thread_info(thid, &thinfo); 1013 set_sem_owner(si->vblank, thinfo.team); 1014 1015 /* If there is a valid interrupt line assigned then set up interrupts */ 1016 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1017 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1018 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1019 { 1020 /* delete the semaphore as it won't be used */ 1021 delete_sem(si->vblank); 1022 si->vblank = -1; 1023 } 1024 else 1025 { 1026 /* otherwise install our interrupt handler */ 1027 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1028 /* bail if we couldn't install the handler */ 1029 if (result != B_OK) 1030 { 1031 /* delete the semaphore as it won't be used */ 1032 delete_sem(si->vblank); 1033 si->vblank = -1; 1034 } 1035 else 1036 { 1037 /* inform accelerant(s) we can use INT related functions */ 1038 si->ps.int_assigned = true; 1039 } 1040 } 1041 1042 mark_as_open: 1043 /* mark the device open */ 1044 di->is_open++; 1045 1046 /* send the cookie to the opener */ 1047 *cookie = di; 1048 1049 goto done; 1050 1051 1052 free_shared_and_alldma: 1053 /* clean up our aligned DMA area */ 1054 delete_area(si->dma_area); 1055 si->dma_area = -1; 1056 si->dma_buffer = NULL; 1057 1058 free_shared_and_uadma: 1059 /* clean up our unaligned DMA area */ 1060 delete_area(si->unaligned_dma_area); 1061 si->unaligned_dma_area = -1; 1062 si->dma_buffer_pci = NULL; 1063 1064 free_shared: 1065 /* clean up our shared area */ 1066 delete_area(di->shared_area); 1067 di->shared_area = -1; 1068 di->si = NULL; 1069 1070 done: 1071 /* end of critical section */ 1072 RELEASE_BEN(pd->kernel); 1073 1074 /* all done, return the status */ 1075 return result; 1076 } 1077 1078 1079 static status_t 1080 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1081 { 1082 *len = 0; 1083 return B_NOT_ALLOWED; 1084 } 1085 1086 1087 static status_t 1088 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1089 { 1090 *len = 0; 1091 return B_NOT_ALLOWED; 1092 } 1093 1094 1095 static status_t 1096 close_hook(void* dev) 1097 { 1098 /* we don't do anything on close: there might be dup'd fd */ 1099 return B_NO_ERROR; 1100 } 1101 1102 1103 static status_t 1104 free_hook(void* dev) 1105 { 1106 device_info *di = (device_info *)dev; 1107 shared_info *si = di->si; 1108 vuint32 *regs = di->regs; 1109 1110 /* lock the driver */ 1111 AQUIRE_BEN(pd->kernel); 1112 1113 /* if opened multiple times, decrement the open count and exit */ 1114 if (di->is_open > 1) 1115 goto unlock_and_exit; 1116 1117 /* disable and clear any pending interrupts */ 1118 //fixme: 1119 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1120 disable_vbi_all(regs); 1121 1122 if (si->ps.int_assigned) { 1123 /* remove interrupt handler */ 1124 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1125 1126 /* delete the semaphores, ignoring any errors ('cause the owning 1127 team may have died on us) */ 1128 delete_sem(si->vblank); 1129 si->vblank = -1; 1130 } 1131 1132 /* free regs and framebuffer areas */ 1133 unmap_device(di); 1134 1135 /* clean up our aligned DMA area */ 1136 delete_area(si->dma_area); 1137 si->dma_area = -1; 1138 si->dma_buffer = NULL; 1139 1140 /* clean up our unaligned DMA area */ 1141 delete_area(si->unaligned_dma_area); 1142 si->unaligned_dma_area = -1; 1143 si->dma_buffer_pci = NULL; 1144 1145 /* clean up our shared area */ 1146 delete_area(di->shared_area); 1147 di->shared_area = -1; 1148 di->si = NULL; 1149 1150 unlock_and_exit: 1151 /* mark the device available */ 1152 di->is_open--; 1153 /* unlock the driver */ 1154 RELEASE_BEN(pd->kernel); 1155 /* all done */ 1156 return B_OK; 1157 } 1158 1159 1160 static status_t 1161 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1162 { 1163 device_info *di = (device_info *)dev; 1164 status_t result = B_DEV_INVALID_IOCTL; 1165 uint32 tmpUlong; 1166 1167 switch (msg) { 1168 /* the only PUBLIC ioctl */ 1169 case B_GET_ACCELERANT_SIGNATURE: 1170 { 1171 strcpy((char* )buf, sSettings.accelerant); 1172 result = B_OK; 1173 break; 1174 } 1175 1176 /* PRIVATE ioctl from here on */ 1177 case NV_GET_PRIVATE_DATA: 1178 { 1179 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1180 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1181 gpd->shared_info_area = di->shared_area; 1182 result = B_OK; 1183 } 1184 break; 1185 } 1186 1187 case NV_GET_PCI: 1188 { 1189 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1190 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1191 pci_info *pcii = &(di->pcii); 1192 gsp->value = get_pci(gsp->offset, gsp->size); 1193 result = B_OK; 1194 } 1195 break; 1196 } 1197 1198 case NV_SET_PCI: 1199 { 1200 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1201 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1202 pci_info *pcii = &(di->pcii); 1203 set_pci(gsp->offset, gsp->size, gsp->value); 1204 result = B_OK; 1205 } 1206 break; 1207 } 1208 1209 case NV_DEVICE_NAME: 1210 { 1211 nv_device_name *dn = (nv_device_name *)buf; 1212 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1213 strcpy(dn->name, di->name); 1214 result = B_OK; 1215 } 1216 break; 1217 } 1218 1219 case NV_RUN_INTERRUPTS: 1220 { 1221 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1222 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1223 vuint32 *regs = di->regs; 1224 if (!(vi->crtc)) { 1225 if (vi->do_it) { 1226 enable_vbi_crtc1(regs); 1227 } else { 1228 disable_vbi_crtc1(regs); 1229 } 1230 } else { 1231 if (vi->do_it) { 1232 enable_vbi_crtc2(regs); 1233 } else { 1234 disable_vbi_crtc2(regs); 1235 } 1236 } 1237 result = B_OK; 1238 } 1239 break; 1240 } 1241 1242 case NV_GET_NTH_AGP_INFO: 1243 { 1244 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1245 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1246 nai->exist = false; 1247 nai->agp_bus = false; 1248 if (agp_bus) { 1249 nai->agp_bus = true; 1250 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1251 nai->exist = true; 1252 } 1253 } 1254 result = B_OK; 1255 } 1256 break; 1257 } 1258 1259 case NV_ENABLE_AGP: 1260 { 1261 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1262 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1263 if (agp_bus) { 1264 nca->agp_bus = true; 1265 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1266 } else { 1267 nca->agp_bus = false; 1268 nca->cmd = 0; 1269 } 1270 result = B_OK; 1271 } 1272 break; 1273 } 1274 1275 case NV_ISA_OUT: 1276 { 1277 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1278 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1279 pci_info *pcii = &(di->pcii); 1280 1281 /* lock the driver: 1282 * no other graphics card may have ISA I/O enabled when we enter */ 1283 AQUIRE_BEN(pd->kernel); 1284 1285 /* enable ISA I/O access */ 1286 tmpUlong = get_pci(PCI_command, 2); 1287 tmpUlong |= PCI_command_io; 1288 set_pci(PCI_command, 2, tmpUlong); 1289 1290 if (io_isa->size == 1) 1291 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1292 else 1293 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1294 result = B_OK; 1295 1296 /* disable ISA I/O access */ 1297 tmpUlong = get_pci(PCI_command, 2); 1298 tmpUlong &= ~PCI_command_io; 1299 set_pci(PCI_command, 2, tmpUlong); 1300 1301 /* end of critical section */ 1302 RELEASE_BEN(pd->kernel); 1303 } 1304 break; 1305 } 1306 1307 case NV_ISA_IN: 1308 { 1309 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1310 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1311 pci_info *pcii = &(di->pcii); 1312 1313 /* lock the driver: 1314 * no other graphics card may have ISA I/O enabled when we enter */ 1315 AQUIRE_BEN(pd->kernel); 1316 1317 /* enable ISA I/O access */ 1318 tmpUlong = get_pci(PCI_command, 2); 1319 tmpUlong |= PCI_command_io; 1320 set_pci(PCI_command, 2, tmpUlong); 1321 1322 if (io_isa->size == 1) 1323 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1324 else 1325 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1326 result = B_OK; 1327 1328 /* disable ISA I/O access */ 1329 tmpUlong = get_pci(PCI_command, 2); 1330 tmpUlong &= ~PCI_command_io; 1331 set_pci(PCI_command, 2, tmpUlong); 1332 1333 /* end of critical section */ 1334 RELEASE_BEN(pd->kernel); 1335 } 1336 break; 1337 } 1338 } 1339 1340 return result; 1341 } 1342 1343 1344 // #pragma mark - driver API 1345 1346 1347 status_t 1348 init_hardware(void) 1349 { 1350 long index = 0; 1351 pci_info pcii; 1352 bool found = false; 1353 1354 /* choke if we can't find the PCI bus */ 1355 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1356 return B_ERROR; 1357 1358 /* choke if we can't find the ISA bus */ 1359 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1360 { 1361 put_module(B_PCI_MODULE_NAME); 1362 return B_ERROR; 1363 } 1364 1365 /* while there are more pci devices */ 1366 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1367 int vendor = 0; 1368 1369 /* if we match a supported vendor */ 1370 while (SupportedDevices[vendor].vendor) { 1371 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1372 uint16 *devices = SupportedDevices[vendor].devices; 1373 /* while there are more supported devices */ 1374 while (*devices) { 1375 /* if we match a supported device */ 1376 if (*devices == pcii.device_id ) { 1377 1378 found = true; 1379 goto done; 1380 } 1381 /* next supported device */ 1382 devices++; 1383 } 1384 } 1385 vendor++; 1386 } 1387 /* next pci_info struct, please */ 1388 index++; 1389 } 1390 1391 done: 1392 /* put away the module manager */ 1393 put_module(B_PCI_MODULE_NAME); 1394 return found ? B_OK : B_ERROR; 1395 } 1396 1397 1398 status_t 1399 init_driver(void) 1400 { 1401 void *settings; 1402 1403 // get driver/accelerant settings 1404 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1405 if (settings != NULL) { 1406 const char *item; 1407 char *end; 1408 uint32 value; 1409 1410 // for driver 1411 item = get_driver_parameter(settings, "accelerant", "", ""); 1412 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1413 strcpy (sSettings.accelerant, item); 1414 1415 item = get_driver_parameter(settings, "primary", "", ""); 1416 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1417 strcpy(sSettings.primary, item); 1418 1419 sSettings.dumprom = get_driver_boolean_parameter(settings, 1420 "dumprom", false, false); 1421 1422 // for accelerant 1423 item = get_driver_parameter(settings, "logmask", 1424 "0x00000000", "0x00000000"); 1425 value = strtoul(item, &end, 0); 1426 if (*end == '\0') 1427 sSettings.logmask = value; 1428 1429 item = get_driver_parameter(settings, "memory", "0", "0"); 1430 value = strtoul(item, &end, 0); 1431 if (*end == '\0') 1432 sSettings.memory = value; 1433 1434 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1435 value = strtoul(item, &end, 0); 1436 if (*end == '\0') 1437 sSettings.tv_output = value; 1438 1439 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1440 "hardcursor", true, true); 1441 sSettings.usebios = get_driver_boolean_parameter(settings, 1442 "usebios", true, true); 1443 sSettings.switchhead = get_driver_boolean_parameter(settings, 1444 "switchhead", false, false); 1445 sSettings.force_pci = get_driver_boolean_parameter(settings, 1446 "force_pci", false, false); 1447 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1448 "unhide_fw", false, false); 1449 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1450 "pgm_panel", false, false); 1451 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1452 "dma_acc", true, true); 1453 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1454 "vga_on_tv", false, false); 1455 sSettings.force_sync = get_driver_boolean_parameter(settings, 1456 "force_sync", false, false); 1457 sSettings.force_ws = get_driver_boolean_parameter(settings, 1458 "force_ws", false, false); 1459 sSettings.block_acc = get_driver_boolean_parameter(settings, 1460 "block_acc", false, false); 1461 1462 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1463 value = strtoul(item, &end, 0); 1464 if (*end == '\0') 1465 sSettings.gpu_clk = value; 1466 1467 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1468 value = strtoul(item, &end, 0); 1469 if (*end == '\0') 1470 sSettings.ram_clk = value; 1471 1472 unload_driver_settings(settings); 1473 } 1474 1475 /* get a handle for the pci bus */ 1476 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1477 return B_ERROR; 1478 1479 /* get a handle for the isa bus */ 1480 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1481 put_module(B_PCI_MODULE_NAME); 1482 return B_ERROR; 1483 } 1484 1485 /* get a handle for the agp bus if it exists */ 1486 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1487 1488 /* driver private data */ 1489 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1490 if (!pd) { 1491 put_module(B_PCI_MODULE_NAME); 1492 return B_ERROR; 1493 } 1494 /* initialize the benaphore */ 1495 INIT_BEN(pd->kernel); 1496 /* find all of our supported devices */ 1497 probe_devices(); 1498 return B_OK; 1499 } 1500 1501 1502 const char ** 1503 publish_devices(void) 1504 { 1505 /* return the list of supported devices */ 1506 return (const char **)pd->device_names; 1507 } 1508 1509 1510 device_hooks * 1511 find_device(const char *name) 1512 { 1513 int index = 0; 1514 while (pd->device_names[index]) { 1515 if (strcmp(name, pd->device_names[index]) == 0) 1516 return &graphics_device_hooks; 1517 index++; 1518 } 1519 return NULL; 1520 1521 } 1522 1523 1524 void 1525 uninit_driver(void) 1526 { 1527 /* free the driver data */ 1528 DELETE_BEN(pd->kernel); 1529 free(pd); 1530 pd = NULL; 1531 1532 /* put the pci module away */ 1533 put_module(B_PCI_MODULE_NAME); 1534 put_module(B_ISA_MODULE_NAME); 1535 1536 /* put the agp module away if it's there */ 1537 if (agp_bus) 1538 put_module(B_AGP_GART_MODULE_NAME); 1539 } 1540 1541