1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-6/2009. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_gart_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 109 0x0041, /* Nvidia GeForce FX 6800 */ 110 0x0042, /* Nvidia GeForce FX 6800LE */ 111 0x0043, /* Nvidia GeForce 6800 XE */ 112 0x0045, /* Nvidia GeForce FX 6800 GT */ 113 0x0046, /* Nvidia GeForce FX 6800 GT */ 114 0x0047, /* Nvidia GeForce 6800 GS */ 115 0x0048, /* Nvidia GeForce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia GeForce 6800 GS */ 126 0x00c1, /* Nvidia GeForce FX 6800 */ 127 0x00c2, /* Nvidia GeForce FX 6800LE */ 128 0x00c3, /* Nvidia GeForce FX 6800 XT */ 129 0x00c8, /* Nvidia GeForce FX 6800 Go */ 130 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 137 0x00f3, /* Nvidia GeForce 6200 */ 138 0x00f4, /* Nvidia GeForce 6600 LE */ 139 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia GeForce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 149 0x0100, /* Nvidia GeForce256 SDR */ 150 0x0101, /* Nvidia GeForce256 DDR */ 151 0x0102, /* Nvidia GeForce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia GeForce2 MX/MX400 */ 154 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia GeForce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia GeForce FX 6600 GT */ 158 0x0141, /* Nvidia GeForce FX 6600 */ 159 0x0142, /* Nvidia GeForce FX 6600LE */ 160 0x0143, /* Nvidia GeForce 6600 VE */ 161 0x0144, /* Nvidia GeForce FX 6600 Go */ 162 0x0145, /* Nvidia GeForce FX 6610 XL */ 163 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia GeForce FX 6700 XL */ 165 0x0148, /* Nvidia GeForce FX 6600 Go */ 166 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia GeForce2 GTS/Pro */ 173 0x0151, /* Nvidia GeForce2 Ti DDR */ 174 0x0152, /* Nvidia GeForce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia GeForce 6500 Go */ 177 0x0161, /* Nvidia GeForce 6200 TurboCache */ 178 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 179 0x0163, /* Nvidia GeForce 6200LE */ 180 0x0164, /* Nvidia GeForce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia GeForce 6400 Go */ 183 0x0167, /* Nvidia GeForce 6200 Go */ 184 0x0168, /* Nvidia GeForce 6400 Go */ 185 0x0169, /* Nvidia GeForce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia GeForce4 MX 460 */ 192 0x0171, /* Nvidia GeForce4 MX 440 */ 193 0x0172, /* Nvidia GeForce4 MX 420 */ 194 0x0173, /* Nvidia GeForce4 MX 440SE */ 195 0x0174, /* Nvidia GeForce4 440 Go */ 196 0x0175, /* Nvidia GeForce4 420 Go */ 197 0x0176, /* Nvidia GeForce4 420 Go 32M */ 198 0x0177, /* Nvidia GeForce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia GeForce4 410 Go 16M */ 204 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia GeForce4 448 Go */ 209 0x0187, /* Nvidia GeForce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia GeForce4 448 Go */ 216 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 217 0x01d1, /* Nvidia GeForce 7300 LE */ 218 0x01d3, /* Nvidia GeForce 7300 SE */ 219 0x01d7, /* Nvidia Quadro NVS 110M/GeForce 7300 Go */ 220 0x01d8, /* Nvidia GeForce 7400 GO */ 221 0x01dd, /* Nvidia GeForce 7500 LE */ 222 0x01df, /* Nvidia GeForce 7300 GS */ 223 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 224 0x0200, /* Nvidia GeForce3 */ 225 0x0201, /* Nvidia GeForce3 Ti 200 */ 226 0x0202, /* Nvidia GeForce3 Ti 500 */ 227 0x0203, /* Nvidia Quadro DCC */ 228 0x0211, /* Nvidia GeForce FX 6800 */ 229 0x0212, /* Nvidia GeForce FX 6800LE */ 230 0x0215, /* Nvidia GeForce FX 6800 GT */ 231 0x0218, /* Nvidia GeForce 6800 XT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 239 0x0244, /* Nvidia GeForce Go 6150 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / GeForce 6150LE */ 241 0x0250, /* Nvidia GeForce4 Ti 4600 */ 242 0x0251, /* Nvidia GeForce4 Ti 4400 */ 243 0x0252, /* Nvidia GeForce4 Ti 4600 */ 244 0x0253, /* Nvidia GeForce4 Ti 4200 */ 245 0x0258, /* Nvidia Quadro4 900 XGL */ 246 0x0259, /* Nvidia Quadro4 750 XGL */ 247 0x025b, /* Nvidia Quadro4 700 XGL */ 248 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 249 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 250 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 251 0x0286, /* Nvidia GeForce4 4200 Go */ 252 0x0288, /* Nvidia Quadro4 980 XGL */ 253 0x0289, /* Nvidia Quadro4 780 XGL */ 254 0x028c, /* Nvidia Quadro4 700 GoGL */ 255 0x0290, /* Nvidia GeForce 7900 GTX */ 256 0x0291, /* Nvidia GeForce 7900 GT */ 257 0x0293, /* Nvidia GeForce 7900 GX2 */ 258 0x0294, /* Nvidia GeForce 7950 GX2 */ 259 0x0295, /* Nvidia GeForce 7950 GT */ 260 0x0298, /* Nvidia GeForce Go 7900 GS */ 261 0x0299, /* Nvidia GeForce Go 7900 GTX */ 262 0x029c, /* Nvidia Quadro FX 5500 */ 263 0x029f, /* Nvidia Quadro FX 4500 X2 */ 264 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 265 0x02e1, /* Nvidia GeForce 7600 GS */ 266 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 267 0x0302, /* Nvidia GeForce FX 5800 */ 268 0x0308, /* Nvidia Quadro FX 2000 */ 269 0x0309, /* Nvidia Quadro FX 1000 */ 270 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 271 0x0312, /* Nvidia GeForce FX 5600 */ 272 0x0313, /* Nvidia unknown FX */ 273 0x0314, /* Nvidia GeForce FX 5600XT */ 274 0x0316, /* Nvidia unknown FX Go */ 275 0x0317, /* Nvidia unknown FX Go */ 276 0x031a, /* Nvidia GeForce FX 5600 Go */ 277 0x031b, /* Nvidia GeForce FX 5650 Go */ 278 0x031c, /* Nvidia Quadro FX 700 Go */ 279 0x031d, /* Nvidia unknown FX Go */ 280 0x031e, /* Nvidia unknown FX Go */ 281 0x031f, /* Nvidia unknown FX Go */ 282 0x0320, /* Nvidia GeForce FX 5200 */ 283 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 284 0x0322, /* Nvidia GeForce FX 5200 */ 285 0x0323, /* Nvidia GeForce FX 5200LE */ 286 0x0324, /* Nvidia GeForce FX 5200 Go */ 287 0x0325, /* Nvidia GeForce FX 5250 Go */ 288 0x0326, /* Nvidia GeForce FX 5500 */ 289 0x0327, /* Nvidia GeForce FX 5100 */ 290 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 291 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 292 0x032a, /* Nvidia Quadro NVS 280 PCI */ 293 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 294 0x032c, /* Nvidia GeForce FX 5300 Go */ 295 0x032d, /* Nvidia GeForce FX 5100 Go */ 296 0x032e, /* Nvidia unknown FX Go */ 297 0x032f, /* Nvidia unknown FX Go */ 298 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 299 0x0331, /* Nvidia GeForce FX 5900 */ 300 0x0332, /* Nvidia GeForce FX 5900 XT */ 301 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 302 0x0334, /* Nvidia GeForce FX 5900 ZT */ 303 0x0338, /* Nvidia Quadro FX 3000 */ 304 0x033f, /* Nvidia Quadro FX 700 */ 305 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 306 0x0342, /* Nvidia GeForce FX 5700 */ 307 0x0343, /* Nvidia GeForce FX 5700LE */ 308 0x0344, /* Nvidia GeForce FX 5700VE */ 309 0x0345, /* Nvidia unknown FX */ 310 0x0347, /* Nvidia GeForce FX 5700 Go */ 311 0x0348, /* Nvidia GeForce FX 5700 Go */ 312 0x0349, /* Nvidia unknown FX Go */ 313 0x034b, /* Nvidia unknown FX Go */ 314 0x034c, /* Nvidia Quadro FX 1000 Go */ 315 0x034e, /* Nvidia Quadro FX 1100 */ 316 0x034f, /* Nvidia unknown FX */ 317 0x0391, /* Nvidia GeForce 7600 GT */ 318 0x0392, /* Nvidia GeForce 7600 GS */ 319 0x0393, /* Nvidia GeForce 7300 GT */ 320 0x0394, /* Nvidia GeForce 7600 LE */ 321 0x0398, /* Nvidia GeForce 7600 GO */ 322 0x03d0, /* Nvidia GeForce 6100 nForce 430 */ 323 0x03d1, /* Nvidia GeForce 6100 nForce 405 */ 324 0x03d2, /* Nvidia GeForce 6100 nForce 400 */ 325 0 326 }; 327 328 static uint16 elsa_device_list[] = { 329 0x0c60, /* Elsa Gladiac Geforce2 MX */ 330 0 331 }; 332 333 static uint16 nvstbsgs_device_list[] = { 334 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 335 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 336 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 337 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 338 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 339 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 340 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 341 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 342 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 343 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 344 0 345 }; 346 347 static uint16 varisys_device_list[] = { 348 0x3503, /* Varisys GeForce4 MX440 */ 349 0x3505, /* Varisys GeForce4 Ti 4200 */ 350 0 351 }; 352 353 static struct { 354 uint16 vendor; 355 uint16 *devices; 356 } SupportedDevices[] = { 357 {VENDOR_ID_NVIDIA, nvidia_device_list}, 358 {VENDOR_ID_ELSA, elsa_device_list}, 359 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 360 {VENDOR_ID_VARISYS, varisys_device_list}, 361 {0x0000, NULL} 362 }; 363 364 static nv_settings sSettings = { // see comments in nvidia.settings 365 /* for driver */ 366 DRIVER_PREFIX ".accelerant", 367 "none", // primary 368 false, // dumprom 369 /* for accelerant */ 370 0x00000000, // logmask 371 0, // memory 372 0, // tv_output 373 true, // usebios 374 true, // hardcursor 375 false, // switchhead 376 false, // force_pci 377 false, // unhide_fw 378 false, // pgm_panel 379 true, // dma_acc 380 false, // vga_on_tv 381 false, // force_sync 382 false, // force_ws 383 false, // block_acc 384 0, // gpu_clk 385 0, // ram_clk 386 }; 387 388 389 static void 390 dumprom(void *rom, uint32 size, pci_info pcii) 391 { 392 int fd; 393 uint32 cnt; 394 char fname[64]; 395 396 /* determine the romfile name: we need split-up per card in the system */ 397 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 398 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 399 400 fd = open (fname, O_WRONLY | O_CREAT, 0666); 401 if (fd < 0) return; 402 403 /* apparantly max. 32kb may be written at once; 404 * the ROM size is a multiple of that anyway. */ 405 for (cnt = 0; (cnt < size); cnt += 32768) 406 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 407 close (fd); 408 } 409 410 411 /*! return 1 if vblank interrupt has occured */ 412 static int 413 caused_vbi_crtc1(vuint32 * regs) 414 { 415 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 416 } 417 418 419 /*! clear the vblank interrupt */ 420 static void 421 clear_vbi_crtc1(vuint32 * regs) 422 { 423 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 424 } 425 426 427 static void 428 enable_vbi_crtc1(vuint32 * regs) 429 { 430 /* clear the vblank interrupt */ 431 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 432 /* enable nVidia interrupt source vblank */ 433 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 434 /* enable nVidia interrupt system hardware (b0-1) */ 435 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 436 } 437 438 439 static void 440 disable_vbi_crtc1(vuint32 * regs) 441 { 442 /* disable nVidia interrupt source vblank */ 443 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 444 /* clear the vblank interrupt */ 445 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 446 } 447 448 449 /*! return 1 if vblank interrupt has occured */ 450 static int 451 caused_vbi_crtc2(vuint32 * regs) 452 { 453 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 454 } 455 456 457 /*! clear the vblank interrupt */ 458 static void 459 clear_vbi_crtc2(vuint32 * regs) 460 { 461 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 462 } 463 464 465 static void 466 enable_vbi_crtc2(vuint32 * regs) 467 { 468 /* clear the vblank interrupt */ 469 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 470 /* enable nVidia interrupt source vblank */ 471 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 472 /* enable nVidia interrupt system hardware (b0-1) */ 473 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 474 } 475 476 477 static void 478 disable_vbi_crtc2(vuint32 * regs) 479 { 480 /* disable nVidia interrupt source vblank */ 481 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 482 /* clear the vblank interrupt */ 483 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 484 } 485 486 487 //fixme: 488 //dangerous code, on singlehead cards better not try accessing secondary head 489 //registers (card might react in unpredictable ways, though there's only a small 490 //chance we actually run into this). 491 //fix requires (some) card recognition code to be moved from accelerant to 492 //kerneldriver... 493 static void 494 disable_vbi_all(vuint32 * regs) 495 { 496 /* disable nVidia interrupt source vblank */ 497 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 498 /* clear the vblank interrupt */ 499 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 500 501 /* disable nVidia interrupt source vblank */ 502 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 503 /* clear the vblank interrupt */ 504 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 505 506 /* disable nVidia interrupt system hardware (b0-1) */ 507 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 508 } 509 510 511 static status_t 512 map_device(device_info *di) 513 { 514 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 515 shared_info *si = di->si; 516 uint32 tmpUlong, tmpROMshadow; 517 pci_info *pcii = &(di->pcii); 518 system_info sysinfo; 519 520 /* variables for making copy of ROM */ 521 uint8* rom_temp; 522 area_id rom_area = -1; 523 524 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 525 int registers = 0; 526 int frame_buffer = 1; 527 528 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 529 tmpUlong = get_pci(PCI_command, 2); 530 /* enable PCI access */ 531 tmpUlong |= PCI_command_memory; 532 /* enable busmastering */ 533 tmpUlong |= PCI_command_master; 534 /* disable ISA I/O access */ 535 tmpUlong &= ~PCI_command_io; 536 set_pci(PCI_command, 2, tmpUlong); 537 538 /*work out which version of BeOS is running*/ 539 get_system_info(&sysinfo); 540 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 541 { 542 si->use_clone_bugfix = 1; 543 } 544 else 545 { 546 si->use_clone_bugfix = 0; 547 } 548 549 /* work out a name for the register mapping */ 550 sprintf(buffer, DEVICE_FORMAT " regs", 551 di->pcii.vendor_id, di->pcii.device_id, 552 di->pcii.bus, di->pcii.device, di->pcii.function); 553 554 /* get a virtual memory address for the registers*/ 555 si->regs_area = map_physical_memory( 556 buffer, 557 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 558 (void *) di->pcii.u.h0.base_registers_pci[registers], 559 di->pcii.u.h0.base_register_sizes[registers], 560 B_ANY_KERNEL_ADDRESS, 561 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 562 (void **)&(di->regs)); 563 si->clone_bugfix_regs = (uint32 *) di->regs; 564 565 /* if mapping registers to vmem failed then pass on error */ 566 if (si->regs_area < 0) return si->regs_area; 567 568 /* work out a name for the ROM mapping*/ 569 sprintf(buffer, DEVICE_FORMAT " rom", 570 di->pcii.vendor_id, di->pcii.device_id, 571 di->pcii.bus, di->pcii.device, di->pcii.function); 572 573 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 574 /* warning: 575 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 576 * NV18, NV28 and NV34 keep working. 577 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 578 * however the actual ROM content (so the used part) is intact (confirmed). */ 579 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 580 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 581 set_pci(NVCFG_ROMSHADOW, 4, 0); 582 583 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 584 tmpUlong = get_pci(PCI_rom_base, 4); 585 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 586 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 587 //legacy space will get us into trouble if we aren't the primary graphics card!! 588 //(as legacy space always has the primary card's ROM 'mapped'!) 589 if (tmpUlong) { 590 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 591 tmpUlong |= 0x00000001; 592 set_pci(PCI_rom_base, 4, tmpUlong); 593 594 rom_area = map_physical_memory( 595 buffer, 596 (void *)di->pcii.u.h0.rom_base_pci, 597 di->pcii.u.h0.rom_size, 598 B_ANY_KERNEL_ADDRESS, 599 B_READ_AREA, 600 (void **)&(rom_temp) 601 ); 602 603 /* check if we got the BIOS and signature (might fail on laptops..) */ 604 if (rom_area >= 0) { 605 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 606 /* apparantly no ROM is mapped here */ 607 delete_area(rom_area); 608 rom_area = -1; 609 /* force using ISA legacy map as fall-back */ 610 tmpUlong = 0x00000000; 611 } 612 } else { 613 /* mapping failed: force using ISA legacy map as fall-back */ 614 tmpUlong = 0x00000000; 615 } 616 } 617 618 if (!tmpUlong) { 619 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 620 rom_area = map_physical_memory(buffer, (void *)0x000c0000, 621 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 622 } 623 624 /* if mapping ROM to vmem failed then clean up and pass on error */ 625 if (rom_area < 0) { 626 delete_area(si->regs_area); 627 si->regs_area = -1; 628 return rom_area; 629 } 630 631 /* dump ROM to file if selected in nvidia.settings 632 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 633 if (sSettings.dumprom) 634 dumprom(rom_temp, 65536, di->pcii); 635 636 /* make a copy of ROM for future reference */ 637 memcpy(si->rom_mirror, rom_temp, 65536); 638 639 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 640 tmpUlong = get_pci(PCI_rom_base, 4); 641 tmpUlong &= 0xfffffffe; 642 set_pci(PCI_rom_base, 4, tmpUlong); 643 delete_area(rom_area); 644 645 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 646 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 647 648 /* work out a name for the framebuffer mapping*/ 649 sprintf(buffer, DEVICE_FORMAT " framebuffer", 650 di->pcii.vendor_id, di->pcii.device_id, 651 di->pcii.bus, di->pcii.device, di->pcii.function); 652 653 /* map the framebuffer into vmem, using Write Combining*/ 654 si->fb_area = map_physical_memory(buffer, 655 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 656 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 657 di->pcii.u.h0.base_register_sizes[frame_buffer], 658 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 659 B_READ_AREA | B_WRITE_AREA, 660 &(si->framebuffer)); 661 662 /*if failed with write combining try again without*/ 663 if (si->fb_area < 0) { 664 si->fb_area = map_physical_memory(buffer, 665 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 666 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 667 di->pcii.u.h0.base_register_sizes[frame_buffer], 668 B_ANY_KERNEL_BLOCK_ADDRESS, 669 B_READ_AREA | B_WRITE_AREA, 670 &(si->framebuffer)); 671 } 672 673 /* if there was an error, delete our other areas and pass on error*/ 674 if (si->fb_area < 0) { 675 delete_area(si->regs_area); 676 si->regs_area = -1; 677 return si->fb_area; 678 } 679 680 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 681 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 682 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 683 684 // remember settings for use here and in accelerant 685 si->settings = sSettings; 686 687 /* in any case, return the result */ 688 return si->fb_area; 689 } 690 691 692 static void 693 unmap_device(device_info *di) 694 { 695 shared_info *si = di->si; 696 uint32 tmpUlong; 697 pci_info *pcii = &(di->pcii); 698 699 /* disable memory mapped IO */ 700 tmpUlong = get_pci(PCI_command, 4); 701 tmpUlong &= 0xfffffffc; 702 set_pci(PCI_command, 4, tmpUlong); 703 /* delete the areas */ 704 if (si->regs_area >= 0) 705 delete_area(si->regs_area); 706 if (si->fb_area >= 0) 707 delete_area(si->fb_area); 708 si->regs_area = si->fb_area = -1; 709 si->framebuffer = NULL; 710 di->regs = NULL; 711 } 712 713 714 static void 715 probe_devices(void) 716 { 717 uint32 pci_index = 0; 718 uint32 count = 0; 719 device_info *di = pd->di; 720 char tmp_name[B_OS_NAME_LENGTH]; 721 722 /* while there are more pci devices */ 723 while (count < MAX_DEVICES 724 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 725 int vendor = 0; 726 727 /* if we match a supported vendor */ 728 while (SupportedDevices[vendor].vendor) { 729 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 730 uint16 *devices = SupportedDevices[vendor].devices; 731 /* while there are more supported devices */ 732 while (*devices) { 733 /* if we match a supported device */ 734 if (*devices == di->pcii.device_id ) { 735 /* publish the device name */ 736 sprintf(tmp_name, DEVICE_FORMAT, 737 di->pcii.vendor_id, di->pcii.device_id, 738 di->pcii.bus, di->pcii.device, di->pcii.function); 739 /* tweak the exported name to show first in the alphabetically ordered /dev/ 740 * hierarchy folder, so the system will use it as primary adaptor if requested 741 * via nvidia.settings. */ 742 if (strcmp(tmp_name, sSettings.primary) == 0) 743 sprintf(tmp_name, "-%s", sSettings.primary); 744 /* add /dev/ hierarchy path */ 745 sprintf(di->name, "graphics/%s", tmp_name); 746 /* remember the name */ 747 pd->device_names[count] = di->name; 748 /* mark the driver as available for R/W open */ 749 di->is_open = 0; 750 /* mark areas as not yet created */ 751 di->shared_area = -1; 752 /* mark pointer to shared data as invalid */ 753 di->si = NULL; 754 /* inc pointer to device info */ 755 di++; 756 /* inc count */ 757 count++; 758 /* break out of these while loops */ 759 goto next_device; 760 } 761 /* next supported device */ 762 devices++; 763 } 764 } 765 vendor++; 766 } 767 next_device: 768 /* next pci_info struct, please */ 769 pci_index++; 770 } 771 /* propagate count */ 772 pd->count = count; 773 /* terminate list of device names with a null pointer */ 774 pd->device_names[pd->count] = NULL; 775 } 776 777 778 static uint32 779 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 780 { 781 uint32 handled = B_HANDLED_INTERRUPT; 782 /* release the vblank semaphore */ 783 if (si->vblank >= 0) { 784 int32 blocked; 785 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 786 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 787 handled = B_INVOKE_SCHEDULER; 788 } 789 } 790 return handled; 791 } 792 793 794 static int32 795 nv_interrupt(void *data) 796 { 797 int32 handled = B_UNHANDLED_INTERRUPT; 798 device_info *di = (device_info *)data; 799 shared_info *si = di->si; 800 int32 *flags = &(si->flags); 801 vuint32 *regs; 802 803 /* is someone already handling an interrupt for this device? */ 804 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 805 806 /* get regs */ 807 regs = di->regs; 808 809 /* was it a VBI? */ 810 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 811 if (si->ps.secondary_head) { 812 //fixme: 813 //rewrite once we use one driver instance 'per head' (instead of 'per card') 814 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 815 /* clear the interrupt(s) */ 816 clear_vbi_crtc1(regs); 817 clear_vbi_crtc2(regs); 818 /* release the semaphore */ 819 handled = thread_interrupt_work(flags, regs, si); 820 } 821 } else { 822 if (caused_vbi_crtc1(regs)) { 823 /* clear the interrupt */ 824 clear_vbi_crtc1(regs); 825 /* release the semaphore */ 826 handled = thread_interrupt_work(flags, regs, si); 827 } 828 } 829 830 /* note that we're not in the handler any more */ 831 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 832 833 exit0: 834 return handled; 835 } 836 837 838 // #pragma mark - device hooks 839 840 841 static status_t 842 open_hook(const char* name, uint32 flags, void** cookie) 843 { 844 int32 index = 0; 845 device_info *di; 846 shared_info *si; 847 thread_id thid; 848 thread_info thinfo; 849 status_t result = B_OK; 850 char shared_name[B_OS_NAME_LENGTH]; 851 physical_entry map[1]; 852 size_t net_buf_size; 853 void *unaligned_dma_buffer; 854 855 /* find the device name in the list of devices */ 856 /* we're never passed a name we didn't publish */ 857 while (pd->device_names[index] 858 && (strcmp(name, pd->device_names[index]) != 0)) 859 index++; 860 861 /* for convienience */ 862 di = &(pd->di[index]); 863 864 /* make sure no one else has write access to the common data */ 865 AQUIRE_BEN(pd->kernel); 866 867 /* if it's already open for writing */ 868 if (di->is_open) { 869 /* mark it open another time */ 870 goto mark_as_open; 871 } 872 /* create the shared_info area */ 873 sprintf(shared_name, DEVICE_FORMAT " shared", 874 di->pcii.vendor_id, di->pcii.device_id, 875 di->pcii.bus, di->pcii.device, di->pcii.function); 876 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 877 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 878 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 879 B_USER_CLONEABLE_AREA); 880 if (di->shared_area < 0) { 881 /* return the error */ 882 result = di->shared_area; 883 goto done; 884 } 885 886 /* save a few dereferences */ 887 si = di->si; 888 889 /* create the DMA command buffer area */ 890 //fixme? for R4.5 a workaround for cloning would be needed! 891 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 892 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 893 /* create the area that will hold the DMA command buffer */ 894 si->unaligned_dma_area = 895 create_area("NV DMA cmd buffer", 896 (void **)&unaligned_dma_buffer, 897 B_ANY_KERNEL_ADDRESS, 898 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 899 B_CONTIGUOUS, /* GPU always needs access */ 900 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 901 /* on error, abort */ 902 if (si->unaligned_dma_area < 0) 903 { 904 /* free the already created shared_info area, and return the error */ 905 result = si->unaligned_dma_area; 906 goto free_shared; 907 } 908 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 909 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 910 * even on older CPU's. */ 911 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 912 si->dma_buffer_pci = (void*) 913 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 914 915 /* map the net DMA command buffer into vmem, using Write Combining */ 916 si->dma_area = map_physical_memory( 917 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 918 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 919 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 920 /* if failed with write combining try again without */ 921 if (si->dma_area < 0) { 922 si->dma_area = map_physical_memory( 923 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 924 B_ANY_KERNEL_BLOCK_ADDRESS, 925 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 926 } 927 /* if there was an error, delete our other areas and pass on error*/ 928 if (si->dma_area < 0) 929 { 930 /* free the already created areas, and return the error */ 931 result = si->dma_area; 932 goto free_shared_and_uadma; 933 } 934 935 /* save the vendor and device IDs */ 936 si->vendor_id = di->pcii.vendor_id; 937 si->device_id = di->pcii.device_id; 938 si->revision = di->pcii.revision; 939 si->bus = di->pcii.bus; 940 si->device = di->pcii.device; 941 si->function = di->pcii.function; 942 943 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 944 si->accelerant_in_use = false; 945 /* preset singlehead card to prevent early INT routine calls (once installed) to 946 * wrongly identify the INT request coming from us! */ 947 si->ps.secondary_head = false; 948 949 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 950 * unified memory architecture (UMA) */ 951 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 952 { 953 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 954 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 955 si->ps.memory_size = 1024 * 1024 * 956 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 957 /* last 64kB RAM is used for the BIOS (or something else?) */ 958 si->ps.memory_size -= (64 * 1024); 959 break; 960 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 961 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 962 si->ps.memory_size = 1024 * 1024 * 963 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 964 /* last 64kB RAM is used for the BIOS (or something else?) */ 965 si->ps.memory_size -= (64 * 1024); 966 break; 967 default: 968 /* all other cards have own RAM: the amount of which is determined in the 969 * accelerant. */ 970 break; 971 } 972 973 /* map the device */ 974 result = map_device(di); 975 if (result < 0) goto free_shared_and_alldma; 976 977 /* we will be returning OK status for sure now */ 978 result = B_OK; 979 980 /* disable and clear any pending interrupts */ 981 //fixme: 982 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 983 disable_vbi_all(di->regs); 984 985 /* preset we can't use INT related functions */ 986 si->ps.int_assigned = false; 987 988 /* create a semaphore for vertical blank management */ 989 si->vblank = create_sem(0, di->name); 990 if (si->vblank < 0) goto mark_as_open; 991 992 /* change the owner of the semaphores to the opener's team */ 993 /* this is required because apps can't aquire kernel semaphores */ 994 thid = find_thread(NULL); 995 get_thread_info(thid, &thinfo); 996 set_sem_owner(si->vblank, thinfo.team); 997 998 /* If there is a valid interrupt line assigned then set up interrupts */ 999 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1000 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1001 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1002 { 1003 /* delete the semaphore as it won't be used */ 1004 delete_sem(si->vblank); 1005 si->vblank = -1; 1006 } 1007 else 1008 { 1009 /* otherwise install our interrupt handler */ 1010 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1011 /* bail if we couldn't install the handler */ 1012 if (result != B_OK) 1013 { 1014 /* delete the semaphore as it won't be used */ 1015 delete_sem(si->vblank); 1016 si->vblank = -1; 1017 } 1018 else 1019 { 1020 /* inform accelerant(s) we can use INT related functions */ 1021 si->ps.int_assigned = true; 1022 } 1023 } 1024 1025 mark_as_open: 1026 /* mark the device open */ 1027 di->is_open++; 1028 1029 /* send the cookie to the opener */ 1030 *cookie = di; 1031 1032 goto done; 1033 1034 1035 free_shared_and_alldma: 1036 /* clean up our aligned DMA area */ 1037 delete_area(si->dma_area); 1038 si->dma_area = -1; 1039 si->dma_buffer = NULL; 1040 1041 free_shared_and_uadma: 1042 /* clean up our unaligned DMA area */ 1043 delete_area(si->unaligned_dma_area); 1044 si->unaligned_dma_area = -1; 1045 si->dma_buffer_pci = NULL; 1046 1047 free_shared: 1048 /* clean up our shared area */ 1049 delete_area(di->shared_area); 1050 di->shared_area = -1; 1051 di->si = NULL; 1052 1053 done: 1054 /* end of critical section */ 1055 RELEASE_BEN(pd->kernel); 1056 1057 /* all done, return the status */ 1058 return result; 1059 } 1060 1061 1062 static status_t 1063 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1064 { 1065 *len = 0; 1066 return B_NOT_ALLOWED; 1067 } 1068 1069 1070 static status_t 1071 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1072 { 1073 *len = 0; 1074 return B_NOT_ALLOWED; 1075 } 1076 1077 1078 static status_t 1079 close_hook(void* dev) 1080 { 1081 /* we don't do anything on close: there might be dup'd fd */ 1082 return B_NO_ERROR; 1083 } 1084 1085 1086 static status_t 1087 free_hook(void* dev) 1088 { 1089 device_info *di = (device_info *)dev; 1090 shared_info *si = di->si; 1091 vuint32 *regs = di->regs; 1092 1093 /* lock the driver */ 1094 AQUIRE_BEN(pd->kernel); 1095 1096 /* if opened multiple times, decrement the open count and exit */ 1097 if (di->is_open > 1) 1098 goto unlock_and_exit; 1099 1100 /* disable and clear any pending interrupts */ 1101 //fixme: 1102 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1103 disable_vbi_all(regs); 1104 1105 if (si->ps.int_assigned) { 1106 /* remove interrupt handler */ 1107 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1108 1109 /* delete the semaphores, ignoring any errors ('cause the owning 1110 team may have died on us) */ 1111 delete_sem(si->vblank); 1112 si->vblank = -1; 1113 } 1114 1115 /* free regs and framebuffer areas */ 1116 unmap_device(di); 1117 1118 /* clean up our aligned DMA area */ 1119 delete_area(si->dma_area); 1120 si->dma_area = -1; 1121 si->dma_buffer = NULL; 1122 1123 /* clean up our unaligned DMA area */ 1124 delete_area(si->unaligned_dma_area); 1125 si->unaligned_dma_area = -1; 1126 si->dma_buffer_pci = NULL; 1127 1128 /* clean up our shared area */ 1129 delete_area(di->shared_area); 1130 di->shared_area = -1; 1131 di->si = NULL; 1132 1133 unlock_and_exit: 1134 /* mark the device available */ 1135 di->is_open--; 1136 /* unlock the driver */ 1137 RELEASE_BEN(pd->kernel); 1138 /* all done */ 1139 return B_OK; 1140 } 1141 1142 1143 static status_t 1144 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1145 { 1146 device_info *di = (device_info *)dev; 1147 status_t result = B_DEV_INVALID_IOCTL; 1148 uint32 tmpUlong; 1149 1150 switch (msg) { 1151 /* the only PUBLIC ioctl */ 1152 case B_GET_ACCELERANT_SIGNATURE: 1153 { 1154 strcpy((char* )buf, sSettings.accelerant); 1155 result = B_OK; 1156 break; 1157 } 1158 1159 /* PRIVATE ioctl from here on */ 1160 case NV_GET_PRIVATE_DATA: 1161 { 1162 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1163 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1164 gpd->shared_info_area = di->shared_area; 1165 result = B_OK; 1166 } 1167 break; 1168 } 1169 1170 case NV_GET_PCI: 1171 { 1172 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1173 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1174 pci_info *pcii = &(di->pcii); 1175 gsp->value = get_pci(gsp->offset, gsp->size); 1176 result = B_OK; 1177 } 1178 break; 1179 } 1180 1181 case NV_SET_PCI: 1182 { 1183 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1184 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1185 pci_info *pcii = &(di->pcii); 1186 set_pci(gsp->offset, gsp->size, gsp->value); 1187 result = B_OK; 1188 } 1189 break; 1190 } 1191 1192 case NV_DEVICE_NAME: 1193 { 1194 nv_device_name *dn = (nv_device_name *)buf; 1195 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1196 strcpy(dn->name, di->name); 1197 result = B_OK; 1198 } 1199 break; 1200 } 1201 1202 case NV_RUN_INTERRUPTS: 1203 { 1204 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1205 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1206 vuint32 *regs = di->regs; 1207 if (!(vi->crtc)) { 1208 if (vi->do_it) { 1209 enable_vbi_crtc1(regs); 1210 } else { 1211 disable_vbi_crtc1(regs); 1212 } 1213 } else { 1214 if (vi->do_it) { 1215 enable_vbi_crtc2(regs); 1216 } else { 1217 disable_vbi_crtc2(regs); 1218 } 1219 } 1220 result = B_OK; 1221 } 1222 break; 1223 } 1224 1225 case NV_GET_NTH_AGP_INFO: 1226 { 1227 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1228 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1229 nai->exist = false; 1230 nai->agp_bus = false; 1231 if (agp_bus) { 1232 nai->agp_bus = true; 1233 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1234 nai->exist = true; 1235 } 1236 } 1237 result = B_OK; 1238 } 1239 break; 1240 } 1241 1242 case NV_ENABLE_AGP: 1243 { 1244 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1245 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1246 if (agp_bus) { 1247 nca->agp_bus = true; 1248 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1249 } else { 1250 nca->agp_bus = false; 1251 nca->cmd = 0; 1252 } 1253 result = B_OK; 1254 } 1255 break; 1256 } 1257 1258 case NV_ISA_OUT: 1259 { 1260 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1261 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1262 pci_info *pcii = &(di->pcii); 1263 1264 /* lock the driver: 1265 * no other graphics card may have ISA I/O enabled when we enter */ 1266 AQUIRE_BEN(pd->kernel); 1267 1268 /* enable ISA I/O access */ 1269 tmpUlong = get_pci(PCI_command, 2); 1270 tmpUlong |= PCI_command_io; 1271 set_pci(PCI_command, 2, tmpUlong); 1272 1273 if (io_isa->size == 1) 1274 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1275 else 1276 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1277 result = B_OK; 1278 1279 /* disable ISA I/O access */ 1280 tmpUlong = get_pci(PCI_command, 2); 1281 tmpUlong &= ~PCI_command_io; 1282 set_pci(PCI_command, 2, tmpUlong); 1283 1284 /* end of critical section */ 1285 RELEASE_BEN(pd->kernel); 1286 } 1287 break; 1288 } 1289 1290 case NV_ISA_IN: 1291 { 1292 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1293 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1294 pci_info *pcii = &(di->pcii); 1295 1296 /* lock the driver: 1297 * no other graphics card may have ISA I/O enabled when we enter */ 1298 AQUIRE_BEN(pd->kernel); 1299 1300 /* enable ISA I/O access */ 1301 tmpUlong = get_pci(PCI_command, 2); 1302 tmpUlong |= PCI_command_io; 1303 set_pci(PCI_command, 2, tmpUlong); 1304 1305 if (io_isa->size == 1) 1306 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1307 else 1308 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1309 result = B_OK; 1310 1311 /* disable ISA I/O access */ 1312 tmpUlong = get_pci(PCI_command, 2); 1313 tmpUlong &= ~PCI_command_io; 1314 set_pci(PCI_command, 2, tmpUlong); 1315 1316 /* end of critical section */ 1317 RELEASE_BEN(pd->kernel); 1318 } 1319 break; 1320 } 1321 } 1322 1323 return result; 1324 } 1325 1326 1327 // #pragma mark - driver API 1328 1329 1330 status_t 1331 init_hardware(void) 1332 { 1333 long index = 0; 1334 pci_info pcii; 1335 bool found = false; 1336 1337 /* choke if we can't find the PCI bus */ 1338 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1339 return B_ERROR; 1340 1341 /* choke if we can't find the ISA bus */ 1342 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1343 { 1344 put_module(B_PCI_MODULE_NAME); 1345 return B_ERROR; 1346 } 1347 1348 /* while there are more pci devices */ 1349 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1350 int vendor = 0; 1351 1352 /* if we match a supported vendor */ 1353 while (SupportedDevices[vendor].vendor) { 1354 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1355 uint16 *devices = SupportedDevices[vendor].devices; 1356 /* while there are more supported devices */ 1357 while (*devices) { 1358 /* if we match a supported device */ 1359 if (*devices == pcii.device_id ) { 1360 1361 found = true; 1362 goto done; 1363 } 1364 /* next supported device */ 1365 devices++; 1366 } 1367 } 1368 vendor++; 1369 } 1370 /* next pci_info struct, please */ 1371 index++; 1372 } 1373 1374 done: 1375 /* put away the module manager */ 1376 put_module(B_PCI_MODULE_NAME); 1377 return found ? B_OK : B_ERROR; 1378 } 1379 1380 1381 status_t 1382 init_driver(void) 1383 { 1384 void *settings; 1385 1386 // get driver/accelerant settings 1387 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1388 if (settings != NULL) { 1389 const char *item; 1390 char *end; 1391 uint32 value; 1392 1393 // for driver 1394 item = get_driver_parameter(settings, "accelerant", "", ""); 1395 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1396 strcpy (sSettings.accelerant, item); 1397 1398 item = get_driver_parameter(settings, "primary", "", ""); 1399 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1400 strcpy(sSettings.primary, item); 1401 1402 sSettings.dumprom = get_driver_boolean_parameter(settings, 1403 "dumprom", false, false); 1404 1405 // for accelerant 1406 item = get_driver_parameter(settings, "logmask", 1407 "0x00000000", "0x00000000"); 1408 value = strtoul(item, &end, 0); 1409 if (*end == '\0') 1410 sSettings.logmask = value; 1411 1412 item = get_driver_parameter(settings, "memory", "0", "0"); 1413 value = strtoul(item, &end, 0); 1414 if (*end == '\0') 1415 sSettings.memory = value; 1416 1417 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1418 value = strtoul(item, &end, 0); 1419 if (*end == '\0') 1420 sSettings.tv_output = value; 1421 1422 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1423 "hardcursor", false, false); 1424 sSettings.usebios = get_driver_boolean_parameter(settings, 1425 "usebios", false, false); 1426 sSettings.switchhead = get_driver_boolean_parameter(settings, 1427 "switchhead", false, false); 1428 sSettings.force_pci = get_driver_boolean_parameter(settings, 1429 "force_pci", false, false); 1430 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1431 "unhide_fw", false, false); 1432 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1433 "pgm_panel", false, false); 1434 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1435 "dma_acc", false, false); 1436 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1437 "vga_on_tv", false, false); 1438 sSettings.force_sync = get_driver_boolean_parameter(settings, 1439 "force_sync", false, false); 1440 sSettings.force_ws = get_driver_boolean_parameter(settings, 1441 "force_ws", false, false); 1442 sSettings.block_acc = get_driver_boolean_parameter(settings, 1443 "block_acc", false, false); 1444 1445 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1446 value = strtoul(item, &end, 0); 1447 if (*end == '\0') 1448 sSettings.gpu_clk = value; 1449 1450 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1451 value = strtoul(item, &end, 0); 1452 if (*end == '\0') 1453 sSettings.ram_clk = value; 1454 1455 unload_driver_settings(settings); 1456 } 1457 1458 /* get a handle for the pci bus */ 1459 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1460 return B_ERROR; 1461 1462 /* get a handle for the isa bus */ 1463 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1464 put_module(B_PCI_MODULE_NAME); 1465 return B_ERROR; 1466 } 1467 1468 /* get a handle for the agp bus if it exists */ 1469 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1470 1471 /* driver private data */ 1472 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1473 if (!pd) { 1474 put_module(B_PCI_MODULE_NAME); 1475 return B_ERROR; 1476 } 1477 /* initialize the benaphore */ 1478 INIT_BEN(pd->kernel); 1479 /* find all of our supported devices */ 1480 probe_devices(); 1481 return B_OK; 1482 } 1483 1484 1485 const char ** 1486 publish_devices(void) 1487 { 1488 /* return the list of supported devices */ 1489 return (const char **)pd->device_names; 1490 } 1491 1492 1493 device_hooks * 1494 find_device(const char *name) 1495 { 1496 int index = 0; 1497 while (pd->device_names[index]) { 1498 if (strcmp(name, pd->device_names[index]) == 0) 1499 return &graphics_device_hooks; 1500 index++; 1501 } 1502 return NULL; 1503 1504 } 1505 1506 1507 void 1508 uninit_driver(void) 1509 { 1510 /* free the driver data */ 1511 DELETE_BEN(pd->kernel); 1512 free(pd); 1513 pd = NULL; 1514 1515 /* put the pci module away */ 1516 put_module(B_PCI_MODULE_NAME); 1517 put_module(B_ISA_MODULE_NAME); 1518 1519 /* put the agp module away if it's there */ 1520 if (agp_bus) 1521 put_module(B_AGP_GART_MODULE_NAME); 1522 } 1523 1524