1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-6/2010. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <directories.h> 21 #include <driver_settings.h> 22 23 #include <stdlib.h> 24 #include <stdio.h> 25 #include <string.h> 26 27 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 28 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 29 30 #define MAX_DEVICES 8 31 32 #ifndef __HAIKU__ 33 # undef B_USER_CLONEABLE_AREA 34 # define B_USER_CLONEABLE_AREA 0 35 #endif 36 37 /* Tell the kernel what revision of the driver API we support */ 38 int32 api_version = B_CUR_DRIVER_API_VERSION; 39 40 /* these structures are private to the kernel driver */ 41 typedef struct device_info device_info; 42 43 typedef struct { 44 timer te; /* timer entry for add_timer() */ 45 device_info *di; /* pointer to the owning device */ 46 bigtime_t when_target; /* when we're supposed to wake up */ 47 } timer_info; 48 49 struct device_info { 50 uint32 is_open; /* a count of how many times the devices has been opened */ 51 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 52 shared_info *si; /* a pointer to the shared area, for convenience */ 53 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 54 pci_info pcii; /* a convenience copy of the pci info for this device */ 55 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 56 }; 57 58 typedef struct { 59 uint32 count; /* number of devices actually found */ 60 benaphore kernel; /* for serializing opens/closes */ 61 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 62 device_info di[MAX_DEVICES]; /* device specific stuff */ 63 } DeviceData; 64 65 /* prototypes for our private functions */ 66 static status_t open_hook(const char* name, uint32 flags, void** cookie); 67 static status_t close_hook(void* dev); 68 static status_t free_hook(void* dev); 69 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 70 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 71 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 72 static status_t map_device(device_info *di); 73 static void unmap_device(device_info *di); 74 static void probe_devices(void); 75 static int32 nv_interrupt(void *data); 76 77 static DeviceData *pd; 78 static isa_module_info *isa_bus = NULL; 79 static pci_module_info *pci_bus = NULL; 80 static agp_gart_module_info *agp_bus = NULL; 81 static device_hooks graphics_device_hooks = { 82 open_hook, 83 close_hook, 84 free_hook, 85 control_hook, 86 read_hook, 87 write_hook, 88 NULL, 89 NULL, 90 NULL, 91 NULL 92 }; 93 94 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 95 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 96 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 97 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 98 99 static uint16 nvidia_device_list[] = { 100 0x0020, /* Nvidia TNT1 */ 101 0x0028, /* Nvidia TNT2 (pro) */ 102 0x0029, /* Nvidia TNT2 Ultra */ 103 0x002a, /* Nvidia TNT2 */ 104 0x002b, /* Nvidia TNT2 */ 105 0x002c, /* Nvidia Vanta (Lt) */ 106 0x002d, /* Nvidia TNT2-M64 (Pro) */ 107 0x002e, /* Nvidia NV06 Vanta */ 108 0x002f, /* Nvidia NV06 Vanta */ 109 0x0040, /* Nvidia Geforce FX 6800 Ultra */ 110 0x0041, /* Nvidia Geforce FX 6800 */ 111 0x0042, /* Nvidia Geforce FX 6800LE */ 112 0x0043, /* Nvidia Geforce 6800 XE */ 113 0x0045, /* Nvidia Geforce FX 6800 GT */ 114 0x0046, /* Nvidia Geforce FX 6800 GT */ 115 0x0047, /* Nvidia Geforce 6800 GS */ 116 0x0048, /* Nvidia Geforce FX 6800 XT */ 117 0x0049, /* Nvidia unknown FX */ 118 0x004d, /* Nvidia Quadro FX 4400 */ 119 0x004e, /* Nvidia Quadro FX 4000 */ 120 0x0091, /* Nvidia Geforce 7800 GTX PCIe */ 121 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 122 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 123 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 124 0x009d, /* Nvidia Quadro FX 4500 */ 125 0x00a0, /* Nvidia Aladdin TNT2 */ 126 0x00c0, /* Nvidia Geforce 6800 GS */ 127 0x00c1, /* Nvidia Geforce FX 6800 */ 128 0x00c2, /* Nvidia Geforce FX 6800LE */ 129 0x00c3, /* Nvidia Geforce FX 6800 XT */ 130 0x00c8, /* Nvidia Geforce FX 6800 Go */ 131 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */ 132 0x00cc, /* Nvidia Quadro FX 1400 Go */ 133 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 134 0x00ce, /* Nvidia Quadro FX 1400 */ 135 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */ 136 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */ 137 0x00f2, /* Nvidia Geforce FX 6600 AGP */ 138 0x00f3, /* Nvidia Geforce 6200 */ 139 0x00f4, /* Nvidia Geforce 6600 LE */ 140 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */ 141 0x00f6, /* Nvidia Geforce 6800 GS */ 142 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 143 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */ 144 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */ 145 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */ 146 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */ 147 0x00fd, /* Nvidia Quadro PCX PCIe */ 148 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 149 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */ 150 0x0100, /* Nvidia Geforce256 SDR */ 151 0x0101, /* Nvidia Geforce256 DDR */ 152 0x0102, /* Nvidia Geforce256 Ultra */ 153 0x0103, /* Nvidia Quadro */ 154 0x0110, /* Nvidia Geforce2 MX/MX400 */ 155 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */ 156 0x0112, /* Nvidia Geforce2 Go */ 157 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 158 0x0140, /* Nvidia Geforce FX 6600 GT */ 159 0x0141, /* Nvidia Geforce FX 6600 */ 160 0x0142, /* Nvidia Geforce FX 6600LE */ 161 0x0143, /* Nvidia Geforce 6600 VE */ 162 0x0144, /* Nvidia Geforce FX 6600 Go */ 163 0x0145, /* Nvidia Geforce FX 6610 XL */ 164 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */ 165 0x0147, /* Nvidia Geforce FX 6700 XL */ 166 0x0148, /* Nvidia Geforce FX 6600 Go */ 167 0x0149, /* Nvidia Geforce FX 6600 GT Go */ 168 0x014b, /* Nvidia unknown FX */ 169 0x014c, /* Nvidia Quadro FX 540 MXM */ 170 0x014d, /* Nvidia unknown FX */ 171 0x014e, /* Nvidia Quadro FX 540 */ 172 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */ 173 0x0150, /* Nvidia Geforce2 GTS/Pro */ 174 0x0151, /* Nvidia Geforce2 Ti DDR */ 175 0x0152, /* Nvidia Geforce2 Ultra */ 176 0x0153, /* Nvidia Quadro2 Pro */ 177 0x0160, /* Nvidia Geforce 6500 Go */ 178 0x0161, /* Nvidia Geforce 6200 TurboCache */ 179 0x0162, /* Nvidia Geforce 6200SE TurboCache */ 180 0x0163, /* Nvidia Geforce 6200LE */ 181 0x0164, /* Nvidia Geforce FX 6200 Go */ 182 0x0165, /* Nvidia Quadro FX NVS 285 */ 183 0x0166, /* Nvidia Geforce 6400 Go */ 184 0x0167, /* Nvidia Geforce 6200 Go */ 185 0x0168, /* Nvidia Geforce 6400 Go */ 186 0x0169, /* Nvidia Geforce 6250 Go */ 187 0x016a, /* Nvidia Geforce 7100 GS */ 188 0x016b, /* Nvidia unknown FX Go */ 189 0x016c, /* Nvidia unknown FX Go */ 190 0x016d, /* Nvidia unknown FX Go */ 191 0x016e, /* Nvidia unknown FX */ 192 0x0170, /* Nvidia Geforce4 MX 460 */ 193 0x0171, /* Nvidia Geforce4 MX 440 */ 194 0x0172, /* Nvidia Geforce4 MX 420 */ 195 0x0173, /* Nvidia Geforce4 MX 440SE */ 196 0x0174, /* Nvidia Geforce4 440 Go */ 197 0x0175, /* Nvidia Geforce4 420 Go */ 198 0x0176, /* Nvidia Geforce4 420 Go 32M */ 199 0x0177, /* Nvidia Geforce4 460 Go */ 200 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 201 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */ 202 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 203 0x017c, /* Nvidia Quadro4 500 GoGL */ 204 0x017d, /* Nvidia Geforce4 410 Go 16M */ 205 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */ 206 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */ 207 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */ 208 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */ 209 0x0186, /* Nvidia Geforce4 448 Go */ 210 0x0187, /* Nvidia Geforce4 488 Go */ 211 0x0188, /* Nvidia Quadro4 580 XGL */ 212 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */ 213 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 214 0x018b, /* Nvidia Quadro4 380 XGL */ 215 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 216 0x018d, /* Nvidia Geforce4 448 Go */ 217 0x01a0, /* Nvidia Geforce2 Integrated GPU */ 218 0x01d1, /* Nvidia Geforce 7300 LE */ 219 0x01d3, /* Nvidia Geforce 7300 SE */ 220 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */ 221 0x01d8, /* Nvidia Geforce 7400 GO */ 222 0x01dd, /* Nvidia Geforce 7500 LE */ 223 0x01df, /* Nvidia Geforce 7300 GS */ 224 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */ 225 0x0200, /* Nvidia Geforce3 */ 226 0x0201, /* Nvidia Geforce3 Ti 200 */ 227 0x0202, /* Nvidia Geforce3 Ti 500 */ 228 0x0203, /* Nvidia Quadro DCC */ 229 0x0211, /* Nvidia Geforce FX 6800 */ 230 0x0212, /* Nvidia Geforce FX 6800LE */ 231 0x0215, /* Nvidia Geforce FX 6800 GT */ 232 0x0218, /* Nvidia Geforce 6800 XT */ 233 0x0220, /* Nvidia unknown FX */ 234 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */ 235 0x0222, /* Nvidia unknown FX */ 236 0x0228, /* Nvidia unknown FX Go */ 237 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */ 238 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */ 239 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */ 240 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */ 241 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */ 242 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */ 243 0x0250, /* Nvidia Geforce4 Ti 4600 */ 244 0x0251, /* Nvidia Geforce4 Ti 4400 */ 245 0x0252, /* Nvidia Geforce4 Ti 4600 */ 246 0x0253, /* Nvidia Geforce4 Ti 4200 */ 247 0x0258, /* Nvidia Quadro4 900 XGL */ 248 0x0259, /* Nvidia Quadro4 750 XGL */ 249 0x025b, /* Nvidia Quadro4 700 XGL */ 250 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */ 251 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */ 252 0x0282, /* Nvidia Geforce4 Ti 4800SE */ 253 0x0286, /* Nvidia Geforce4 4200 Go */ 254 0x0288, /* Nvidia Quadro4 980 XGL */ 255 0x0289, /* Nvidia Quadro4 780 XGL */ 256 0x028c, /* Nvidia Quadro4 700 GoGL */ 257 0x0290, /* Nvidia Geforce 7900 GTX */ 258 0x0291, /* Nvidia Geforce 7900 GT */ 259 0x0293, /* Nvidia Geforce 7900 GX2 */ 260 0x0294, /* Nvidia Geforce 7950 GX2 */ 261 0x0295, /* Nvidia Geforce 7950 GT */ 262 0x0298, /* Nvidia Geforce Go 7900 GS */ 263 0x0299, /* Nvidia Geforce Go 7900 GTX */ 264 0x029c, /* Nvidia Quadro FX 5500 */ 265 0x029f, /* Nvidia Quadro FX 4500 X2 */ 266 0x02a0, /* Nvidia Geforce3 Integrated GPU */ 267 0x02e0, /* Nvidia Geforce 7600 GT */ 268 0x02e1, /* Nvidia Geforce 7600 GS */ 269 0x02e2, /* Nvidia Geforce 7300 GT */ 270 0x0301, /* Nvidia Geforce FX 5800 Ultra */ 271 0x0302, /* Nvidia Geforce FX 5800 */ 272 0x0308, /* Nvidia Quadro FX 2000 */ 273 0x0309, /* Nvidia Quadro FX 1000 */ 274 0x0311, /* Nvidia Geforce FX 5600 Ultra */ 275 0x0312, /* Nvidia Geforce FX 5600 */ 276 0x0313, /* Nvidia unknown FX */ 277 0x0314, /* Nvidia Geforce FX 5600XT */ 278 0x0316, /* Nvidia unknown FX Go */ 279 0x0317, /* Nvidia unknown FX Go */ 280 0x031a, /* Nvidia Geforce FX 5600 Go */ 281 0x031b, /* Nvidia Geforce FX 5650 Go */ 282 0x031c, /* Nvidia Quadro FX 700 Go */ 283 0x031d, /* Nvidia unknown FX Go */ 284 0x031e, /* Nvidia unknown FX Go */ 285 0x031f, /* Nvidia unknown FX Go */ 286 0x0320, /* Nvidia Geforce FX 5200 */ 287 0x0321, /* Nvidia Geforce FX 5200 Ultra */ 288 0x0322, /* Nvidia Geforce FX 5200 */ 289 0x0323, /* Nvidia Geforce FX 5200LE */ 290 0x0324, /* Nvidia Geforce FX 5200 Go */ 291 0x0325, /* Nvidia Geforce FX 5250 Go */ 292 0x0326, /* Nvidia Geforce FX 5500 */ 293 0x0327, /* Nvidia Geforce FX 5100 */ 294 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */ 295 0x0329, /* Nvidia Geforce FX 5200 (PPC) */ 296 0x032a, /* Nvidia Quadro NVS 280 PCI */ 297 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 298 0x032c, /* Nvidia Geforce FX 5300 Go */ 299 0x032d, /* Nvidia Geforce FX 5100 Go */ 300 0x032e, /* Nvidia unknown FX Go */ 301 0x032f, /* Nvidia unknown FX Go */ 302 0x0330, /* Nvidia Geforce FX 5900 Ultra */ 303 0x0331, /* Nvidia Geforce FX 5900 */ 304 0x0332, /* Nvidia Geforce FX 5900 XT */ 305 0x0333, /* Nvidia Geforce FX 5950 Ultra */ 306 0x0334, /* Nvidia Geforce FX 5900 ZT */ 307 0x0338, /* Nvidia Quadro FX 3000 */ 308 0x033f, /* Nvidia Quadro FX 700 */ 309 0x0341, /* Nvidia Geforce FX 5700 Ultra */ 310 0x0342, /* Nvidia Geforce FX 5700 */ 311 0x0343, /* Nvidia Geforce FX 5700LE */ 312 0x0344, /* Nvidia Geforce FX 5700VE */ 313 0x0345, /* Nvidia unknown FX */ 314 0x0347, /* Nvidia Geforce FX 5700 Go */ 315 0x0348, /* Nvidia Geforce FX 5700 Go */ 316 0x0349, /* Nvidia unknown FX Go */ 317 0x034b, /* Nvidia unknown FX Go */ 318 0x034c, /* Nvidia Quadro FX 1000 Go */ 319 0x034e, /* Nvidia Quadro FX 1100 */ 320 0x034f, /* Nvidia unknown FX */ 321 0x0391, /* Nvidia Geforce 7600 GT */ 322 0x0392, /* Nvidia Geforce 7600 GS */ 323 0x0393, /* Nvidia Geforce 7300 GT */ 324 0x0394, /* Nvidia Geforce 7600 LE */ 325 0x0398, /* Nvidia Geforce 7600 GO */ 326 0x03d0, /* Nvidia Geforce 6100 nForce 430 */ 327 0x03d1, /* Nvidia Geforce 6100 nForce 405 */ 328 0x03d2, /* Nvidia Geforce 6100 nForce 400 */ 329 0x03d5, /* Nvidia Geforce 6100 nForce 420 */ 330 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */ 331 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */ 332 0 333 }; 334 335 static uint16 elsa_device_list[] = { 336 0x0c60, /* Elsa Gladiac Geforce2 MX */ 337 0 338 }; 339 340 static uint16 nvstbsgs_device_list[] = { 341 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 342 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 343 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 344 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 345 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 346 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 347 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 348 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 349 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 350 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 351 0 352 }; 353 354 static uint16 varisys_device_list[] = { 355 0x3503, /* Varisys Geforce4 MX440 */ 356 0x3505, /* Varisys Geforce4 Ti 4200 */ 357 0 358 }; 359 360 static struct { 361 uint16 vendor; 362 uint16 *devices; 363 } SupportedDevices[] = { 364 {VENDOR_ID_NVIDIA, nvidia_device_list}, 365 {VENDOR_ID_ELSA, elsa_device_list}, 366 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 367 {VENDOR_ID_VARISYS, varisys_device_list}, 368 {0x0000, NULL} 369 }; 370 371 static nv_settings sSettings = { // see comments in nvidia.settings 372 /* for driver */ 373 DRIVER_PREFIX ".accelerant", 374 "none", // primary 375 false, // dumprom 376 /* for accelerant */ 377 0x00000000, // logmask 378 0, // memory 379 0, // tv_output 380 true, // usebios 381 true, // hardcursor 382 false, // switchhead 383 false, // force_pci 384 false, // unhide_fw 385 false, // pgm_panel 386 true, // dma_acc 387 false, // vga_on_tv 388 false, // force_sync 389 false, // force_ws 390 false, // block_acc 391 0, // gpu_clk 392 0, // ram_clk 393 }; 394 395 396 static void 397 dumprom(void *rom, uint32 size, pci_info pcii) 398 { 399 int fd; 400 uint32 cnt; 401 char fname[64]; 402 403 /* determine the romfile name: we need split-up per card in the system */ 404 sprintf (fname, kUserDirectory "//" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 405 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 406 407 fd = open (fname, O_WRONLY | O_CREAT, 0666); 408 if (fd < 0) return; 409 410 /* apparantly max. 32kb may be written at once; 411 * the ROM size is a multiple of that anyway. */ 412 for (cnt = 0; (cnt < size); cnt += 32768) 413 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 414 close (fd); 415 } 416 417 418 /*! return 1 if vblank interrupt has occured */ 419 static int 420 caused_vbi_crtc1(vuint32 * regs) 421 { 422 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 423 } 424 425 426 /*! clear the vblank interrupt */ 427 static void 428 clear_vbi_crtc1(vuint32 * regs) 429 { 430 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 431 } 432 433 434 static void 435 enable_vbi_crtc1(vuint32 * regs) 436 { 437 /* clear the vblank interrupt */ 438 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 439 /* enable nVidia interrupt source vblank */ 440 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 441 /* enable nVidia interrupt system hardware (b0-1) */ 442 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 443 } 444 445 446 static void 447 disable_vbi_crtc1(vuint32 * regs) 448 { 449 /* disable nVidia interrupt source vblank */ 450 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 451 /* clear the vblank interrupt */ 452 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 453 } 454 455 456 /*! return 1 if vblank interrupt has occured */ 457 static int 458 caused_vbi_crtc2(vuint32 * regs) 459 { 460 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 461 } 462 463 464 /*! clear the vblank interrupt */ 465 static void 466 clear_vbi_crtc2(vuint32 * regs) 467 { 468 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 469 } 470 471 472 static void 473 enable_vbi_crtc2(vuint32 * regs) 474 { 475 /* clear the vblank interrupt */ 476 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 477 /* enable nVidia interrupt source vblank */ 478 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 479 /* enable nVidia interrupt system hardware (b0-1) */ 480 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 481 } 482 483 484 static void 485 disable_vbi_crtc2(vuint32 * regs) 486 { 487 /* disable nVidia interrupt source vblank */ 488 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 489 /* clear the vblank interrupt */ 490 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 491 } 492 493 494 //fixme: 495 //dangerous code, on singlehead cards better not try accessing secondary head 496 //registers (card might react in unpredictable ways, though there's only a small 497 //chance we actually run into this). 498 //fix requires (some) card recognition code to be moved from accelerant to 499 //kerneldriver... 500 static void 501 disable_vbi_all(vuint32 * regs) 502 { 503 /* disable nVidia interrupt source vblank */ 504 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 505 /* clear the vblank interrupt */ 506 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 507 508 /* disable nVidia interrupt source vblank */ 509 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 510 /* clear the vblank interrupt */ 511 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 512 513 /* disable nVidia interrupt system hardware (b0-1) */ 514 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 515 } 516 517 518 static status_t 519 map_device(device_info *di) 520 { 521 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 522 shared_info *si = di->si; 523 uint32 tmpUlong, tmpROMshadow; 524 pci_info *pcii = &(di->pcii); 525 system_info sysinfo; 526 527 /* variables for making copy of ROM */ 528 uint8* rom_temp; 529 area_id rom_area = -1; 530 531 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 532 int registers = 0; 533 int frame_buffer = 1; 534 535 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 536 tmpUlong = get_pci(PCI_command, 2); 537 /* enable PCI access */ 538 tmpUlong |= PCI_command_memory; 539 /* enable busmastering */ 540 tmpUlong |= PCI_command_master; 541 /* disable ISA I/O access */ 542 tmpUlong &= ~PCI_command_io; 543 set_pci(PCI_command, 2, tmpUlong); 544 545 /*work out which version of BeOS is running*/ 546 get_system_info(&sysinfo); 547 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 548 { 549 si->use_clone_bugfix = 1; 550 } 551 else 552 { 553 si->use_clone_bugfix = 0; 554 } 555 556 /* work out a name for the register mapping */ 557 sprintf(buffer, DEVICE_FORMAT " regs", 558 di->pcii.vendor_id, di->pcii.device_id, 559 di->pcii.bus, di->pcii.device, di->pcii.function); 560 561 /* get a virtual memory address for the registers*/ 562 si->regs_area = map_physical_memory( 563 buffer, 564 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 565 di->pcii.u.h0.base_registers_pci[registers], 566 di->pcii.u.h0.base_register_sizes[registers], 567 B_ANY_KERNEL_ADDRESS, 568 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 569 (void **)&(di->regs)); 570 si->clone_bugfix_regs = (uint32 *) di->regs; 571 572 /* if mapping registers to vmem failed then pass on error */ 573 if (si->regs_area < 0) return si->regs_area; 574 575 /* work out a name for the ROM mapping*/ 576 sprintf(buffer, DEVICE_FORMAT " rom", 577 di->pcii.vendor_id, di->pcii.device_id, 578 di->pcii.bus, di->pcii.device, di->pcii.function); 579 580 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 581 /* warning: 582 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 583 * NV18, NV28 and NV34 keep working. 584 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 585 * however the actual ROM content (so the used part) is intact (confirmed). */ 586 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 587 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 588 set_pci(NVCFG_ROMSHADOW, 4, 0); 589 590 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 591 tmpUlong = get_pci(PCI_rom_base, 4); 592 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 593 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 594 //legacy space will get us into trouble if we aren't the primary graphics card!! 595 //(as legacy space always has the primary card's ROM 'mapped'!) 596 if (tmpUlong) { 597 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 598 tmpUlong |= 0x00000001; 599 set_pci(PCI_rom_base, 4, tmpUlong); 600 601 rom_area = map_physical_memory( 602 buffer, 603 di->pcii.u.h0.rom_base_pci, 604 di->pcii.u.h0.rom_size, 605 B_ANY_KERNEL_ADDRESS, 606 B_READ_AREA, 607 (void **)&(rom_temp) 608 ); 609 610 /* check if we got the BIOS and signature (might fail on laptops..) */ 611 if (rom_area >= 0) { 612 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 613 /* apparantly no ROM is mapped here */ 614 delete_area(rom_area); 615 rom_area = -1; 616 /* force using ISA legacy map as fall-back */ 617 tmpUlong = 0x00000000; 618 } 619 } else { 620 /* mapping failed: force using ISA legacy map as fall-back */ 621 tmpUlong = 0x00000000; 622 } 623 } 624 625 if (!tmpUlong) { 626 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 627 rom_area = map_physical_memory(buffer, 0x000c0000, 628 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 629 } 630 631 /* if mapping ROM to vmem failed then clean up and pass on error */ 632 if (rom_area < 0) { 633 delete_area(si->regs_area); 634 si->regs_area = -1; 635 return rom_area; 636 } 637 638 /* dump ROM to file if selected in nvidia.settings 639 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 640 if (sSettings.dumprom) 641 dumprom(rom_temp, 65536, di->pcii); 642 643 /* make a copy of ROM for future reference */ 644 memcpy(si->rom_mirror, rom_temp, 65536); 645 646 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 647 tmpUlong = get_pci(PCI_rom_base, 4); 648 tmpUlong &= 0xfffffffe; 649 set_pci(PCI_rom_base, 4, tmpUlong); 650 delete_area(rom_area); 651 652 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 653 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 654 655 /* work out a name for the framebuffer mapping*/ 656 sprintf(buffer, DEVICE_FORMAT " framebuffer", 657 di->pcii.vendor_id, di->pcii.device_id, 658 di->pcii.bus, di->pcii.device, di->pcii.function); 659 660 /* map the framebuffer into vmem, using Write Combining*/ 661 si->fb_area = map_physical_memory(buffer, 662 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 663 di->pcii.u.h0.base_registers_pci[frame_buffer], 664 di->pcii.u.h0.base_register_sizes[frame_buffer], 665 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 666 B_READ_AREA | B_WRITE_AREA, 667 &(si->framebuffer)); 668 669 /*if failed with write combining try again without*/ 670 if (si->fb_area < 0) { 671 si->fb_area = map_physical_memory(buffer, 672 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 673 di->pcii.u.h0.base_registers_pci[frame_buffer], 674 di->pcii.u.h0.base_register_sizes[frame_buffer], 675 B_ANY_KERNEL_BLOCK_ADDRESS, 676 B_READ_AREA | B_WRITE_AREA, 677 &(si->framebuffer)); 678 } 679 680 /* if there was an error, delete our other areas and pass on error*/ 681 if (si->fb_area < 0) { 682 delete_area(si->regs_area); 683 si->regs_area = -1; 684 return si->fb_area; 685 } 686 687 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 688 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 689 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 690 691 /* note the amount of memory mapped by the kerneldriver so we can make sure we 692 * don't attempt to adress more later on */ 693 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 694 695 // remember settings for use here and in accelerant 696 si->settings = sSettings; 697 698 /* in any case, return the result */ 699 return si->fb_area; 700 } 701 702 703 static void 704 unmap_device(device_info *di) 705 { 706 shared_info *si = di->si; 707 uint32 tmpUlong; 708 pci_info *pcii = &(di->pcii); 709 710 /* disable memory mapped IO */ 711 tmpUlong = get_pci(PCI_command, 4); 712 tmpUlong &= 0xfffffffc; 713 set_pci(PCI_command, 4, tmpUlong); 714 /* delete the areas */ 715 if (si->regs_area >= 0) 716 delete_area(si->regs_area); 717 if (si->fb_area >= 0) 718 delete_area(si->fb_area); 719 si->regs_area = si->fb_area = -1; 720 si->framebuffer = NULL; 721 di->regs = NULL; 722 } 723 724 725 static void 726 probe_devices(void) 727 { 728 uint32 pci_index = 0; 729 uint32 count = 0; 730 device_info *di = pd->di; 731 char tmp_name[B_OS_NAME_LENGTH]; 732 733 /* while there are more pci devices */ 734 while (count < MAX_DEVICES 735 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 736 int vendor = 0; 737 738 /* if we match a supported vendor */ 739 while (SupportedDevices[vendor].vendor) { 740 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 741 uint16 *devices = SupportedDevices[vendor].devices; 742 /* while there are more supported devices */ 743 while (*devices) { 744 /* if we match a supported device */ 745 if (*devices == di->pcii.device_id ) { 746 /* publish the device name */ 747 sprintf(tmp_name, DEVICE_FORMAT, 748 di->pcii.vendor_id, di->pcii.device_id, 749 di->pcii.bus, di->pcii.device, di->pcii.function); 750 /* tweak the exported name to show first in the alphabetically ordered /dev/ 751 * hierarchy folder, so the system will use it as primary adaptor if requested 752 * via nvidia.settings. */ 753 if (strcmp(tmp_name, sSettings.primary) == 0) 754 sprintf(tmp_name, "-%s", sSettings.primary); 755 /* add /dev/ hierarchy path */ 756 sprintf(di->name, "graphics/%s", tmp_name); 757 /* remember the name */ 758 pd->device_names[count] = di->name; 759 /* mark the driver as available for R/W open */ 760 di->is_open = 0; 761 /* mark areas as not yet created */ 762 di->shared_area = -1; 763 /* mark pointer to shared data as invalid */ 764 di->si = NULL; 765 /* inc pointer to device info */ 766 di++; 767 /* inc count */ 768 count++; 769 /* break out of these while loops */ 770 goto next_device; 771 } 772 /* next supported device */ 773 devices++; 774 } 775 } 776 vendor++; 777 } 778 next_device: 779 /* next pci_info struct, please */ 780 pci_index++; 781 } 782 /* propagate count */ 783 pd->count = count; 784 /* terminate list of device names with a null pointer */ 785 pd->device_names[pd->count] = NULL; 786 } 787 788 789 static uint32 790 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 791 { 792 uint32 handled = B_HANDLED_INTERRUPT; 793 /* release the vblank semaphore */ 794 if (si->vblank >= 0) { 795 int32 blocked; 796 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 797 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 798 handled = B_INVOKE_SCHEDULER; 799 } 800 } 801 return handled; 802 } 803 804 805 static int32 806 nv_interrupt(void *data) 807 { 808 int32 handled = B_UNHANDLED_INTERRUPT; 809 device_info *di = (device_info *)data; 810 shared_info *si = di->si; 811 int32 *flags = &(si->flags); 812 vuint32 *regs; 813 814 /* is someone already handling an interrupt for this device? */ 815 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 816 817 /* get regs */ 818 regs = di->regs; 819 820 /* was it a VBI? */ 821 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 822 if (si->ps.secondary_head) { 823 //fixme: 824 //rewrite once we use one driver instance 'per head' (instead of 'per card') 825 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 826 /* clear the interrupt(s) */ 827 clear_vbi_crtc1(regs); 828 clear_vbi_crtc2(regs); 829 /* release the semaphore */ 830 handled = thread_interrupt_work(flags, regs, si); 831 } 832 } else { 833 if (caused_vbi_crtc1(regs)) { 834 /* clear the interrupt */ 835 clear_vbi_crtc1(regs); 836 /* release the semaphore */ 837 handled = thread_interrupt_work(flags, regs, si); 838 } 839 } 840 841 /* note that we're not in the handler any more */ 842 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 843 844 exit0: 845 return handled; 846 } 847 848 849 // #pragma mark - device hooks 850 851 852 static status_t 853 open_hook(const char* name, uint32 flags, void** cookie) 854 { 855 int32 index = 0; 856 device_info *di; 857 shared_info *si; 858 thread_id thid; 859 thread_info thinfo; 860 status_t result = B_OK; 861 char shared_name[B_OS_NAME_LENGTH]; 862 physical_entry map[1]; 863 size_t net_buf_size; 864 void *unaligned_dma_buffer; 865 uint32 mem_size; 866 867 /* find the device name in the list of devices */ 868 /* we're never passed a name we didn't publish */ 869 while (pd->device_names[index] 870 && (strcmp(name, pd->device_names[index]) != 0)) 871 index++; 872 873 /* for convienience */ 874 di = &(pd->di[index]); 875 876 /* make sure no one else has write access to the common data */ 877 AQUIRE_BEN(pd->kernel); 878 879 /* if it's already open for writing */ 880 if (di->is_open) { 881 /* mark it open another time */ 882 goto mark_as_open; 883 } 884 /* create the shared_info area */ 885 sprintf(shared_name, DEVICE_FORMAT " shared", 886 di->pcii.vendor_id, di->pcii.device_id, 887 di->pcii.bus, di->pcii.device, di->pcii.function); 888 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 889 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 890 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 891 B_USER_CLONEABLE_AREA); 892 if (di->shared_area < 0) { 893 /* return the error */ 894 result = di->shared_area; 895 goto done; 896 } 897 898 /* save a few dereferences */ 899 si = di->si; 900 901 /* create the DMA command buffer area */ 902 //fixme? for R4.5 a workaround for cloning would be needed! 903 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 904 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 905 /* create the area that will hold the DMA command buffer */ 906 si->unaligned_dma_area = 907 create_area("NV DMA cmd buffer", 908 (void **)&unaligned_dma_buffer, 909 B_ANY_KERNEL_ADDRESS, 910 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 911 B_32_BIT_CONTIGUOUS, /* GPU always needs access */ 912 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 913 // TODO: Physical aligning can be done without waste using the 914 // private create_area_etc(). 915 /* on error, abort */ 916 if (si->unaligned_dma_area < 0) 917 { 918 /* free the already created shared_info area, and return the error */ 919 result = si->unaligned_dma_area; 920 goto free_shared; 921 } 922 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 923 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 924 * even on older CPU's. */ 925 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 926 si->dma_buffer_pci = (void*) 927 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); 928 929 /* map the net DMA command buffer into vmem, using Write Combining */ 930 si->dma_area = map_physical_memory( 931 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, 932 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 933 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 934 /* if failed with write combining try again without */ 935 if (si->dma_area < 0) { 936 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer", 937 (addr_t)si->dma_buffer_pci, net_buf_size, 938 B_ANY_KERNEL_BLOCK_ADDRESS, 939 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 940 } 941 /* if there was an error, delete our other areas and pass on error*/ 942 if (si->dma_area < 0) 943 { 944 /* free the already created areas, and return the error */ 945 result = si->dma_area; 946 goto free_shared_and_uadma; 947 } 948 949 /* save the vendor and device IDs */ 950 si->vendor_id = di->pcii.vendor_id; 951 si->device_id = di->pcii.device_id; 952 si->revision = di->pcii.revision; 953 si->bus = di->pcii.bus; 954 si->device = di->pcii.device; 955 si->function = di->pcii.function; 956 957 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 958 si->accelerant_in_use = false; 959 /* preset singlehead card to prevent early INT routine calls (once installed) to 960 * wrongly identify the INT request coming from us! */ 961 si->ps.secondary_head = false; 962 963 /* map the device */ 964 result = map_device(di); 965 if (result < 0) goto free_shared_and_alldma; 966 967 /* we will be returning OK status for sure now */ 968 result = B_OK; 969 970 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 971 * unified memory architecture (UMA) */ 972 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 973 { 974 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */ 975 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 976 mem_size = 1024 * 1024 * 977 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 978 /* don't attempt to adress memory not mapped by the kerneldriver */ 979 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 980 /* last 64kB RAM is used for the BIOS (or something else?) */ 981 si->ps.memory_size -= (64 * 1024); 982 break; 983 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */ 984 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 985 mem_size = 1024 * 1024 * 986 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 987 /* don't attempt to adress memory not mapped by the kerneldriver */ 988 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 989 /* last 64kB RAM is used for the BIOS (or something else?) */ 990 si->ps.memory_size -= (64 * 1024); 991 break; 992 default: 993 /* all other cards have own RAM: the amount of which is determined in the 994 * accelerant. */ 995 break; 996 } 997 998 /* disable and clear any pending interrupts */ 999 //fixme: 1000 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1001 disable_vbi_all(di->regs); 1002 1003 /* preset we can't use INT related functions */ 1004 si->ps.int_assigned = false; 1005 1006 /* create a semaphore for vertical blank management */ 1007 si->vblank = create_sem(0, di->name); 1008 if (si->vblank < 0) goto mark_as_open; 1009 1010 /* change the owner of the semaphores to the opener's team */ 1011 /* this is required because apps can't aquire kernel semaphores */ 1012 thid = find_thread(NULL); 1013 get_thread_info(thid, &thinfo); 1014 set_sem_owner(si->vblank, thinfo.team); 1015 1016 /* If there is a valid interrupt line assigned then set up interrupts */ 1017 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1018 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1019 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1020 { 1021 /* delete the semaphore as it won't be used */ 1022 delete_sem(si->vblank); 1023 si->vblank = -1; 1024 } 1025 else 1026 { 1027 /* otherwise install our interrupt handler */ 1028 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1029 /* bail if we couldn't install the handler */ 1030 if (result != B_OK) 1031 { 1032 /* delete the semaphore as it won't be used */ 1033 delete_sem(si->vblank); 1034 si->vblank = -1; 1035 } 1036 else 1037 { 1038 /* inform accelerant(s) we can use INT related functions */ 1039 si->ps.int_assigned = true; 1040 } 1041 } 1042 1043 mark_as_open: 1044 /* mark the device open */ 1045 di->is_open++; 1046 1047 /* send the cookie to the opener */ 1048 *cookie = di; 1049 1050 goto done; 1051 1052 1053 free_shared_and_alldma: 1054 /* clean up our aligned DMA area */ 1055 delete_area(si->dma_area); 1056 si->dma_area = -1; 1057 si->dma_buffer = NULL; 1058 1059 free_shared_and_uadma: 1060 /* clean up our unaligned DMA area */ 1061 delete_area(si->unaligned_dma_area); 1062 si->unaligned_dma_area = -1; 1063 si->dma_buffer_pci = NULL; 1064 1065 free_shared: 1066 /* clean up our shared area */ 1067 delete_area(di->shared_area); 1068 di->shared_area = -1; 1069 di->si = NULL; 1070 1071 done: 1072 /* end of critical section */ 1073 RELEASE_BEN(pd->kernel); 1074 1075 /* all done, return the status */ 1076 return result; 1077 } 1078 1079 1080 static status_t 1081 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1082 { 1083 *len = 0; 1084 return B_NOT_ALLOWED; 1085 } 1086 1087 1088 static status_t 1089 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1090 { 1091 *len = 0; 1092 return B_NOT_ALLOWED; 1093 } 1094 1095 1096 static status_t 1097 close_hook(void* dev) 1098 { 1099 /* we don't do anything on close: there might be dup'd fd */ 1100 return B_NO_ERROR; 1101 } 1102 1103 1104 static status_t 1105 free_hook(void* dev) 1106 { 1107 device_info *di = (device_info *)dev; 1108 shared_info *si = di->si; 1109 vuint32 *regs = di->regs; 1110 1111 /* lock the driver */ 1112 AQUIRE_BEN(pd->kernel); 1113 1114 /* if opened multiple times, decrement the open count and exit */ 1115 if (di->is_open > 1) 1116 goto unlock_and_exit; 1117 1118 /* disable and clear any pending interrupts */ 1119 //fixme: 1120 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1121 disable_vbi_all(regs); 1122 1123 if (si->ps.int_assigned) { 1124 /* remove interrupt handler */ 1125 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1126 1127 /* delete the semaphores, ignoring any errors ('cause the owning 1128 team may have died on us) */ 1129 delete_sem(si->vblank); 1130 si->vblank = -1; 1131 } 1132 1133 /* free regs and framebuffer areas */ 1134 unmap_device(di); 1135 1136 /* clean up our aligned DMA area */ 1137 delete_area(si->dma_area); 1138 si->dma_area = -1; 1139 si->dma_buffer = NULL; 1140 1141 /* clean up our unaligned DMA area */ 1142 delete_area(si->unaligned_dma_area); 1143 si->unaligned_dma_area = -1; 1144 si->dma_buffer_pci = NULL; 1145 1146 /* clean up our shared area */ 1147 delete_area(di->shared_area); 1148 di->shared_area = -1; 1149 di->si = NULL; 1150 1151 unlock_and_exit: 1152 /* mark the device available */ 1153 di->is_open--; 1154 /* unlock the driver */ 1155 RELEASE_BEN(pd->kernel); 1156 /* all done */ 1157 return B_OK; 1158 } 1159 1160 1161 static status_t 1162 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1163 { 1164 device_info *di = (device_info *)dev; 1165 status_t result = B_DEV_INVALID_IOCTL; 1166 uint32 tmpUlong; 1167 1168 switch (msg) { 1169 /* the only PUBLIC ioctl */ 1170 case B_GET_ACCELERANT_SIGNATURE: 1171 { 1172 strcpy((char* )buf, sSettings.accelerant); 1173 result = B_OK; 1174 break; 1175 } 1176 1177 /* PRIVATE ioctl from here on */ 1178 case NV_GET_PRIVATE_DATA: 1179 { 1180 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1181 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1182 gpd->shared_info_area = di->shared_area; 1183 result = B_OK; 1184 } 1185 break; 1186 } 1187 1188 case NV_GET_PCI: 1189 { 1190 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1191 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1192 pci_info *pcii = &(di->pcii); 1193 gsp->value = get_pci(gsp->offset, gsp->size); 1194 result = B_OK; 1195 } 1196 break; 1197 } 1198 1199 case NV_SET_PCI: 1200 { 1201 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1202 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1203 pci_info *pcii = &(di->pcii); 1204 set_pci(gsp->offset, gsp->size, gsp->value); 1205 result = B_OK; 1206 } 1207 break; 1208 } 1209 1210 case NV_DEVICE_NAME: 1211 { 1212 nv_device_name *dn = (nv_device_name *)buf; 1213 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1214 strcpy(dn->name, di->name); 1215 result = B_OK; 1216 } 1217 break; 1218 } 1219 1220 case NV_RUN_INTERRUPTS: 1221 { 1222 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1223 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1224 vuint32 *regs = di->regs; 1225 if (!(vi->crtc)) { 1226 if (vi->do_it) { 1227 enable_vbi_crtc1(regs); 1228 } else { 1229 disable_vbi_crtc1(regs); 1230 } 1231 } else { 1232 if (vi->do_it) { 1233 enable_vbi_crtc2(regs); 1234 } else { 1235 disable_vbi_crtc2(regs); 1236 } 1237 } 1238 result = B_OK; 1239 } 1240 break; 1241 } 1242 1243 case NV_GET_NTH_AGP_INFO: 1244 { 1245 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1246 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1247 nai->exist = false; 1248 nai->agp_bus = false; 1249 if (agp_bus) { 1250 nai->agp_bus = true; 1251 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1252 nai->exist = true; 1253 } 1254 } 1255 result = B_OK; 1256 } 1257 break; 1258 } 1259 1260 case NV_ENABLE_AGP: 1261 { 1262 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1263 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1264 if (agp_bus) { 1265 nca->agp_bus = true; 1266 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1267 } else { 1268 nca->agp_bus = false; 1269 nca->cmd = 0; 1270 } 1271 result = B_OK; 1272 } 1273 break; 1274 } 1275 1276 case NV_ISA_OUT: 1277 { 1278 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1279 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1280 pci_info *pcii = &(di->pcii); 1281 1282 /* lock the driver: 1283 * no other graphics card may have ISA I/O enabled when we enter */ 1284 AQUIRE_BEN(pd->kernel); 1285 1286 /* enable ISA I/O access */ 1287 tmpUlong = get_pci(PCI_command, 2); 1288 tmpUlong |= PCI_command_io; 1289 set_pci(PCI_command, 2, tmpUlong); 1290 1291 if (io_isa->size == 1) 1292 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1293 else 1294 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1295 result = B_OK; 1296 1297 /* disable ISA I/O access */ 1298 tmpUlong = get_pci(PCI_command, 2); 1299 tmpUlong &= ~PCI_command_io; 1300 set_pci(PCI_command, 2, tmpUlong); 1301 1302 /* end of critical section */ 1303 RELEASE_BEN(pd->kernel); 1304 } 1305 break; 1306 } 1307 1308 case NV_ISA_IN: 1309 { 1310 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1311 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1312 pci_info *pcii = &(di->pcii); 1313 1314 /* lock the driver: 1315 * no other graphics card may have ISA I/O enabled when we enter */ 1316 AQUIRE_BEN(pd->kernel); 1317 1318 /* enable ISA I/O access */ 1319 tmpUlong = get_pci(PCI_command, 2); 1320 tmpUlong |= PCI_command_io; 1321 set_pci(PCI_command, 2, tmpUlong); 1322 1323 if (io_isa->size == 1) 1324 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1325 else 1326 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1327 result = B_OK; 1328 1329 /* disable ISA I/O access */ 1330 tmpUlong = get_pci(PCI_command, 2); 1331 tmpUlong &= ~PCI_command_io; 1332 set_pci(PCI_command, 2, tmpUlong); 1333 1334 /* end of critical section */ 1335 RELEASE_BEN(pd->kernel); 1336 } 1337 break; 1338 } 1339 } 1340 1341 return result; 1342 } 1343 1344 1345 // #pragma mark - driver API 1346 1347 1348 status_t 1349 init_hardware(void) 1350 { 1351 long index = 0; 1352 pci_info pcii; 1353 bool found = false; 1354 1355 /* choke if we can't find the PCI bus */ 1356 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1357 return B_ERROR; 1358 1359 /* choke if we can't find the ISA bus */ 1360 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1361 { 1362 put_module(B_PCI_MODULE_NAME); 1363 return B_ERROR; 1364 } 1365 1366 /* while there are more pci devices */ 1367 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1368 int vendor = 0; 1369 1370 /* if we match a supported vendor */ 1371 while (SupportedDevices[vendor].vendor) { 1372 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1373 uint16 *devices = SupportedDevices[vendor].devices; 1374 /* while there are more supported devices */ 1375 while (*devices) { 1376 /* if we match a supported device */ 1377 if (*devices == pcii.device_id ) { 1378 1379 found = true; 1380 goto done; 1381 } 1382 /* next supported device */ 1383 devices++; 1384 } 1385 } 1386 vendor++; 1387 } 1388 /* next pci_info struct, please */ 1389 index++; 1390 } 1391 1392 done: 1393 /* put away the module manager */ 1394 put_module(B_PCI_MODULE_NAME); 1395 return found ? B_OK : B_ERROR; 1396 } 1397 1398 1399 status_t 1400 init_driver(void) 1401 { 1402 void *settings; 1403 1404 // get driver/accelerant settings 1405 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1406 if (settings != NULL) { 1407 const char *item; 1408 char *end; 1409 uint32 value; 1410 1411 // for driver 1412 item = get_driver_parameter(settings, "accelerant", "", ""); 1413 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1414 strcpy (sSettings.accelerant, item); 1415 1416 item = get_driver_parameter(settings, "primary", "", ""); 1417 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1418 strcpy(sSettings.primary, item); 1419 1420 sSettings.dumprom = get_driver_boolean_parameter(settings, 1421 "dumprom", false, false); 1422 1423 // for accelerant 1424 item = get_driver_parameter(settings, "logmask", 1425 "0x00000000", "0x00000000"); 1426 value = strtoul(item, &end, 0); 1427 if (*end == '\0') 1428 sSettings.logmask = value; 1429 1430 item = get_driver_parameter(settings, "memory", "0", "0"); 1431 value = strtoul(item, &end, 0); 1432 if (*end == '\0') 1433 sSettings.memory = value; 1434 1435 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1436 value = strtoul(item, &end, 0); 1437 if (*end == '\0') 1438 sSettings.tv_output = value; 1439 1440 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1441 "hardcursor", true, true); 1442 sSettings.usebios = get_driver_boolean_parameter(settings, 1443 "usebios", true, true); 1444 sSettings.switchhead = get_driver_boolean_parameter(settings, 1445 "switchhead", false, false); 1446 sSettings.force_pci = get_driver_boolean_parameter(settings, 1447 "force_pci", false, false); 1448 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1449 "unhide_fw", false, false); 1450 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1451 "pgm_panel", false, false); 1452 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1453 "dma_acc", true, true); 1454 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1455 "vga_on_tv", false, false); 1456 sSettings.force_sync = get_driver_boolean_parameter(settings, 1457 "force_sync", false, false); 1458 sSettings.force_ws = get_driver_boolean_parameter(settings, 1459 "force_ws", false, false); 1460 sSettings.block_acc = get_driver_boolean_parameter(settings, 1461 "block_acc", false, false); 1462 1463 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1464 value = strtoul(item, &end, 0); 1465 if (*end == '\0') 1466 sSettings.gpu_clk = value; 1467 1468 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1469 value = strtoul(item, &end, 0); 1470 if (*end == '\0') 1471 sSettings.ram_clk = value; 1472 1473 unload_driver_settings(settings); 1474 } 1475 1476 /* get a handle for the pci bus */ 1477 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1478 return B_ERROR; 1479 1480 /* get a handle for the isa bus */ 1481 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1482 put_module(B_PCI_MODULE_NAME); 1483 return B_ERROR; 1484 } 1485 1486 /* get a handle for the agp bus if it exists */ 1487 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1488 1489 /* driver private data */ 1490 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1491 if (!pd) { 1492 put_module(B_PCI_MODULE_NAME); 1493 return B_ERROR; 1494 } 1495 /* initialize the benaphore */ 1496 INIT_BEN(pd->kernel); 1497 /* find all of our supported devices */ 1498 probe_devices(); 1499 return B_OK; 1500 } 1501 1502 1503 const char ** 1504 publish_devices(void) 1505 { 1506 /* return the list of supported devices */ 1507 return (const char **)pd->device_names; 1508 } 1509 1510 1511 device_hooks * 1512 find_device(const char *name) 1513 { 1514 int index = 0; 1515 while (pd->device_names[index]) { 1516 if (strcmp(name, pd->device_names[index]) == 0) 1517 return &graphics_device_hooks; 1518 index++; 1519 } 1520 return NULL; 1521 1522 } 1523 1524 1525 void 1526 uninit_driver(void) 1527 { 1528 /* free the driver data */ 1529 DELETE_BEN(pd->kernel); 1530 free(pd); 1531 pd = NULL; 1532 1533 /* put the pci module away */ 1534 put_module(B_PCI_MODULE_NAME); 1535 put_module(B_ISA_MODULE_NAME); 1536 1537 /* put the agp module away if it's there */ 1538 if (agp_bus) 1539 put_module(B_AGP_GART_MODULE_NAME); 1540 } 1541 1542