1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-1/2016. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <directories.h> 21 #include <driver_settings.h> 22 23 #include <stdlib.h> 24 #include <stdio.h> 25 #include <string.h> 26 27 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 28 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 29 30 #define MAX_DEVICES 8 31 32 /* Tell the kernel what revision of the driver API we support */ 33 int32 api_version = B_CUR_DRIVER_API_VERSION; 34 35 /* these structures are private to the kernel driver */ 36 typedef struct device_info device_info; 37 38 typedef struct { 39 timer te; /* timer entry for add_timer() */ 40 device_info *di; /* pointer to the owning device */ 41 bigtime_t when_target; /* when we're supposed to wake up */ 42 } timer_info; 43 44 struct device_info { 45 uint32 is_open; /* a count of how many times the devices has been opened */ 46 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 47 shared_info *si; /* a pointer to the shared area, for convenience */ 48 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 49 pci_info pcii; /* a convenience copy of the pci info for this device */ 50 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 51 }; 52 53 typedef struct { 54 uint32 count; /* number of devices actually found */ 55 benaphore kernel; /* for serializing opens/closes */ 56 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 57 device_info di[MAX_DEVICES]; /* device specific stuff */ 58 } DeviceData; 59 60 /* prototypes for our private functions */ 61 static status_t open_hook(const char* name, uint32 flags, void** cookie); 62 static status_t close_hook(void* dev); 63 static status_t free_hook(void* dev); 64 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 65 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 66 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 67 static status_t map_device(device_info *di); 68 static void unmap_device(device_info *di); 69 static void probe_devices(void); 70 static int32 nv_interrupt(void *data); 71 72 static DeviceData *pd; 73 static isa_module_info *isa_bus = NULL; 74 static pci_module_info *pci_bus = NULL; 75 static agp_gart_module_info *agp_bus = NULL; 76 static device_hooks graphics_device_hooks = { 77 open_hook, 78 close_hook, 79 free_hook, 80 control_hook, 81 read_hook, 82 write_hook, 83 NULL, 84 NULL, 85 NULL, 86 NULL 87 }; 88 89 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 90 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 91 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 92 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 93 94 static uint16 nvidia_device_list[] = { 95 0x0020, /* Nvidia TNT1 */ 96 0x0028, /* Nvidia TNT2 (pro) */ 97 0x0029, /* Nvidia TNT2 Ultra */ 98 0x002a, /* Nvidia TNT2 */ 99 0x002b, /* Nvidia TNT2 */ 100 0x002c, /* Nvidia Vanta (Lt) */ 101 0x002d, /* Nvidia TNT2-M64 (Pro) */ 102 0x002e, /* Nvidia NV06 Vanta */ 103 0x002f, /* Nvidia NV06 Vanta */ 104 0x0040, /* Nvidia Geforce FX 6800 Ultra */ 105 0x0041, /* Nvidia Geforce FX 6800 */ 106 0x0042, /* Nvidia Geforce FX 6800LE */ 107 0x0043, /* Nvidia Geforce 6800 XE */ 108 0x0045, /* Nvidia Geforce FX 6800 GT */ 109 0x0046, /* Nvidia Geforce FX 6800 GT */ 110 0x0047, /* Nvidia Geforce 6800 GS */ 111 0x0048, /* Nvidia Geforce FX 6800 XT */ 112 0x0049, /* Nvidia unknown FX */ 113 0x004d, /* Nvidia Quadro FX 4400 */ 114 0x004e, /* Nvidia Quadro FX 4000 */ 115 0x0091, /* Nvidia Geforce 7800 GTX PCIe */ 116 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 117 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 118 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 119 0x009d, /* Nvidia Quadro FX 4500 */ 120 0x00a0, /* Nvidia Aladdin TNT2 */ 121 0x00c0, /* Nvidia Geforce 6800 GS */ 122 0x00c1, /* Nvidia Geforce FX 6800 */ 123 0x00c2, /* Nvidia Geforce FX 6800LE */ 124 0x00c3, /* Nvidia Geforce FX 6800 XT */ 125 0x00c8, /* Nvidia Geforce FX 6800 Go */ 126 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */ 127 0x00cc, /* Nvidia Quadro FX 1400 Go */ 128 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 129 0x00ce, /* Nvidia Quadro FX 1400 */ 130 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */ 131 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */ 132 0x00f2, /* Nvidia Geforce FX 6600 AGP */ 133 0x00f3, /* Nvidia Geforce 6200 */ 134 0x00f4, /* Nvidia Geforce 6600 LE */ 135 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */ 136 0x00f6, /* Nvidia Geforce 6800 GS */ 137 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 138 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */ 139 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */ 140 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */ 141 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */ 142 0x00fd, /* Nvidia Quadro PCX PCIe */ 143 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 144 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */ 145 0x0100, /* Nvidia Geforce256 SDR */ 146 0x0101, /* Nvidia Geforce256 DDR */ 147 0x0102, /* Nvidia Geforce256 Ultra */ 148 0x0103, /* Nvidia Quadro */ 149 0x0110, /* Nvidia Geforce2 MX/MX400 */ 150 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */ 151 0x0112, /* Nvidia Geforce2 Go */ 152 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 153 0x0140, /* Nvidia Geforce FX 6600 GT */ 154 0x0141, /* Nvidia Geforce FX 6600 */ 155 0x0142, /* Nvidia Geforce FX 6600LE */ 156 0x0143, /* Nvidia Geforce 6600 VE */ 157 0x0144, /* Nvidia Geforce FX 6600 Go */ 158 0x0145, /* Nvidia Geforce FX 6610 XL */ 159 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */ 160 0x0147, /* Nvidia Geforce FX 6700 XL */ 161 0x0148, /* Nvidia Geforce FX 6600 Go */ 162 0x0149, /* Nvidia Geforce FX 6600 GT Go */ 163 0x014b, /* Nvidia unknown FX */ 164 0x014c, /* Nvidia Quadro FX 540 MXM */ 165 0x014d, /* Nvidia unknown FX */ 166 0x014e, /* Nvidia Quadro FX 540 */ 167 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */ 168 0x0150, /* Nvidia Geforce2 GTS/Pro */ 169 0x0151, /* Nvidia Geforce2 Ti DDR */ 170 0x0152, /* Nvidia Geforce2 Ultra */ 171 0x0153, /* Nvidia Quadro2 Pro */ 172 0x0160, /* Nvidia Geforce 6500 Go */ 173 0x0161, /* Nvidia Geforce 6200 TurboCache */ 174 0x0162, /* Nvidia Geforce 6200SE TurboCache */ 175 0x0163, /* Nvidia Geforce 6200LE */ 176 0x0164, /* Nvidia Geforce FX 6200 Go */ 177 0x0165, /* Nvidia Quadro FX NVS 285 */ 178 0x0166, /* Nvidia Geforce 6400 Go */ 179 0x0167, /* Nvidia Geforce 6200 Go */ 180 0x0168, /* Nvidia Geforce 6400 Go */ 181 0x0169, /* Nvidia Geforce 6250 Go */ 182 0x016a, /* Nvidia Geforce 7100 GS */ 183 0x016b, /* Nvidia unknown FX Go */ 184 0x016c, /* Nvidia unknown FX Go */ 185 0x016d, /* Nvidia unknown FX Go */ 186 0x016e, /* Nvidia unknown FX */ 187 0x0170, /* Nvidia Geforce4 MX 460 */ 188 0x0171, /* Nvidia Geforce4 MX 440 */ 189 0x0172, /* Nvidia Geforce4 MX 420 */ 190 0x0173, /* Nvidia Geforce4 MX 440SE */ 191 0x0174, /* Nvidia Geforce4 440 Go */ 192 0x0175, /* Nvidia Geforce4 420 Go */ 193 0x0176, /* Nvidia Geforce4 420 Go 32M */ 194 0x0177, /* Nvidia Geforce4 460 Go */ 195 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 196 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */ 197 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 198 0x017c, /* Nvidia Quadro4 500 GoGL */ 199 0x017d, /* Nvidia Geforce4 410 Go 16M */ 200 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */ 201 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */ 202 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */ 203 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */ 204 0x0186, /* Nvidia Geforce4 448 Go */ 205 0x0187, /* Nvidia Geforce4 488 Go */ 206 0x0188, /* Nvidia Quadro4 580 XGL */ 207 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */ 208 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 209 0x018b, /* Nvidia Quadro4 380 XGL */ 210 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 211 0x018d, /* Nvidia Geforce4 448 Go */ 212 0x01a0, /* Nvidia Geforce2 Integrated GPU */ 213 0x01d1, /* Nvidia Geforce 7300 LE */ 214 0x01d3, /* Nvidia Geforce 7300 SE */ 215 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */ 216 0x01d8, /* Nvidia Geforce 7400 GO */ 217 0x01dd, /* Nvidia Geforce 7500 LE */ 218 0x01df, /* Nvidia Geforce 7300 GS */ 219 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */ 220 0x0200, /* Nvidia Geforce3 */ 221 0x0201, /* Nvidia Geforce3 Ti 200 */ 222 0x0202, /* Nvidia Geforce3 Ti 500 */ 223 0x0203, /* Nvidia Quadro DCC */ 224 0x0211, /* Nvidia Geforce FX 6800 */ 225 0x0212, /* Nvidia Geforce FX 6800LE */ 226 0x0215, /* Nvidia Geforce FX 6800 GT */ 227 0x0218, /* Nvidia Geforce 6800 XT */ 228 0x0220, /* Nvidia unknown FX */ 229 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */ 230 0x0222, /* Nvidia unknown FX */ 231 0x0228, /* Nvidia unknown FX Go */ 232 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */ 233 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */ 234 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */ 235 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */ 236 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */ 237 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */ 238 0x0250, /* Nvidia Geforce4 Ti 4600 */ 239 0x0251, /* Nvidia Geforce4 Ti 4400 */ 240 0x0252, /* Nvidia Geforce4 Ti 4600 */ 241 0x0253, /* Nvidia Geforce4 Ti 4200 */ 242 0x0258, /* Nvidia Quadro4 900 XGL */ 243 0x0259, /* Nvidia Quadro4 750 XGL */ 244 0x025b, /* Nvidia Quadro4 700 XGL */ 245 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */ 246 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */ 247 0x0282, /* Nvidia Geforce4 Ti 4800SE */ 248 0x0286, /* Nvidia Geforce4 4200 Go */ 249 0x0288, /* Nvidia Quadro4 980 XGL */ 250 0x0289, /* Nvidia Quadro4 780 XGL */ 251 0x028c, /* Nvidia Quadro4 700 GoGL */ 252 0x0290, /* Nvidia Geforce 7900 GTX */ 253 0x0291, /* Nvidia Geforce 7900 GT */ 254 0x0292, /* Nvidia Geforce 7900 GS */ 255 0x0293, /* Nvidia Geforce 7900 GX2 */ 256 0x0294, /* Nvidia Geforce 7950 GX2 */ 257 0x0295, /* Nvidia Geforce 7950 GT */ 258 0x0298, /* Nvidia Geforce Go 7900 GS */ 259 0x0299, /* Nvidia Geforce Go 7900 GTX */ 260 0x029c, /* Nvidia Quadro FX 5500 */ 261 0x029f, /* Nvidia Quadro FX 4500 X2 */ 262 0x02a0, /* Nvidia Geforce3 Integrated GPU */ 263 0x02e0, /* Nvidia Geforce 7600 GT */ 264 0x02e1, /* Nvidia Geforce 7600 GS */ 265 0x02e2, /* Nvidia Geforce 7300 GT */ 266 0x0301, /* Nvidia Geforce FX 5800 Ultra */ 267 0x0302, /* Nvidia Geforce FX 5800 */ 268 0x0308, /* Nvidia Quadro FX 2000 */ 269 0x0309, /* Nvidia Quadro FX 1000 */ 270 0x0311, /* Nvidia Geforce FX 5600 Ultra */ 271 0x0312, /* Nvidia Geforce FX 5600 */ 272 0x0313, /* Nvidia unknown FX */ 273 0x0314, /* Nvidia Geforce FX 5600XT */ 274 0x0316, /* Nvidia unknown FX Go */ 275 0x0317, /* Nvidia unknown FX Go */ 276 0x031a, /* Nvidia Geforce FX 5600 Go */ 277 0x031b, /* Nvidia Geforce FX 5650 Go */ 278 0x031c, /* Nvidia Quadro FX 700 Go */ 279 0x031d, /* Nvidia unknown FX Go */ 280 0x031e, /* Nvidia unknown FX Go */ 281 0x031f, /* Nvidia unknown FX Go */ 282 0x0320, /* Nvidia Geforce FX 5200 */ 283 0x0321, /* Nvidia Geforce FX 5200 Ultra */ 284 0x0322, /* Nvidia Geforce FX 5200 */ 285 0x0323, /* Nvidia Geforce FX 5200LE */ 286 0x0324, /* Nvidia Geforce FX 5200 Go */ 287 0x0325, /* Nvidia Geforce FX 5250 Go */ 288 0x0326, /* Nvidia Geforce FX 5500 */ 289 0x0327, /* Nvidia Geforce FX 5100 */ 290 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */ 291 0x0329, /* Nvidia Geforce FX 5200 (PPC) */ 292 0x032a, /* Nvidia Quadro NVS 280 PCI */ 293 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 294 0x032c, /* Nvidia Geforce FX 5300 Go */ 295 0x032d, /* Nvidia Geforce FX 5100 Go */ 296 0x032e, /* Nvidia unknown FX Go */ 297 0x032f, /* Nvidia unknown FX Go */ 298 0x0330, /* Nvidia Geforce FX 5900 Ultra */ 299 0x0331, /* Nvidia Geforce FX 5900 */ 300 0x0332, /* Nvidia Geforce FX 5900 XT */ 301 0x0333, /* Nvidia Geforce FX 5950 Ultra */ 302 0x0334, /* Nvidia Geforce FX 5900 ZT */ 303 0x0338, /* Nvidia Quadro FX 3000 */ 304 0x033f, /* Nvidia Quadro FX 700 */ 305 0x0341, /* Nvidia Geforce FX 5700 Ultra */ 306 0x0342, /* Nvidia Geforce FX 5700 */ 307 0x0343, /* Nvidia Geforce FX 5700LE */ 308 0x0344, /* Nvidia Geforce FX 5700VE */ 309 0x0345, /* Nvidia unknown FX */ 310 0x0347, /* Nvidia Geforce FX 5700 Go */ 311 0x0348, /* Nvidia Geforce FX 5700 Go */ 312 0x0349, /* Nvidia unknown FX Go */ 313 0x034b, /* Nvidia unknown FX Go */ 314 0x034c, /* Nvidia Quadro FX 1000 Go */ 315 0x034e, /* Nvidia Quadro FX 1100 */ 316 0x034f, /* Nvidia unknown FX */ 317 0x0391, /* Nvidia Geforce 7600 GT */ 318 0x0392, /* Nvidia Geforce 7600 GS */ 319 0x0393, /* Nvidia Geforce 7300 GT */ 320 0x0394, /* Nvidia Geforce 7600 LE */ 321 0x0398, /* Nvidia Geforce 7600 GO */ 322 0x03d0, /* Nvidia Geforce 6100 nForce 430 */ 323 0x03d1, /* Nvidia Geforce 6100 nForce 405 */ 324 0x03d2, /* Nvidia Geforce 6100 nForce 400 */ 325 0x03d5, /* Nvidia Geforce 6100 nForce 420 */ 326 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */ 327 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */ 328 0 329 }; 330 331 static uint16 elsa_device_list[] = { 332 0x0c60, /* Elsa Gladiac Geforce2 MX */ 333 0 334 }; 335 336 static uint16 nvstbsgs_device_list[] = { 337 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 338 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 339 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 340 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 341 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 342 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 343 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 344 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 345 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 346 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 347 0 348 }; 349 350 static uint16 varisys_device_list[] = { 351 0x3503, /* Varisys Geforce4 MX440 */ 352 0x3505, /* Varisys Geforce4 Ti 4200 */ 353 0 354 }; 355 356 static struct { 357 uint16 vendor; 358 uint16 *devices; 359 } SupportedDevices[] = { 360 {VENDOR_ID_NVIDIA, nvidia_device_list}, 361 {VENDOR_ID_ELSA, elsa_device_list}, 362 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 363 {VENDOR_ID_VARISYS, varisys_device_list}, 364 {0x0000, NULL} 365 }; 366 367 static nv_settings sSettings = { // see comments in nvidia.settings 368 /* for driver */ 369 DRIVER_PREFIX ".accelerant", 370 "none", // primary 371 false, // dumprom 372 /* for accelerant */ 373 0x00000000, // logmask 374 0, // memory 375 0, // tv_output 376 true, // usebios 377 true, // hardcursor 378 false, // switchhead 379 false, // force_pci 380 false, // unhide_fw 381 false, // pgm_panel 382 true, // dma_acc 383 false, // vga_on_tv 384 false, // force_sync 385 false, // force_ws 386 false, // block_acc 387 0, // gpu_clk 388 0, // ram_clk 389 true, // check_edid 390 }; 391 392 393 static void 394 dumprom(void *rom, uint32 size, pci_info pcii) 395 { 396 int fd; 397 uint32 cnt; 398 char fname[64]; 399 400 /* determine the romfile name: we need split-up per card in the system */ 401 sprintf (fname, kUserDirectory "//" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 402 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 403 404 fd = open (fname, O_WRONLY | O_CREAT, 0666); 405 if (fd < 0) return; 406 407 /* apparantly max. 32kb may be written at once; 408 * the ROM size is a multiple of that anyway. */ 409 for (cnt = 0; (cnt < size); cnt += 32768) 410 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 411 close (fd); 412 } 413 414 415 /*! return 1 if vblank interrupt has occured */ 416 static int 417 caused_vbi_crtc1(vuint32 * regs) 418 { 419 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 420 } 421 422 423 /*! clear the vblank interrupt */ 424 static void 425 clear_vbi_crtc1(vuint32 * regs) 426 { 427 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 428 } 429 430 431 static void 432 enable_vbi_crtc1(vuint32 * regs) 433 { 434 /* clear the vblank interrupt */ 435 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 436 /* enable nVidia interrupt source vblank */ 437 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 438 /* enable nVidia interrupt system hardware (b0-1) */ 439 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 440 } 441 442 443 static void 444 disable_vbi_crtc1(vuint32 * regs) 445 { 446 /* disable nVidia interrupt source vblank */ 447 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 448 /* clear the vblank interrupt */ 449 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 450 } 451 452 453 /*! return 1 if vblank interrupt has occured */ 454 static int 455 caused_vbi_crtc2(vuint32 * regs) 456 { 457 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 458 } 459 460 461 /*! clear the vblank interrupt */ 462 static void 463 clear_vbi_crtc2(vuint32 * regs) 464 { 465 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 466 } 467 468 469 static void 470 enable_vbi_crtc2(vuint32 * regs) 471 { 472 /* clear the vblank interrupt */ 473 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 474 /* enable nVidia interrupt source vblank */ 475 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 476 /* enable nVidia interrupt system hardware (b0-1) */ 477 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 478 } 479 480 481 static void 482 disable_vbi_crtc2(vuint32 * regs) 483 { 484 /* disable nVidia interrupt source vblank */ 485 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 486 /* clear the vblank interrupt */ 487 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 488 } 489 490 491 //fixme: 492 //dangerous code, on singlehead cards better not try accessing secondary head 493 //registers (card might react in unpredictable ways, though there's only a small 494 //chance we actually run into this). 495 //fix requires (some) card recognition code to be moved from accelerant to 496 //kerneldriver... 497 static void 498 disable_vbi_all(vuint32 * regs) 499 { 500 /* disable nVidia interrupt source vblank */ 501 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 502 /* clear the vblank interrupt */ 503 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 504 505 /* disable nVidia interrupt source vblank */ 506 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 507 /* clear the vblank interrupt */ 508 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 509 510 /* disable nVidia interrupt system hardware (b0-1) */ 511 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 512 } 513 514 515 static status_t 516 map_device(device_info *di) 517 { 518 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 519 shared_info *si = di->si; 520 uint32 tmpUlong, tmpROMshadow; 521 pci_info *pcii = &(di->pcii); 522 system_info sysinfo; 523 524 /* variables for making copy of ROM */ 525 uint8* rom_temp; 526 area_id rom_area = -1; 527 528 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 529 int registers = 0; 530 int frame_buffer = 1; 531 532 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 533 tmpUlong = get_pci(PCI_command, 2); 534 /* enable PCI access */ 535 tmpUlong |= PCI_command_memory; 536 /* enable busmastering */ 537 tmpUlong |= PCI_command_master; 538 /* disable ISA I/O access */ 539 tmpUlong &= ~PCI_command_io; 540 set_pci(PCI_command, 2, tmpUlong); 541 542 /*work out which version of BeOS is running*/ 543 get_system_info(&sysinfo); 544 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 545 { 546 si->use_clone_bugfix = 1; 547 } 548 else 549 { 550 si->use_clone_bugfix = 0; 551 } 552 553 /* work out a name for the register mapping */ 554 sprintf(buffer, DEVICE_FORMAT " regs", 555 di->pcii.vendor_id, di->pcii.device_id, 556 di->pcii.bus, di->pcii.device, di->pcii.function); 557 558 /* get a virtual memory address for the registers*/ 559 si->regs_area = map_physical_memory( 560 buffer, 561 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 562 di->pcii.u.h0.base_registers_pci[registers], 563 di->pcii.u.h0.base_register_sizes[registers], 564 B_ANY_KERNEL_ADDRESS, 565 B_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 566 (void **)&(di->regs)); 567 si->clone_bugfix_regs = (uint32 *) di->regs; 568 569 /* if mapping registers to vmem failed then pass on error */ 570 if (si->regs_area < 0) return si->regs_area; 571 572 /* work out a name for the ROM mapping*/ 573 sprintf(buffer, DEVICE_FORMAT " rom", 574 di->pcii.vendor_id, di->pcii.device_id, 575 di->pcii.bus, di->pcii.device, di->pcii.function); 576 577 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 578 /* warning: 579 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 580 * NV18, NV28 and NV34 keep working. 581 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 582 * however the actual ROM content (so the used part) is intact (confirmed). */ 583 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 584 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 585 set_pci(NVCFG_ROMSHADOW, 4, 0); 586 587 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 588 tmpUlong = get_pci(PCI_rom_base, 4); 589 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 590 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 591 //legacy space will get us into trouble if we aren't the primary graphics card!! 592 //(as legacy space always has the primary card's ROM 'mapped'!) 593 if (tmpUlong) { 594 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 595 tmpUlong |= 0x00000001; 596 set_pci(PCI_rom_base, 4, tmpUlong); 597 598 rom_area = map_physical_memory( 599 buffer, 600 di->pcii.u.h0.rom_base_pci, 601 di->pcii.u.h0.rom_size, 602 B_ANY_KERNEL_ADDRESS, 603 B_READ_AREA, 604 (void **)&(rom_temp) 605 ); 606 607 /* check if we got the BIOS and signature (might fail on laptops..) */ 608 if (rom_area >= 0) { 609 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 610 /* apparantly no ROM is mapped here */ 611 delete_area(rom_area); 612 rom_area = -1; 613 /* force using ISA legacy map as fall-back */ 614 tmpUlong = 0x00000000; 615 } 616 } else { 617 /* mapping failed: force using ISA legacy map as fall-back */ 618 tmpUlong = 0x00000000; 619 } 620 } 621 622 if (!tmpUlong) { 623 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 624 rom_area = map_physical_memory(buffer, 0x000c0000, 625 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 626 } 627 628 /* if mapping ROM to vmem failed then clean up and pass on error */ 629 if (rom_area < 0) { 630 delete_area(si->regs_area); 631 si->regs_area = -1; 632 return rom_area; 633 } 634 635 /* dump ROM to file if selected in nvidia.settings 636 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 637 if (sSettings.dumprom) 638 dumprom(rom_temp, 65536, di->pcii); 639 640 /* make a copy of ROM for future reference */ 641 memcpy(si->rom_mirror, rom_temp, 65536); 642 643 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 644 tmpUlong = get_pci(PCI_rom_base, 4); 645 tmpUlong &= 0xfffffffe; 646 set_pci(PCI_rom_base, 4, tmpUlong); 647 delete_area(rom_area); 648 649 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 650 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 651 652 /* work out a name for the framebuffer mapping*/ 653 sprintf(buffer, DEVICE_FORMAT " framebuffer", 654 di->pcii.vendor_id, di->pcii.device_id, 655 di->pcii.bus, di->pcii.device, di->pcii.function); 656 657 /* map the framebuffer into vmem, using Write Combining*/ 658 si->fb_area = map_physical_memory(buffer, 659 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 660 di->pcii.u.h0.base_registers_pci[frame_buffer], 661 di->pcii.u.h0.base_register_sizes[frame_buffer], 662 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 663 B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA, 664 &(si->framebuffer)); 665 666 /*if failed with write combining try again without*/ 667 if (si->fb_area < 0) { 668 si->fb_area = map_physical_memory(buffer, 669 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 670 di->pcii.u.h0.base_registers_pci[frame_buffer], 671 di->pcii.u.h0.base_register_sizes[frame_buffer], 672 B_ANY_KERNEL_BLOCK_ADDRESS, 673 B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA, 674 &(si->framebuffer)); 675 } 676 677 /* if there was an error, delete our other areas and pass on error*/ 678 if (si->fb_area < 0) { 679 delete_area(si->regs_area); 680 si->regs_area = -1; 681 return si->fb_area; 682 } 683 684 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 685 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 686 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 687 688 /* note the amount of memory mapped by the kerneldriver so we can make sure we 689 * don't attempt to adress more later on */ 690 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 691 692 // remember settings for use here and in accelerant 693 si->settings = sSettings; 694 695 /* in any case, return the result */ 696 return si->fb_area; 697 } 698 699 700 static void 701 unmap_device(device_info *di) 702 { 703 shared_info *si = di->si; 704 uint32 tmpUlong; 705 pci_info *pcii = &(di->pcii); 706 707 /* disable memory mapped IO */ 708 tmpUlong = get_pci(PCI_command, 4); 709 tmpUlong &= 0xfffffffc; 710 set_pci(PCI_command, 4, tmpUlong); 711 /* delete the areas */ 712 if (si->regs_area >= 0) 713 delete_area(si->regs_area); 714 if (si->fb_area >= 0) 715 delete_area(si->fb_area); 716 si->regs_area = si->fb_area = -1; 717 si->framebuffer = NULL; 718 di->regs = NULL; 719 } 720 721 722 static void 723 probe_devices(void) 724 { 725 uint32 pci_index = 0; 726 uint32 count = 0; 727 device_info *di = pd->di; 728 char tmp_name[B_OS_NAME_LENGTH]; 729 730 /* while there are more pci devices */ 731 while (count < MAX_DEVICES 732 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 733 int vendor = 0; 734 735 /* if we match a supported vendor */ 736 while (SupportedDevices[vendor].vendor) { 737 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 738 uint16 *devices = SupportedDevices[vendor].devices; 739 /* while there are more supported devices */ 740 while (*devices) { 741 /* if we match a supported device */ 742 if (*devices == di->pcii.device_id ) { 743 /* publish the device name */ 744 sprintf(tmp_name, DEVICE_FORMAT, 745 di->pcii.vendor_id, di->pcii.device_id, 746 di->pcii.bus, di->pcii.device, di->pcii.function); 747 /* tweak the exported name to show first in the alphabetically ordered /dev/ 748 * hierarchy folder, so the system will use it as primary adaptor if requested 749 * via nvidia.settings. */ 750 if (strcmp(tmp_name, sSettings.primary) == 0) 751 sprintf(tmp_name, "-%s", sSettings.primary); 752 /* add /dev/ hierarchy path */ 753 sprintf(di->name, "graphics/%s", tmp_name); 754 /* remember the name */ 755 pd->device_names[count] = di->name; 756 /* mark the driver as available for R/W open */ 757 di->is_open = 0; 758 /* mark areas as not yet created */ 759 di->shared_area = -1; 760 /* mark pointer to shared data as invalid */ 761 di->si = NULL; 762 /* inc pointer to device info */ 763 di++; 764 /* inc count */ 765 count++; 766 /* break out of these while loops */ 767 goto next_device; 768 } 769 /* next supported device */ 770 devices++; 771 } 772 } 773 vendor++; 774 } 775 next_device: 776 /* next pci_info struct, please */ 777 pci_index++; 778 } 779 /* propagate count */ 780 pd->count = count; 781 /* terminate list of device names with a null pointer */ 782 pd->device_names[pd->count] = NULL; 783 } 784 785 786 static uint32 787 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 788 { 789 uint32 handled = B_HANDLED_INTERRUPT; 790 /* release the vblank semaphore */ 791 if (si->vblank >= 0) { 792 int32 blocked; 793 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 794 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 795 handled = B_INVOKE_SCHEDULER; 796 } 797 } 798 return handled; 799 } 800 801 802 static int32 803 nv_interrupt(void *data) 804 { 805 int32 handled = B_UNHANDLED_INTERRUPT; 806 device_info *di = (device_info *)data; 807 shared_info *si = di->si; 808 int32 *flags = &(si->flags); 809 vuint32 *regs; 810 811 /* is someone already handling an interrupt for this device? */ 812 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 813 814 /* get regs */ 815 regs = di->regs; 816 817 /* was it a VBI? */ 818 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 819 if (si->ps.secondary_head) { 820 //fixme: 821 //rewrite once we use one driver instance 'per head' (instead of 'per card') 822 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 823 /* clear the interrupt(s) */ 824 clear_vbi_crtc1(regs); 825 clear_vbi_crtc2(regs); 826 /* release the semaphore */ 827 handled = thread_interrupt_work(flags, regs, si); 828 } 829 } else { 830 if (caused_vbi_crtc1(regs)) { 831 /* clear the interrupt */ 832 clear_vbi_crtc1(regs); 833 /* release the semaphore */ 834 handled = thread_interrupt_work(flags, regs, si); 835 } 836 } 837 838 /* note that we're not in the handler any more */ 839 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 840 841 exit0: 842 return handled; 843 } 844 845 846 // #pragma mark - device hooks 847 848 849 static status_t 850 open_hook(const char* name, uint32 flags, void** cookie) 851 { 852 int32 index = 0; 853 device_info *di; 854 shared_info *si; 855 thread_id thid; 856 thread_info thinfo; 857 status_t result = B_OK; 858 char shared_name[B_OS_NAME_LENGTH]; 859 physical_entry map[1]; 860 size_t net_buf_size; 861 void *unaligned_dma_buffer; 862 uint32 mem_size; 863 864 /* find the device name in the list of devices */ 865 /* we're never passed a name we didn't publish */ 866 while (pd->device_names[index] 867 && (strcmp(name, pd->device_names[index]) != 0)) 868 index++; 869 870 /* for convienience */ 871 di = &(pd->di[index]); 872 873 /* make sure no one else has write access to the common data */ 874 AQUIRE_BEN(pd->kernel); 875 876 /* if it's already open for writing */ 877 if (di->is_open) { 878 /* mark it open another time */ 879 goto mark_as_open; 880 } 881 /* create the shared_info area */ 882 sprintf(shared_name, DEVICE_FORMAT " shared", 883 di->pcii.vendor_id, di->pcii.device_id, 884 di->pcii.bus, di->pcii.device, di->pcii.function); 885 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 886 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 887 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 888 B_CLONEABLE_AREA); 889 if (di->shared_area < 0) { 890 /* return the error */ 891 result = di->shared_area; 892 goto done; 893 } 894 895 /* save a few dereferences */ 896 si = di->si; 897 898 /* create the DMA command buffer area */ 899 //fixme? for R4.5 a workaround for cloning would be needed! 900 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 901 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 902 /* create the area that will hold the DMA command buffer */ 903 si->unaligned_dma_area = 904 create_area("NV DMA cmd buffer", 905 (void **)&unaligned_dma_buffer, 906 B_ANY_KERNEL_ADDRESS, 907 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 908 B_32_BIT_CONTIGUOUS, /* GPU always needs access */ 909 B_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 910 // TODO: Physical aligning can be done without waste using the 911 // private create_area_etc(). 912 /* on error, abort */ 913 if (si->unaligned_dma_area < 0) 914 { 915 /* free the already created shared_info area, and return the error */ 916 result = si->unaligned_dma_area; 917 goto free_shared; 918 } 919 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 920 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 921 * even on older CPU's. */ 922 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 923 si->dma_buffer_pci = (void*) 924 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); 925 926 /* map the net DMA command buffer into vmem, using Write Combining */ 927 si->dma_area = map_physical_memory( 928 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, 929 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 930 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 931 /* if failed with write combining try again without */ 932 if (si->dma_area < 0) { 933 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer", 934 (addr_t)si->dma_buffer_pci, net_buf_size, 935 B_ANY_KERNEL_BLOCK_ADDRESS, 936 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 937 } 938 /* if there was an error, delete our other areas and pass on error*/ 939 if (si->dma_area < 0) 940 { 941 /* free the already created areas, and return the error */ 942 result = si->dma_area; 943 goto free_shared_and_uadma; 944 } 945 946 /* save the vendor and device IDs */ 947 si->vendor_id = di->pcii.vendor_id; 948 si->device_id = di->pcii.device_id; 949 si->revision = di->pcii.revision; 950 si->bus = di->pcii.bus; 951 si->device = di->pcii.device; 952 si->function = di->pcii.function; 953 954 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 955 si->accelerant_in_use = false; 956 /* preset singlehead card to prevent early INT routine calls (once installed) to 957 * wrongly identify the INT request coming from us! */ 958 si->ps.secondary_head = false; 959 960 /* map the device */ 961 result = map_device(di); 962 if (result < 0) goto free_shared_and_alldma; 963 964 /* we will be returning OK status for sure now */ 965 result = B_OK; 966 967 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 968 * unified memory architecture (UMA) */ 969 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 970 { 971 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */ 972 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 973 mem_size = 1024 * 1024 * 974 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 975 /* don't attempt to adress memory not mapped by the kerneldriver */ 976 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 977 /* last 64kB RAM is used for the BIOS (or something else?) */ 978 si->ps.memory_size -= (64 * 1024); 979 break; 980 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */ 981 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 982 mem_size = 1024 * 1024 * 983 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 984 /* don't attempt to adress memory not mapped by the kerneldriver */ 985 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 986 /* last 64kB RAM is used for the BIOS (or something else?) */ 987 si->ps.memory_size -= (64 * 1024); 988 break; 989 default: 990 /* all other cards have own RAM: the amount of which is determined in the 991 * accelerant. */ 992 break; 993 } 994 995 /* disable and clear any pending interrupts */ 996 //fixme: 997 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 998 disable_vbi_all(di->regs); 999 1000 /* preset we can't use INT related functions */ 1001 si->ps.int_assigned = false; 1002 1003 /* create a semaphore for vertical blank management */ 1004 si->vblank = create_sem(0, di->name); 1005 if (si->vblank < 0) goto mark_as_open; 1006 1007 /* change the owner of the semaphores to the opener's team */ 1008 /* this is required because apps can't aquire kernel semaphores */ 1009 thid = find_thread(NULL); 1010 get_thread_info(thid, &thinfo); 1011 set_sem_owner(si->vblank, thinfo.team); 1012 1013 /* If there is a valid interrupt line assigned then set up interrupts */ 1014 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1015 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1016 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1017 { 1018 /* delete the semaphore as it won't be used */ 1019 delete_sem(si->vblank); 1020 si->vblank = -1; 1021 } 1022 else 1023 { 1024 /* otherwise install our interrupt handler */ 1025 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1026 /* bail if we couldn't install the handler */ 1027 if (result != B_OK) 1028 { 1029 /* delete the semaphore as it won't be used */ 1030 delete_sem(si->vblank); 1031 si->vblank = -1; 1032 } 1033 else 1034 { 1035 /* inform accelerant(s) we can use INT related functions */ 1036 si->ps.int_assigned = true; 1037 } 1038 } 1039 1040 mark_as_open: 1041 /* mark the device open */ 1042 di->is_open++; 1043 1044 /* send the cookie to the opener */ 1045 *cookie = di; 1046 1047 goto done; 1048 1049 1050 free_shared_and_alldma: 1051 /* clean up our aligned DMA area */ 1052 delete_area(si->dma_area); 1053 si->dma_area = -1; 1054 si->dma_buffer = NULL; 1055 1056 free_shared_and_uadma: 1057 /* clean up our unaligned DMA area */ 1058 delete_area(si->unaligned_dma_area); 1059 si->unaligned_dma_area = -1; 1060 si->dma_buffer_pci = NULL; 1061 1062 free_shared: 1063 /* clean up our shared area */ 1064 delete_area(di->shared_area); 1065 di->shared_area = -1; 1066 di->si = NULL; 1067 1068 done: 1069 /* end of critical section */ 1070 RELEASE_BEN(pd->kernel); 1071 1072 /* all done, return the status */ 1073 return result; 1074 } 1075 1076 1077 static status_t 1078 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1079 { 1080 *len = 0; 1081 return B_NOT_ALLOWED; 1082 } 1083 1084 1085 static status_t 1086 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1087 { 1088 *len = 0; 1089 return B_NOT_ALLOWED; 1090 } 1091 1092 1093 static status_t 1094 close_hook(void* dev) 1095 { 1096 /* we don't do anything on close: there might be dup'd fd */ 1097 return B_NO_ERROR; 1098 } 1099 1100 1101 static status_t 1102 free_hook(void* dev) 1103 { 1104 device_info *di = (device_info *)dev; 1105 shared_info *si = di->si; 1106 vuint32 *regs = di->regs; 1107 1108 /* lock the driver */ 1109 AQUIRE_BEN(pd->kernel); 1110 1111 /* if opened multiple times, decrement the open count and exit */ 1112 if (di->is_open > 1) 1113 goto unlock_and_exit; 1114 1115 /* disable and clear any pending interrupts */ 1116 //fixme: 1117 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1118 disable_vbi_all(regs); 1119 1120 if (si->ps.int_assigned) { 1121 /* remove interrupt handler */ 1122 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1123 1124 /* delete the semaphores, ignoring any errors ('cause the owning 1125 team may have died on us) */ 1126 delete_sem(si->vblank); 1127 si->vblank = -1; 1128 } 1129 1130 /* free regs and framebuffer areas */ 1131 unmap_device(di); 1132 1133 /* clean up our aligned DMA area */ 1134 delete_area(si->dma_area); 1135 si->dma_area = -1; 1136 si->dma_buffer = NULL; 1137 1138 /* clean up our unaligned DMA area */ 1139 delete_area(si->unaligned_dma_area); 1140 si->unaligned_dma_area = -1; 1141 si->dma_buffer_pci = NULL; 1142 1143 /* clean up our shared area */ 1144 delete_area(di->shared_area); 1145 di->shared_area = -1; 1146 di->si = NULL; 1147 1148 unlock_and_exit: 1149 /* mark the device available */ 1150 di->is_open--; 1151 /* unlock the driver */ 1152 RELEASE_BEN(pd->kernel); 1153 /* all done */ 1154 return B_OK; 1155 } 1156 1157 1158 static status_t 1159 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1160 { 1161 device_info *di = (device_info *)dev; 1162 status_t result = B_DEV_INVALID_IOCTL; 1163 uint32 tmpUlong; 1164 1165 switch (msg) { 1166 /* the only PUBLIC ioctl */ 1167 case B_GET_ACCELERANT_SIGNATURE: 1168 { 1169 strcpy((char* )buf, sSettings.accelerant); 1170 result = B_OK; 1171 break; 1172 } 1173 1174 /* PRIVATE ioctl from here on */ 1175 case NV_GET_PRIVATE_DATA: 1176 { 1177 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1178 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1179 gpd->shared_info_area = di->shared_area; 1180 result = B_OK; 1181 } 1182 break; 1183 } 1184 1185 case NV_GET_PCI: 1186 { 1187 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1188 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1189 pci_info *pcii = &(di->pcii); 1190 gsp->value = get_pci(gsp->offset, gsp->size); 1191 result = B_OK; 1192 } 1193 break; 1194 } 1195 1196 case NV_SET_PCI: 1197 { 1198 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1199 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1200 pci_info *pcii = &(di->pcii); 1201 set_pci(gsp->offset, gsp->size, gsp->value); 1202 result = B_OK; 1203 } 1204 break; 1205 } 1206 1207 case NV_DEVICE_NAME: 1208 { 1209 nv_device_name *dn = (nv_device_name *)buf; 1210 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1211 strcpy(dn->name, di->name); 1212 result = B_OK; 1213 } 1214 break; 1215 } 1216 1217 case NV_RUN_INTERRUPTS: 1218 { 1219 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1220 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1221 vuint32 *regs = di->regs; 1222 if (!(vi->crtc)) { 1223 if (vi->do_it) { 1224 enable_vbi_crtc1(regs); 1225 } else { 1226 disable_vbi_crtc1(regs); 1227 } 1228 } else { 1229 if (vi->do_it) { 1230 enable_vbi_crtc2(regs); 1231 } else { 1232 disable_vbi_crtc2(regs); 1233 } 1234 } 1235 result = B_OK; 1236 } 1237 break; 1238 } 1239 1240 case NV_GET_NTH_AGP_INFO: 1241 { 1242 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1243 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1244 nai->exist = false; 1245 nai->agp_bus = false; 1246 if (agp_bus) { 1247 nai->agp_bus = true; 1248 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1249 nai->exist = true; 1250 } 1251 } 1252 result = B_OK; 1253 } 1254 break; 1255 } 1256 1257 case NV_ENABLE_AGP: 1258 { 1259 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1260 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1261 if (agp_bus) { 1262 nca->agp_bus = true; 1263 nca->cmd = agp_bus->set_agp_mode(nca->cmd); 1264 } else { 1265 nca->agp_bus = false; 1266 nca->cmd = 0; 1267 } 1268 result = B_OK; 1269 } 1270 break; 1271 } 1272 1273 case NV_ISA_OUT: 1274 { 1275 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1276 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1277 pci_info *pcii = &(di->pcii); 1278 1279 /* lock the driver: 1280 * no other graphics card may have ISA I/O enabled when we enter */ 1281 AQUIRE_BEN(pd->kernel); 1282 1283 /* enable ISA I/O access */ 1284 tmpUlong = get_pci(PCI_command, 2); 1285 tmpUlong |= PCI_command_io; 1286 set_pci(PCI_command, 2, tmpUlong); 1287 1288 if (io_isa->size == 1) 1289 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1290 else 1291 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1292 result = B_OK; 1293 1294 /* disable ISA I/O access */ 1295 tmpUlong = get_pci(PCI_command, 2); 1296 tmpUlong &= ~PCI_command_io; 1297 set_pci(PCI_command, 2, tmpUlong); 1298 1299 /* end of critical section */ 1300 RELEASE_BEN(pd->kernel); 1301 } 1302 break; 1303 } 1304 1305 case NV_ISA_IN: 1306 { 1307 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1308 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1309 pci_info *pcii = &(di->pcii); 1310 1311 /* lock the driver: 1312 * no other graphics card may have ISA I/O enabled when we enter */ 1313 AQUIRE_BEN(pd->kernel); 1314 1315 /* enable ISA I/O access */ 1316 tmpUlong = get_pci(PCI_command, 2); 1317 tmpUlong |= PCI_command_io; 1318 set_pci(PCI_command, 2, tmpUlong); 1319 1320 if (io_isa->size == 1) 1321 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1322 else 1323 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1324 result = B_OK; 1325 1326 /* disable ISA I/O access */ 1327 tmpUlong = get_pci(PCI_command, 2); 1328 tmpUlong &= ~PCI_command_io; 1329 set_pci(PCI_command, 2, tmpUlong); 1330 1331 /* end of critical section */ 1332 RELEASE_BEN(pd->kernel); 1333 } 1334 break; 1335 } 1336 } 1337 1338 return result; 1339 } 1340 1341 1342 // #pragma mark - driver API 1343 1344 1345 status_t 1346 init_hardware(void) 1347 { 1348 long index = 0; 1349 pci_info pcii; 1350 bool found = false; 1351 1352 /* choke if we can't find the PCI bus */ 1353 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1354 return B_ERROR; 1355 1356 /* choke if we can't find the ISA bus */ 1357 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1358 { 1359 put_module(B_PCI_MODULE_NAME); 1360 return B_ERROR; 1361 } 1362 1363 /* while there are more pci devices */ 1364 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1365 int vendor = 0; 1366 1367 /* if we match a supported vendor */ 1368 while (SupportedDevices[vendor].vendor) { 1369 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1370 uint16 *devices = SupportedDevices[vendor].devices; 1371 /* while there are more supported devices */ 1372 while (*devices) { 1373 /* if we match a supported device */ 1374 if (*devices == pcii.device_id ) { 1375 1376 found = true; 1377 goto done; 1378 } 1379 /* next supported device */ 1380 devices++; 1381 } 1382 } 1383 vendor++; 1384 } 1385 /* next pci_info struct, please */ 1386 index++; 1387 } 1388 1389 done: 1390 /* put away the module manager */ 1391 put_module(B_PCI_MODULE_NAME); 1392 return found ? B_OK : B_ERROR; 1393 } 1394 1395 1396 status_t 1397 init_driver(void) 1398 { 1399 void *settings; 1400 1401 // get driver/accelerant settings 1402 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1403 if (settings != NULL) { 1404 const char *item; 1405 char *end; 1406 uint32 value; 1407 1408 // for driver 1409 item = get_driver_parameter(settings, "accelerant", "", ""); 1410 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1411 strcpy (sSettings.accelerant, item); 1412 1413 item = get_driver_parameter(settings, "primary", "", ""); 1414 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1415 strcpy(sSettings.primary, item); 1416 1417 sSettings.dumprom = get_driver_boolean_parameter(settings, 1418 "dumprom", false, false); 1419 1420 // for accelerant 1421 item = get_driver_parameter(settings, "logmask", 1422 "0x00000000", "0x00000000"); 1423 value = strtoul(item, &end, 0); 1424 if (*end == '\0') 1425 sSettings.logmask = value; 1426 1427 item = get_driver_parameter(settings, "memory", "0", "0"); 1428 value = strtoul(item, &end, 0); 1429 if (*end == '\0') 1430 sSettings.memory = value; 1431 1432 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1433 value = strtoul(item, &end, 0); 1434 if (*end == '\0') 1435 sSettings.tv_output = value; 1436 1437 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1438 "hardcursor", true, true); 1439 sSettings.usebios = get_driver_boolean_parameter(settings, 1440 "usebios", true, true); 1441 sSettings.switchhead = get_driver_boolean_parameter(settings, 1442 "switchhead", false, false); 1443 sSettings.force_pci = get_driver_boolean_parameter(settings, 1444 "force_pci", false, false); 1445 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1446 "unhide_fw", false, false); 1447 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1448 "pgm_panel", false, false); 1449 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1450 "dma_acc", true, true); 1451 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1452 "vga_on_tv", false, false); 1453 sSettings.force_sync = get_driver_boolean_parameter(settings, 1454 "force_sync", false, false); 1455 sSettings.force_ws = get_driver_boolean_parameter(settings, 1456 "force_ws", false, false); 1457 sSettings.block_acc = get_driver_boolean_parameter(settings, 1458 "block_acc", false, false); 1459 sSettings.check_edid = get_driver_boolean_parameter(settings, 1460 "check_edid", true, true); 1461 1462 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1463 value = strtoul(item, &end, 0); 1464 if (*end == '\0') 1465 sSettings.gpu_clk = value; 1466 1467 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1468 value = strtoul(item, &end, 0); 1469 if (*end == '\0') 1470 sSettings.ram_clk = value; 1471 1472 unload_driver_settings(settings); 1473 } 1474 1475 /* get a handle for the pci bus */ 1476 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1477 return B_ERROR; 1478 1479 /* get a handle for the isa bus */ 1480 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1481 put_module(B_PCI_MODULE_NAME); 1482 return B_ERROR; 1483 } 1484 1485 /* get a handle for the agp bus if it exists */ 1486 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1487 1488 /* driver private data */ 1489 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1490 if (!pd) { 1491 put_module(B_PCI_MODULE_NAME); 1492 return B_ERROR; 1493 } 1494 /* initialize the benaphore */ 1495 INIT_BEN(pd->kernel); 1496 /* find all of our supported devices */ 1497 probe_devices(); 1498 return B_OK; 1499 } 1500 1501 1502 const char ** 1503 publish_devices(void) 1504 { 1505 /* return the list of supported devices */ 1506 return (const char **)pd->device_names; 1507 } 1508 1509 1510 device_hooks * 1511 find_device(const char *name) 1512 { 1513 int index = 0; 1514 while (pd->device_names[index]) { 1515 if (strcmp(name, pd->device_names[index]) == 0) 1516 return &graphics_device_hooks; 1517 index++; 1518 } 1519 return NULL; 1520 1521 } 1522 1523 1524 void 1525 uninit_driver(void) 1526 { 1527 /* free the driver data */ 1528 DELETE_BEN(pd->kernel); 1529 free(pd); 1530 pd = NULL; 1531 1532 /* put the pci module away */ 1533 put_module(B_PCI_MODULE_NAME); 1534 put_module(B_ISA_MODULE_NAME); 1535 1536 /* put the agp module away if it's there */ 1537 if (agp_bus) 1538 put_module(B_AGP_GART_MODULE_NAME); 1539 } 1540 1541