1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-4/2006. 8 */ 9 10 11 #include "AGP.h" 12 #include "DriverInterface.h" 13 #include "nv_macros.h" 14 15 #include <graphic_driver.h> 16 #include <KernelExport.h> 17 #include <ISA.h> 18 #include <PCI.h> 19 #include <OS.h> 20 #include <driver_settings.h> 21 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <string.h> 25 26 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 27 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 28 29 #define MAX_DEVICES 8 30 31 #ifndef __HAIKU__ 32 # undef B_USER_CLONEABLE_AREA 33 # define B_USER_CLONEABLE_AREA 0 34 #endif 35 36 /* Tell the kernel what revision of the driver API we support */ 37 int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39 /* these structures are private to the kernel driver */ 40 typedef struct device_info device_info; 41 42 typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46 } timer_info; 47 48 struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55 }; 56 57 typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62 } DeviceData; 63 64 /* prototypes for our private functions */ 65 static status_t open_hook(const char* name, uint32 flags, void** cookie); 66 static status_t close_hook(void* dev); 67 static status_t free_hook(void* dev); 68 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71 static status_t map_device(device_info *di); 72 static void unmap_device(device_info *di); 73 static void probe_devices(void); 74 static int32 nv_interrupt(void *data); 75 76 static DeviceData *pd; 77 static isa_module_info *isa_bus = NULL; 78 static pci_module_info *pci_bus = NULL; 79 static agp_module_info *agp_bus = NULL; 80 static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91 }; 92 93 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98 static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia GeForce FX 6800 Ultra */ 109 0x0041, /* Nvidia GeForce FX 6800 */ 110 0x0042, /* Nvidia GeForce FX 6800LE */ 111 0x0043, /* Nvidia unknown FX */ 112 0x0045, /* Nvidia GeForce FX 6800 GT */ 113 0x0046, /* Nvidia GeForce FX 6800 GT */ 114 0x0048, /* Nvidia GeForce FX 6800 XT */ 115 0x0049, /* Nvidia unknown FX */ 116 0x004d, /* Nvidia Quadro FX 4400 */ 117 0x004e, /* Nvidia Quadro FX 4000 */ 118 0x0091, /* Nvidia GeForce 7800 GTX PCIe */ 119 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 120 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 121 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 122 0x009d, /* Nvidia Quadro FX 4500 */ 123 0x00a0, /* Nvidia Aladdin TNT2 */ 124 0x00c0, /* Nvidia unknown FX */ 125 0x00c1, /* Nvidia GeForce FX 6800 */ 126 0x00c2, /* Nvidia GeForce FX 6800LE */ 127 0x00c3, /* Nvidia GeForce FX 6800 XT */ 128 0x00c8, /* Nvidia GeForce FX 6800 Go */ 129 0x00c9, /* Nvidia GeForce FX 6800 Ultra Go */ 130 0x00cc, /* Nvidia Quadro FX 1400 Go */ 131 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 132 0x00ce, /* Nvidia Quadro FX 1400 */ 133 0x00f0, /* Nvidia GeForce FX 6800 (Ultra) AGP(?) */ 134 0x00f1, /* Nvidia GeForce FX 6600 GT AGP */ 135 0x00f2, /* Nvidia GeForce FX 6600 AGP */ 136 0x00f3, /* Nvidia GeForce 6200 */ 137 0x00f5, /* Nvidia GeForce FX 7800 GS AGP */ 138 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 139 0x00f9, /* Nvidia GeForce PCX 6800 PCIe */ 140 0x00fa, /* Nvidia GeForce PCX 5750 PCIe */ 141 0x00fb, /* Nvidia GeForce PCX 5900 PCIe */ 142 0x00fc, /* Nvidia GeForce PCX 5300 PCIe */ 143 0x00fd, /* Nvidia Quadro PCX PCIe */ 144 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 145 0x00ff, /* Nvidia GeForce PCX 4300 PCIe */ 146 0x0100, /* Nvidia GeForce256 SDR */ 147 0x0101, /* Nvidia GeForce256 DDR */ 148 0x0102, /* Nvidia GeForce256 Ultra */ 149 0x0103, /* Nvidia Quadro */ 150 0x0110, /* Nvidia GeForce2 MX/MX400 */ 151 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ 152 0x0112, /* Nvidia GeForce2 Go */ 153 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 154 0x0140, /* Nvidia GeForce FX 6600 GT */ 155 0x0141, /* Nvidia GeForce FX 6600 */ 156 0x0142, /* Nvidia GeForce FX 6600LE */ 157 0x0143, /* Nvidia unknown FX */ 158 0x0144, /* Nvidia GeForce FX 6600 Go */ 159 0x0145, /* Nvidia GeForce FX 6610 XL */ 160 0x0146, /* Nvidia GeForce FX 6600 TE Go / 6200 TE Go */ 161 0x0147, /* Nvidia GeForce FX 6700 XL */ 162 0x0148, /* Nvidia GeForce FX 6600 Go */ 163 0x0149, /* Nvidia GeForce FX 6600 GT Go */ 164 0x014b, /* Nvidia unknown FX */ 165 0x014c, /* Nvidia unknown FX */ 166 0x014d, /* Nvidia unknown FX */ 167 0x014e, /* Nvidia Quadro FX 540 */ 168 0x014f, /* Nvidia GeForce 6200 PCIe (128Mb) */ 169 0x0150, /* Nvidia GeForce2 GTS/Pro */ 170 0x0151, /* Nvidia GeForce2 Ti DDR */ 171 0x0152, /* Nvidia GeForce2 Ultra */ 172 0x0153, /* Nvidia Quadro2 Pro */ 173 0x0160, /* Nvidia GeForce 6500 Go */ 174 0x0161, /* Nvidia GeForce 6200 TurboCache */ 175 0x0162, /* Nvidia GeForce 6200SE TurboCache */ 176 0x0163, /* Nvidia GeForce 6200LE */ 177 0x0164, /* Nvidia GeForce FX 6200 Go */ 178 0x0165, /* Nvidia Quadro FX NVS 285 */ 179 0x0166, /* Nvidia GeForce 6400 Go */ 180 0x0167, /* Nvidia GeForce 6200 Go */ 181 0x0168, /* Nvidia GeForce 6400 Go */ 182 0x0169, /* Nvidia GeForce 6250 Go */ 183 0x016a, /* Nvidia Geforce 7100 GS */ 184 0x016b, /* Nvidia unknown FX Go */ 185 0x016c, /* Nvidia unknown FX Go */ 186 0x016d, /* Nvidia unknown FX Go */ 187 0x016e, /* Nvidia unknown FX */ 188 0x0170, /* Nvidia GeForce4 MX 460 */ 189 0x0171, /* Nvidia GeForce4 MX 440 */ 190 0x0172, /* Nvidia GeForce4 MX 420 */ 191 0x0173, /* Nvidia GeForce4 MX 440SE */ 192 0x0174, /* Nvidia GeForce4 440 Go */ 193 0x0175, /* Nvidia GeForce4 420 Go */ 194 0x0176, /* Nvidia GeForce4 420 Go 32M */ 195 0x0177, /* Nvidia GeForce4 460 Go */ 196 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 197 0x0179, /* Nvidia GeForce4 440 Go 64M (PPC: GeForce4 MX) */ 198 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 199 0x017c, /* Nvidia Quadro4 500 GoGL */ 200 0x017d, /* Nvidia GeForce4 410 Go 16M */ 201 0x0181, /* Nvidia GeForce4 MX 440 AGP8X */ 202 0x0182, /* Nvidia GeForce4 MX 440SE AGP8X */ 203 0x0183, /* Nvidia GeForce4 MX 420 AGP8X */ 204 0x0185, /* Nvidia GeForce4 MX 4000 AGP8X */ 205 0x0186, /* Nvidia GeForce4 448 Go */ 206 0x0187, /* Nvidia GeForce4 488 Go */ 207 0x0188, /* Nvidia Quadro4 580 XGL */ 208 0x0189, /* Nvidia GeForce4 MX AGP8X (PPC) */ 209 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 210 0x018b, /* Nvidia Quadro4 380 XGL */ 211 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 212 0x018d, /* Nvidia GeForce4 448 Go */ 213 0x01a0, /* Nvidia GeForce2 Integrated GPU */ 214 0x01d1, /* Nvidia GeForce 7300 LE */ 215 0x01d8, /* Nvidia GeForce 7400 GO */ 216 0x01df, /* Nvidia GeForce 7300 GS */ 217 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ 218 0x0200, /* Nvidia GeForce3 */ 219 0x0201, /* Nvidia GeForce3 Ti 200 */ 220 0x0202, /* Nvidia GeForce3 Ti 500 */ 221 0x0203, /* Nvidia Quadro DCC */ 222 0x0211, /* Nvidia GeForce FX 6800 */ 223 0x0212, /* Nvidia GeForce FX 6800LE */ 224 0x0215, /* Nvidia GeForce FX 6800 GT */ 225 0x0220, /* Nvidia unknown FX */ 226 0x0221, /* Nvidia GeForce 6200 AGP (256Mb - 128bit) */ 227 0x0222, /* Nvidia unknown FX */ 228 0x0228, /* Nvidia unknown FX Go */ 229 0x0240, /* Nvidia GeForce 6150 (NFORCE4 Integr.GPU) */ 230 0x0241, /* Nvidia GeForce 6150 LE (NFORCE4 Integr.GPU) */ 231 0x0242, /* Nvidia GeForce 6100 (NFORCE4 Integr.GPU) */ 232 0x0250, /* Nvidia GeForce4 Ti 4600 */ 233 0x0251, /* Nvidia GeForce4 Ti 4400 */ 234 0x0252, /* Nvidia GeForce4 Ti 4600 */ 235 0x0253, /* Nvidia GeForce4 Ti 4200 */ 236 0x0258, /* Nvidia Quadro4 900 XGL */ 237 0x0259, /* Nvidia Quadro4 750 XGL */ 238 0x025b, /* Nvidia Quadro4 700 XGL */ 239 0x0280, /* Nvidia GeForce4 Ti 4800 AGP8X */ 240 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ 241 0x0282, /* Nvidia GeForce4 Ti 4800SE */ 242 0x0286, /* Nvidia GeForce4 4200 Go */ 243 0x0288, /* Nvidia Quadro4 980 XGL */ 244 0x0289, /* Nvidia Quadro4 780 XGL */ 245 0x028c, /* Nvidia Quadro4 700 GoGL */ 246 0x0290, /* Nvidia GeForce 7900 GTX */ 247 0x0291, /* Nvidia GeForce 7900 GT */ 248 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 249 0x02e1, /* Nvidia GeForce 7600 GS */ 250 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 251 0x0302, /* Nvidia GeForce FX 5800 */ 252 0x0308, /* Nvidia Quadro FX 2000 */ 253 0x0309, /* Nvidia Quadro FX 1000 */ 254 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 255 0x0312, /* Nvidia GeForce FX 5600 */ 256 0x0313, /* Nvidia unknown FX */ 257 0x0314, /* Nvidia GeForce FX 5600XT */ 258 0x0316, /* Nvidia unknown FX Go */ 259 0x0317, /* Nvidia unknown FX Go */ 260 0x031a, /* Nvidia GeForce FX 5600 Go */ 261 0x031b, /* Nvidia GeForce FX 5650 Go */ 262 0x031c, /* Nvidia Quadro FX 700 Go */ 263 0x031d, /* Nvidia unknown FX Go */ 264 0x031e, /* Nvidia unknown FX Go */ 265 0x031f, /* Nvidia unknown FX Go */ 266 0x0320, /* Nvidia GeForce FX 5200 */ 267 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 268 0x0322, /* Nvidia GeForce FX 5200 */ 269 0x0323, /* Nvidia GeForce FX 5200LE */ 270 0x0324, /* Nvidia GeForce FX 5200 Go */ 271 0x0325, /* Nvidia GeForce FX 5250 Go */ 272 0x0326, /* Nvidia GeForce FX 5500 */ 273 0x0327, /* Nvidia GeForce FX 5100 */ 274 0x0328, /* Nvidia GeForce FX 5200 Go 32M/64M */ 275 0x0329, /* Nvidia GeForce FX 5200 (PPC) */ 276 0x032a, /* Nvidia Quadro NVS 280 PCI */ 277 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 278 0x032c, /* Nvidia GeForce FX 5300 Go */ 279 0x032d, /* Nvidia GeForce FX 5100 Go */ 280 0x032e, /* Nvidia unknown FX Go */ 281 0x032f, /* Nvidia unknown FX Go */ 282 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 283 0x0331, /* Nvidia GeForce FX 5900 */ 284 0x0332, /* Nvidia GeForce FX 5900 XT */ 285 0x0333, /* Nvidia GeForce FX 5950 Ultra */ 286 0x0334, /* Nvidia GeForce FX 5900 ZT */ 287 0x0338, /* Nvidia Quadro FX 3000 */ 288 0x033f, /* Nvidia Quadro FX 700 */ 289 0x0341, /* Nvidia GeForce FX 5700 Ultra */ 290 0x0342, /* Nvidia GeForce FX 5700 */ 291 0x0343, /* Nvidia GeForce FX 5700LE */ 292 0x0344, /* Nvidia GeForce FX 5700VE */ 293 0x0345, /* Nvidia unknown FX */ 294 0x0347, /* Nvidia GeForce FX 5700 Go */ 295 0x0348, /* Nvidia GeForce FX 5700 Go */ 296 0x0349, /* Nvidia unknown FX Go */ 297 0x034b, /* Nvidia unknown FX Go */ 298 0x034c, /* Nvidia Quadro FX 1000 Go */ 299 0x034e, /* Nvidia Quadro FX 1100 */ 300 0x034f, /* Nvidia unknown FX */ 301 0x0391, /* Nvidia GeForce 7600 GT */ 302 0x0392, /* Nvidia GeForce 7600 GS */ 303 0x0393, /* Nvidia GeForce 7300 GT */ 304 0x0398, /* Nvidia GeForce 7600 GO */ 305 0 306 }; 307 /* 308 not yet included nVidia ID's that are unknown, but used according to nvidia: 309 0x0090 //g70 310 0x0093 //g70 311 0x0094 //g70 312 0x009c //g70 313 0x009e //g70 314 0x0210 //nv48 315 0x021d //nv48 (existing? not in nvidia list) 316 0x021e //nv48 (existing? not in nvidia list) 317 318 The following ranges seem to exist as well, but no cards are defined yet: 319 0x012x //nv41? 320 0x023x //nv44 type 2? (0x022x is also type 2) 321 */ 322 323 static uint16 elsa_device_list[] = { 324 0x0c60, /* Elsa Gladiac Geforce2 MX */ 325 0 326 }; 327 328 static uint16 nvstbsgs_device_list[] = { 329 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 330 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 331 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 332 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 333 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 334 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 335 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 336 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 337 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 338 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 339 0 340 }; 341 342 static uint16 varisys_device_list[] = { 343 0x3503, /* Varisys GeForce4 MX440 */ 344 0x3505, /* Varisys GeForce4 Ti 4200 */ 345 0 346 }; 347 348 static struct { 349 uint16 vendor; 350 uint16 *devices; 351 } SupportedDevices[] = { 352 {VENDOR_ID_NVIDIA, nvidia_device_list}, 353 {VENDOR_ID_ELSA, elsa_device_list}, 354 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 355 {VENDOR_ID_VARISYS, varisys_device_list}, 356 {0x0000, NULL} 357 }; 358 359 static nv_settings sSettings = { // see comments in nvidia.settings 360 /* for driver */ 361 DRIVER_PREFIX ".accelerant", 362 "none", // primary 363 false, // dumprom 364 /* for accelerant */ 365 0x00000000, // logmask 366 0, // memory 367 0, // tv_output 368 true, // usebios 369 true, // hardcursor 370 false, // switchhead 371 false, // force_pci 372 false, // unhide_fw 373 true, // pgm_panel 374 true, // dma_acc 375 false, // vga_on_tv 376 false, // force_sync 377 false, // force_ws 378 0, // gpu_clk 379 0, // ram_clk 380 }; 381 382 383 static void 384 dumprom(void *rom, uint32 size, pci_info pcii) 385 { 386 int fd; 387 uint32 cnt; 388 char fname[64]; 389 390 /* determine the romfile name: we need split-up per card in the system */ 391 sprintf (fname, "/boot/home/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 392 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 393 394 fd = open (fname, O_WRONLY | O_CREAT, 0666); 395 if (fd < 0) return; 396 397 /* apparantly max. 32kb may be written at once; 398 * the ROM size is a multiple of that anyway. */ 399 for (cnt = 0; (cnt < size); cnt += 32768) 400 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 401 close (fd); 402 } 403 404 405 /*! return 1 if vblank interrupt has occured */ 406 static int 407 caused_vbi_crtc1(vuint32 * regs) 408 { 409 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 410 } 411 412 413 /*! clear the vblank interrupt */ 414 static void 415 clear_vbi_crtc1(vuint32 * regs) 416 { 417 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 418 } 419 420 421 static void 422 enable_vbi_crtc1(vuint32 * regs) 423 { 424 /* clear the vblank interrupt */ 425 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 426 /* enable nVidia interrupt source vblank */ 427 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 428 /* enable nVidia interrupt system hardware (b0-1) */ 429 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 430 } 431 432 433 static void 434 disable_vbi_crtc1(vuint32 * regs) 435 { 436 /* disable nVidia interrupt source vblank */ 437 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 438 /* clear the vblank interrupt */ 439 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 440 } 441 442 443 /*! return 1 if vblank interrupt has occured */ 444 static int 445 caused_vbi_crtc2(vuint32 * regs) 446 { 447 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 448 } 449 450 451 /*! clear the vblank interrupt */ 452 static void 453 clear_vbi_crtc2(vuint32 * regs) 454 { 455 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 456 } 457 458 459 static void 460 enable_vbi_crtc2(vuint32 * regs) 461 { 462 /* clear the vblank interrupt */ 463 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 464 /* enable nVidia interrupt source vblank */ 465 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 466 /* enable nVidia interrupt system hardware (b0-1) */ 467 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 468 } 469 470 471 static void 472 disable_vbi_crtc2(vuint32 * regs) 473 { 474 /* disable nVidia interrupt source vblank */ 475 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 476 /* clear the vblank interrupt */ 477 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 478 } 479 480 481 //fixme: 482 //dangerous code, on singlehead cards better not try accessing secondary head 483 //registers (card might react in unpredictable ways, though there's only a small 484 //chance we actually run into this). 485 //fix requires (some) card recognition code to be moved from accelerant to 486 //kerneldriver... 487 static void 488 disable_vbi_all(vuint32 * regs) 489 { 490 /* disable nVidia interrupt source vblank */ 491 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 492 /* clear the vblank interrupt */ 493 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 494 495 /* disable nVidia interrupt source vblank */ 496 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 497 /* clear the vblank interrupt */ 498 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 499 500 /* disable nVidia interrupt system hardware (b0-1) */ 501 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 502 } 503 504 505 static status_t 506 map_device(device_info *di) 507 { 508 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 509 shared_info *si = di->si; 510 uint32 tmpUlong, tmpROMshadow; 511 pci_info *pcii = &(di->pcii); 512 system_info sysinfo; 513 514 /* variables for making copy of ROM */ 515 uint8* rom_temp; 516 area_id rom_area = -1; 517 518 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 519 int registers = 0; 520 int frame_buffer = 1; 521 522 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 523 tmpUlong = get_pci(PCI_command, 2); 524 /* enable PCI access */ 525 tmpUlong |= PCI_command_memory; 526 /* enable busmastering */ 527 tmpUlong |= PCI_command_master; 528 /* disable ISA I/O access */ 529 tmpUlong &= ~PCI_command_io; 530 set_pci(PCI_command, 2, tmpUlong); 531 532 /*work out which version of BeOS is running*/ 533 get_system_info(&sysinfo); 534 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 535 { 536 si->use_clone_bugfix = 1; 537 } 538 else 539 { 540 si->use_clone_bugfix = 0; 541 } 542 543 /* work out a name for the register mapping */ 544 sprintf(buffer, DEVICE_FORMAT " regs", 545 di->pcii.vendor_id, di->pcii.device_id, 546 di->pcii.bus, di->pcii.device, di->pcii.function); 547 548 /* get a virtual memory address for the registers*/ 549 si->regs_area = map_physical_memory( 550 buffer, 551 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 552 (void *) di->pcii.u.h0.base_registers_pci[registers], 553 di->pcii.u.h0.base_register_sizes[registers], 554 B_ANY_KERNEL_ADDRESS, 555 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), 556 (void **)&(di->regs)); 557 si->clone_bugfix_regs = (uint32 *) di->regs; 558 559 /* if mapping registers to vmem failed then pass on error */ 560 if (si->regs_area < 0) return si->regs_area; 561 562 /* work out a name for the ROM mapping*/ 563 sprintf(buffer, DEVICE_FORMAT " rom", 564 di->pcii.vendor_id, di->pcii.device_id, 565 di->pcii.bus, di->pcii.device, di->pcii.function); 566 567 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 568 /* warning: 569 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 570 * NV18, NV28 and NV34 keep working. 571 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 572 * however the actual ROM content (so the used part) is intact (confirmed). */ 573 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 574 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 575 set_pci(NVCFG_ROMSHADOW, 4, 0); 576 577 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 578 tmpUlong = get_pci(PCI_rom_base, 4); 579 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 580 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 581 //legacy space will get us into trouble if we aren't the primary graphics card!! 582 //(as legacy space always has the primary card's ROM 'mapped'!) 583 if (tmpUlong) { 584 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 585 tmpUlong |= 0x00000001; 586 set_pci(PCI_rom_base, 4, tmpUlong); 587 588 rom_area = map_physical_memory( 589 buffer, 590 (void *)di->pcii.u.h0.rom_base_pci, 591 di->pcii.u.h0.rom_size, 592 B_ANY_KERNEL_ADDRESS, 593 B_READ_AREA, 594 (void **)&(rom_temp) 595 ); 596 597 /* check if we got the BIOS and signature (might fail on laptops..) */ 598 if (rom_area >= 0) { 599 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 600 /* apparantly no ROM is mapped here */ 601 delete_area(rom_area); 602 rom_area = -1; 603 /* force using ISA legacy map as fall-back */ 604 tmpUlong = 0x00000000; 605 } 606 } else { 607 /* mapping failed: force using ISA legacy map as fall-back */ 608 tmpUlong = 0x00000000; 609 } 610 } 611 612 if (!tmpUlong) { 613 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 614 rom_area = map_physical_memory(buffer, (void *)0x000c0000, 615 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); 616 } 617 618 /* if mapping ROM to vmem failed then clean up and pass on error */ 619 if (rom_area < 0) { 620 delete_area(si->regs_area); 621 si->regs_area = -1; 622 return rom_area; 623 } 624 625 /* dump ROM to file if selected in nvidia.settings 626 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 627 if (sSettings.dumprom) 628 dumprom(rom_temp, 65536, di->pcii); 629 630 /* make a copy of ROM for future reference */ 631 memcpy(si->rom_mirror, rom_temp, 65536); 632 633 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 634 tmpUlong = get_pci(PCI_rom_base, 4); 635 tmpUlong &= 0xfffffffe; 636 set_pci(PCI_rom_base, 4, tmpUlong); 637 delete_area(rom_area); 638 639 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 640 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 641 642 /* work out a name for the framebuffer mapping*/ 643 sprintf(buffer, DEVICE_FORMAT " framebuffer", 644 di->pcii.vendor_id, di->pcii.device_id, 645 di->pcii.bus, di->pcii.device, di->pcii.function); 646 647 /* map the framebuffer into vmem, using Write Combining*/ 648 si->fb_area = map_physical_memory(buffer, 649 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 650 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 651 di->pcii.u.h0.base_register_sizes[frame_buffer], 652 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 653 B_READ_AREA | B_WRITE_AREA, 654 &(si->framebuffer)); 655 656 /*if failed with write combining try again without*/ 657 if (si->fb_area < 0) { 658 si->fb_area = map_physical_memory(buffer, 659 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 660 (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], 661 di->pcii.u.h0.base_register_sizes[frame_buffer], 662 B_ANY_KERNEL_BLOCK_ADDRESS, 663 B_READ_AREA | B_WRITE_AREA, 664 &(si->framebuffer)); 665 } 666 667 /* if there was an error, delete our other areas and pass on error*/ 668 if (si->fb_area < 0) { 669 delete_area(si->regs_area); 670 si->regs_area = -1; 671 return si->fb_area; 672 } 673 674 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 675 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 676 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; 677 678 // remember settings for use here and in accelerant 679 si->settings = sSettings; 680 681 /* in any case, return the result */ 682 return si->fb_area; 683 } 684 685 686 static void 687 unmap_device(device_info *di) 688 { 689 shared_info *si = di->si; 690 uint32 tmpUlong; 691 pci_info *pcii = &(di->pcii); 692 693 /* disable memory mapped IO */ 694 tmpUlong = get_pci(PCI_command, 4); 695 tmpUlong &= 0xfffffffc; 696 set_pci(PCI_command, 4, tmpUlong); 697 /* delete the areas */ 698 if (si->regs_area >= 0) 699 delete_area(si->regs_area); 700 if (si->fb_area >= 0) 701 delete_area(si->fb_area); 702 si->regs_area = si->fb_area = -1; 703 si->framebuffer = NULL; 704 di->regs = NULL; 705 } 706 707 708 static void 709 probe_devices(void) 710 { 711 uint32 pci_index = 0; 712 uint32 count = 0; 713 device_info *di = pd->di; 714 char tmp_name[B_OS_NAME_LENGTH]; 715 716 /* while there are more pci devices */ 717 while (count < MAX_DEVICES 718 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 719 int vendor = 0; 720 721 /* if we match a supported vendor */ 722 while (SupportedDevices[vendor].vendor) { 723 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 724 uint16 *devices = SupportedDevices[vendor].devices; 725 /* while there are more supported devices */ 726 while (*devices) { 727 /* if we match a supported device */ 728 if (*devices == di->pcii.device_id ) { 729 /* publish the device name */ 730 sprintf(tmp_name, DEVICE_FORMAT, 731 di->pcii.vendor_id, di->pcii.device_id, 732 di->pcii.bus, di->pcii.device, di->pcii.function); 733 /* tweak the exported name to show first in the alphabetically ordered /dev/ 734 * hierarchy folder, so the system will use it as primary adaptor if requested 735 * via nvidia.settings. */ 736 if (strcmp(tmp_name, sSettings.primary) == 0) 737 sprintf(tmp_name, "-%s", sSettings.primary); 738 /* add /dev/ hierarchy path */ 739 sprintf(di->name, "graphics/%s", tmp_name); 740 /* remember the name */ 741 pd->device_names[count] = di->name; 742 /* mark the driver as available for R/W open */ 743 di->is_open = 0; 744 /* mark areas as not yet created */ 745 di->shared_area = -1; 746 /* mark pointer to shared data as invalid */ 747 di->si = NULL; 748 /* inc pointer to device info */ 749 di++; 750 /* inc count */ 751 count++; 752 /* break out of these while loops */ 753 goto next_device; 754 } 755 /* next supported device */ 756 devices++; 757 } 758 } 759 vendor++; 760 } 761 next_device: 762 /* next pci_info struct, please */ 763 pci_index++; 764 } 765 /* propagate count */ 766 pd->count = count; 767 /* terminate list of device names with a null pointer */ 768 pd->device_names[pd->count] = NULL; 769 } 770 771 772 static uint32 773 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 774 { 775 uint32 handled = B_HANDLED_INTERRUPT; 776 /* release the vblank semaphore */ 777 if (si->vblank >= 0) { 778 int32 blocked; 779 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 780 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 781 handled = B_INVOKE_SCHEDULER; 782 } 783 } 784 return handled; 785 } 786 787 788 static int32 789 nv_interrupt(void *data) 790 { 791 int32 handled = B_UNHANDLED_INTERRUPT; 792 device_info *di = (device_info *)data; 793 shared_info *si = di->si; 794 int32 *flags = &(si->flags); 795 vuint32 *regs; 796 797 /* is someone already handling an interrupt for this device? */ 798 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 799 800 /* get regs */ 801 regs = di->regs; 802 803 /* was it a VBI? */ 804 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 805 if (si->ps.secondary_head) { 806 //fixme: 807 //rewrite once we use one driver instance 'per head' (instead of 'per card') 808 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 809 /* clear the interrupt(s) */ 810 clear_vbi_crtc1(regs); 811 clear_vbi_crtc2(regs); 812 /* release the semaphore */ 813 handled = thread_interrupt_work(flags, regs, si); 814 } 815 } else { 816 if (caused_vbi_crtc1(regs)) { 817 /* clear the interrupt */ 818 clear_vbi_crtc1(regs); 819 /* release the semaphore */ 820 handled = thread_interrupt_work(flags, regs, si); 821 } 822 } 823 824 /* note that we're not in the handler any more */ 825 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 826 827 exit0: 828 return handled; 829 } 830 831 832 // #pragma mark - device hooks 833 834 835 static status_t 836 open_hook(const char* name, uint32 flags, void** cookie) 837 { 838 int32 index = 0; 839 device_info *di; 840 shared_info *si; 841 thread_id thid; 842 thread_info thinfo; 843 status_t result = B_OK; 844 char shared_name[B_OS_NAME_LENGTH]; 845 physical_entry map[1]; 846 size_t net_buf_size; 847 void *unaligned_dma_buffer; 848 849 /* find the device name in the list of devices */ 850 /* we're never passed a name we didn't publish */ 851 while (pd->device_names[index] 852 && (strcmp(name, pd->device_names[index]) != 0)) 853 index++; 854 855 /* for convienience */ 856 di = &(pd->di[index]); 857 858 /* make sure no one else has write access to the common data */ 859 AQUIRE_BEN(pd->kernel); 860 861 /* if it's already open for writing */ 862 if (di->is_open) { 863 /* mark it open another time */ 864 goto mark_as_open; 865 } 866 /* create the shared_info area */ 867 sprintf(shared_name, DEVICE_FORMAT " shared", 868 di->pcii.vendor_id, di->pcii.device_id, 869 di->pcii.bus, di->pcii.device, di->pcii.function); 870 /* create this area with NO user-space read or write permissions, to prevent accidental damage */ 871 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 872 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 873 B_USER_CLONEABLE_AREA); 874 if (di->shared_area < 0) { 875 /* return the error */ 876 result = di->shared_area; 877 goto done; 878 } 879 880 /* save a few dereferences */ 881 si = di->si; 882 883 /* create the DMA command buffer area */ 884 //fixme? for R4.5 a workaround for cloning would be needed! 885 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 886 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 887 /* create the area that will hold the DMA command buffer */ 888 si->unaligned_dma_area = 889 create_area("NV DMA cmd buffer", 890 (void **)&unaligned_dma_buffer, 891 B_ANY_KERNEL_ADDRESS, 892 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 893 B_FULL_LOCK | B_CONTIGUOUS, /* both properties needed: GPU always needs access */ 894 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 895 /* on error, abort */ 896 if (si->unaligned_dma_area < 0) 897 { 898 /* free the already created shared_info area, and return the error */ 899 result = si->unaligned_dma_area; 900 goto free_shared; 901 } 902 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 903 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 904 * even on older CPU's. */ 905 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 906 si->dma_buffer_pci = (void*) 907 ((((uint32)(map[0].address)) + net_buf_size - 1) & ~(net_buf_size - 1)); 908 909 /* map the net DMA command buffer into vmem, using Write Combining */ 910 si->dma_area = map_physical_memory( 911 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 912 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 913 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 914 /* if failed with write combining try again without */ 915 if (si->dma_area < 0) { 916 si->dma_area = map_physical_memory( 917 "NV aligned DMA cmd buffer", si->dma_buffer_pci, net_buf_size, 918 B_ANY_KERNEL_BLOCK_ADDRESS, 919 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 920 } 921 /* if there was an error, delete our other areas and pass on error*/ 922 if (si->dma_area < 0) 923 { 924 /* free the already created areas, and return the error */ 925 result = si->dma_area; 926 goto free_shared_and_uadma; 927 } 928 929 /* save the vendor and device IDs */ 930 si->vendor_id = di->pcii.vendor_id; 931 si->device_id = di->pcii.device_id; 932 si->revision = di->pcii.revision; 933 si->bus = di->pcii.bus; 934 si->device = di->pcii.device; 935 si->function = di->pcii.function; 936 937 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 938 si->accelerant_in_use = false; 939 /* preset singlehead card to prevent early INT routine calls (once installed) to 940 * wrongly identify the INT request coming from us! */ 941 si->ps.secondary_head = false; 942 943 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 944 * unified memory architecture (UMA) */ 945 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 946 { 947 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 948 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 949 si->ps.memory_size = 1024 * 1024 * 950 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 951 /* last 64kB RAM is used for the BIOS (or something else?) */ 952 si->ps.memory_size -= (64 * 1024); 953 break; 954 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 955 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 956 si->ps.memory_size = 1024 * 1024 * 957 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 958 /* last 64kB RAM is used for the BIOS (or something else?) */ 959 si->ps.memory_size -= (64 * 1024); 960 break; 961 default: 962 /* all other cards have own RAM: the amount of which is determined in the 963 * accelerant. */ 964 break; 965 } 966 967 /* map the device */ 968 result = map_device(di); 969 if (result < 0) goto free_shared_and_alldma; 970 971 /* we will be returning OK status for sure now */ 972 result = B_OK; 973 974 /* disable and clear any pending interrupts */ 975 //fixme: 976 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 977 disable_vbi_all(di->regs); 978 979 /* preset we can't use INT related functions */ 980 si->ps.int_assigned = false; 981 982 /* create a semaphore for vertical blank management */ 983 si->vblank = create_sem(0, di->name); 984 if (si->vblank < 0) goto mark_as_open; 985 986 /* change the owner of the semaphores to the opener's team */ 987 /* this is required because apps can't aquire kernel semaphores */ 988 thid = find_thread(NULL); 989 get_thread_info(thid, &thinfo); 990 set_sem_owner(si->vblank, thinfo.team); 991 992 /* If there is a valid interrupt line assigned then set up interrupts */ 993 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 994 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 995 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 996 { 997 /* delete the semaphore as it won't be used */ 998 delete_sem(si->vblank); 999 si->vblank = -1; 1000 } 1001 else 1002 { 1003 /* otherwise install our interrupt handler */ 1004 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1005 /* bail if we couldn't install the handler */ 1006 if (result != B_OK) 1007 { 1008 /* delete the semaphore as it won't be used */ 1009 delete_sem(si->vblank); 1010 si->vblank = -1; 1011 } 1012 else 1013 { 1014 /* inform accelerant(s) we can use INT related functions */ 1015 si->ps.int_assigned = true; 1016 } 1017 } 1018 1019 mark_as_open: 1020 /* mark the device open */ 1021 di->is_open++; 1022 1023 /* send the cookie to the opener */ 1024 *cookie = di; 1025 1026 goto done; 1027 1028 1029 free_shared_and_alldma: 1030 /* clean up our aligned DMA area */ 1031 delete_area(si->dma_area); 1032 si->dma_area = -1; 1033 si->dma_buffer = NULL; 1034 1035 free_shared_and_uadma: 1036 /* clean up our unaligned DMA area */ 1037 delete_area(si->unaligned_dma_area); 1038 si->unaligned_dma_area = -1; 1039 si->dma_buffer_pci = NULL; 1040 1041 free_shared: 1042 /* clean up our shared area */ 1043 delete_area(di->shared_area); 1044 di->shared_area = -1; 1045 di->si = NULL; 1046 1047 done: 1048 /* end of critical section */ 1049 RELEASE_BEN(pd->kernel); 1050 1051 /* all done, return the status */ 1052 return result; 1053 } 1054 1055 1056 static status_t 1057 read_hook(void* dev, off_t pos, void* buf, size_t* len) 1058 { 1059 *len = 0; 1060 return B_NOT_ALLOWED; 1061 } 1062 1063 1064 static status_t 1065 write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1066 { 1067 *len = 0; 1068 return B_NOT_ALLOWED; 1069 } 1070 1071 1072 static status_t 1073 close_hook(void* dev) 1074 { 1075 /* we don't do anything on close: there might be dup'd fd */ 1076 return B_NO_ERROR; 1077 } 1078 1079 1080 static status_t 1081 free_hook(void* dev) 1082 { 1083 device_info *di = (device_info *)dev; 1084 shared_info *si = di->si; 1085 vuint32 *regs = di->regs; 1086 1087 /* lock the driver */ 1088 AQUIRE_BEN(pd->kernel); 1089 1090 /* if opened multiple times, decrement the open count and exit */ 1091 if (di->is_open > 1) 1092 goto unlock_and_exit; 1093 1094 /* disable and clear any pending interrupts */ 1095 //fixme: 1096 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1097 disable_vbi_all(regs); 1098 1099 if (si->ps.int_assigned) { 1100 /* remove interrupt handler */ 1101 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1102 1103 /* delete the semaphores, ignoring any errors ('cause the owning 1104 team may have died on us) */ 1105 delete_sem(si->vblank); 1106 si->vblank = -1; 1107 } 1108 1109 /* free regs and framebuffer areas */ 1110 unmap_device(di); 1111 1112 /* clean up our aligned DMA area */ 1113 delete_area(si->dma_area); 1114 si->dma_area = -1; 1115 si->dma_buffer = NULL; 1116 1117 /* clean up our unaligned DMA area */ 1118 delete_area(si->unaligned_dma_area); 1119 si->unaligned_dma_area = -1; 1120 si->dma_buffer_pci = NULL; 1121 1122 /* clean up our shared area */ 1123 delete_area(di->shared_area); 1124 di->shared_area = -1; 1125 di->si = NULL; 1126 1127 unlock_and_exit: 1128 /* mark the device available */ 1129 di->is_open--; 1130 /* unlock the driver */ 1131 RELEASE_BEN(pd->kernel); 1132 /* all done */ 1133 return B_OK; 1134 } 1135 1136 1137 static status_t 1138 control_hook(void* dev, uint32 msg, void *buf, size_t len) 1139 { 1140 device_info *di = (device_info *)dev; 1141 status_t result = B_DEV_INVALID_IOCTL; 1142 uint32 tmpUlong; 1143 1144 switch (msg) { 1145 /* the only PUBLIC ioctl */ 1146 case B_GET_ACCELERANT_SIGNATURE: 1147 { 1148 strcpy((char* )buf, sSettings.accelerant); 1149 result = B_OK; 1150 break; 1151 } 1152 1153 /* PRIVATE ioctl from here on */ 1154 case NV_GET_PRIVATE_DATA: 1155 { 1156 nv_get_private_data *gpd = (nv_get_private_data *)buf; 1157 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { 1158 gpd->shared_info_area = di->shared_area; 1159 result = B_OK; 1160 } 1161 break; 1162 } 1163 1164 case NV_GET_PCI: 1165 { 1166 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1167 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1168 pci_info *pcii = &(di->pcii); 1169 gsp->value = get_pci(gsp->offset, gsp->size); 1170 result = B_OK; 1171 } 1172 break; 1173 } 1174 1175 case NV_SET_PCI: 1176 { 1177 nv_get_set_pci *gsp = (nv_get_set_pci *)buf; 1178 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { 1179 pci_info *pcii = &(di->pcii); 1180 set_pci(gsp->offset, gsp->size, gsp->value); 1181 result = B_OK; 1182 } 1183 break; 1184 } 1185 1186 case NV_DEVICE_NAME: 1187 { 1188 nv_device_name *dn = (nv_device_name *)buf; 1189 if (dn->magic == NV_PRIVATE_DATA_MAGIC) { 1190 strcpy(dn->name, di->name); 1191 result = B_OK; 1192 } 1193 break; 1194 } 1195 1196 case NV_RUN_INTERRUPTS: 1197 { 1198 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; 1199 if (vi->magic == NV_PRIVATE_DATA_MAGIC) { 1200 vuint32 *regs = di->regs; 1201 if (!(vi->crtc)) { 1202 if (vi->do_it) { 1203 enable_vbi_crtc1(regs); 1204 } else { 1205 disable_vbi_crtc1(regs); 1206 } 1207 } else { 1208 if (vi->do_it) { 1209 enable_vbi_crtc2(regs); 1210 } else { 1211 disable_vbi_crtc2(regs); 1212 } 1213 } 1214 result = B_OK; 1215 } 1216 break; 1217 } 1218 1219 case NV_GET_NTH_AGP_INFO: 1220 { 1221 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf; 1222 if (nai->magic == NV_PRIVATE_DATA_MAGIC) { 1223 nai->exist = false; 1224 nai->agp_bus = false; 1225 if (agp_bus) { 1226 nai->agp_bus = true; 1227 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { 1228 nai->exist = true; 1229 } 1230 } 1231 result = B_OK; 1232 } 1233 break; 1234 } 1235 1236 case NV_ENABLE_AGP: 1237 { 1238 nv_cmd_agp *nca = (nv_cmd_agp *)buf; 1239 if (nca->magic == NV_PRIVATE_DATA_MAGIC) { 1240 if (agp_bus) { 1241 nca->agp_bus = true; 1242 (*agp_bus->enable_agp)(&(nca->cmd)); 1243 } else { 1244 nca->agp_bus = false; 1245 nca->cmd = 0; 1246 } 1247 result = B_OK; 1248 } 1249 break; 1250 } 1251 1252 case NV_ISA_OUT: 1253 { 1254 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1255 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1256 pci_info *pcii = &(di->pcii); 1257 1258 /* lock the driver: 1259 * no other graphics card may have ISA I/O enabled when we enter */ 1260 AQUIRE_BEN(pd->kernel); 1261 1262 /* enable ISA I/O access */ 1263 tmpUlong = get_pci(PCI_command, 2); 1264 tmpUlong |= PCI_command_io; 1265 set_pci(PCI_command, 2, tmpUlong); 1266 1267 if (io_isa->size == 1) 1268 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); 1269 else 1270 isa_bus->write_io_16(io_isa->adress, io_isa->data); 1271 result = B_OK; 1272 1273 /* disable ISA I/O access */ 1274 tmpUlong = get_pci(PCI_command, 2); 1275 tmpUlong &= ~PCI_command_io; 1276 set_pci(PCI_command, 2, tmpUlong); 1277 1278 /* end of critical section */ 1279 RELEASE_BEN(pd->kernel); 1280 } 1281 break; 1282 } 1283 1284 case NV_ISA_IN: 1285 { 1286 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; 1287 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { 1288 pci_info *pcii = &(di->pcii); 1289 1290 /* lock the driver: 1291 * no other graphics card may have ISA I/O enabled when we enter */ 1292 AQUIRE_BEN(pd->kernel); 1293 1294 /* enable ISA I/O access */ 1295 tmpUlong = get_pci(PCI_command, 2); 1296 tmpUlong |= PCI_command_io; 1297 set_pci(PCI_command, 2, tmpUlong); 1298 1299 if (io_isa->size == 1) 1300 io_isa->data = isa_bus->read_io_8(io_isa->adress); 1301 else 1302 io_isa->data = isa_bus->read_io_16(io_isa->adress); 1303 result = B_OK; 1304 1305 /* disable ISA I/O access */ 1306 tmpUlong = get_pci(PCI_command, 2); 1307 tmpUlong &= ~PCI_command_io; 1308 set_pci(PCI_command, 2, tmpUlong); 1309 1310 /* end of critical section */ 1311 RELEASE_BEN(pd->kernel); 1312 } 1313 break; 1314 } 1315 } 1316 1317 return result; 1318 } 1319 1320 1321 // #pragma mark - driver API 1322 1323 1324 status_t 1325 init_hardware(void) 1326 { 1327 long index = 0; 1328 pci_info pcii; 1329 bool found = false; 1330 1331 /* choke if we can't find the PCI bus */ 1332 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1333 return B_ERROR; 1334 1335 /* choke if we can't find the ISA bus */ 1336 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1337 { 1338 put_module(B_PCI_MODULE_NAME); 1339 return B_ERROR; 1340 } 1341 1342 /* while there are more pci devices */ 1343 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1344 int vendor = 0; 1345 1346 /* if we match a supported vendor */ 1347 while (SupportedDevices[vendor].vendor) { 1348 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1349 uint16 *devices = SupportedDevices[vendor].devices; 1350 /* while there are more supported devices */ 1351 while (*devices) { 1352 /* if we match a supported device */ 1353 if (*devices == pcii.device_id ) { 1354 1355 found = true; 1356 goto done; 1357 } 1358 /* next supported device */ 1359 devices++; 1360 } 1361 } 1362 vendor++; 1363 } 1364 /* next pci_info struct, please */ 1365 index++; 1366 } 1367 1368 done: 1369 /* put away the module manager */ 1370 put_module(B_PCI_MODULE_NAME); 1371 return found ? B_OK : B_ERROR; 1372 } 1373 1374 1375 status_t 1376 init_driver(void) 1377 { 1378 void *settings; 1379 1380 // get driver/accelerant settings 1381 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1382 if (settings != NULL) { 1383 const char *item; 1384 char *end; 1385 uint32 value; 1386 1387 // for driver 1388 item = get_driver_parameter(settings, "accelerant", "", ""); 1389 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1390 strcpy (sSettings.accelerant, item); 1391 1392 item = get_driver_parameter(settings, "primary", "", ""); 1393 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1394 strcpy(sSettings.primary, item); 1395 1396 sSettings.dumprom = get_driver_boolean_parameter(settings, 1397 "dumprom", false, false); 1398 1399 // for accelerant 1400 item = get_driver_parameter(settings, "logmask", 1401 "0x00000000", "0x00000000"); 1402 value = strtoul(item, &end, 0); 1403 if (*end == '\0') 1404 sSettings.logmask = value; 1405 1406 item = get_driver_parameter(settings, "memory", "0", "0"); 1407 value = strtoul(item, &end, 0); 1408 if (*end == '\0') 1409 sSettings.memory = value; 1410 1411 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1412 value = strtoul(item, &end, 0); 1413 if (*end == '\0') 1414 sSettings.tv_output = value; 1415 1416 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1417 "hardcursor", false, false); 1418 sSettings.usebios = get_driver_boolean_parameter(settings, 1419 "usebios", false, false); 1420 sSettings.switchhead = get_driver_boolean_parameter(settings, 1421 "switchhead", false, false); 1422 sSettings.force_pci = get_driver_boolean_parameter(settings, 1423 "force_pci", false, false); 1424 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1425 "unhide_fw", false, false); 1426 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1427 "pgm_panel", false, false); 1428 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1429 "dma_acc", false, false); 1430 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1431 "vga_on_tv", false, false); 1432 sSettings.force_sync = get_driver_boolean_parameter(settings, 1433 "force_sync", false, false); 1434 sSettings.force_ws = get_driver_boolean_parameter(settings, 1435 "force_ws", false, false); 1436 1437 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1438 value = strtoul(item, &end, 0); 1439 if (*end == '\0') 1440 sSettings.gpu_clk = value; 1441 1442 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1443 value = strtoul(item, &end, 0); 1444 if (*end == '\0') 1445 sSettings.ram_clk = value; 1446 1447 unload_driver_settings(settings); 1448 } 1449 1450 /* get a handle for the pci bus */ 1451 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1452 return B_ERROR; 1453 1454 /* get a handle for the isa bus */ 1455 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1456 put_module(B_PCI_MODULE_NAME); 1457 return B_ERROR; 1458 } 1459 1460 /* get a handle for the agp bus if it exists */ 1461 get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus); 1462 1463 /* driver private data */ 1464 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1465 if (!pd) { 1466 put_module(B_PCI_MODULE_NAME); 1467 return B_ERROR; 1468 } 1469 /* initialize the benaphore */ 1470 INIT_BEN(pd->kernel); 1471 /* find all of our supported devices */ 1472 probe_devices(); 1473 return B_OK; 1474 } 1475 1476 1477 const char ** 1478 publish_devices(void) 1479 { 1480 /* return the list of supported devices */ 1481 return (const char **)pd->device_names; 1482 } 1483 1484 1485 device_hooks * 1486 find_device(const char *name) 1487 { 1488 int index = 0; 1489 while (pd->device_names[index]) { 1490 if (strcmp(name, pd->device_names[index]) == 0) 1491 return &graphics_device_hooks; 1492 index++; 1493 } 1494 return NULL; 1495 1496 } 1497 1498 1499 void 1500 uninit_driver(void) 1501 { 1502 /* free the driver data */ 1503 DELETE_BEN(pd->kernel); 1504 free(pd); 1505 pd = NULL; 1506 1507 /* put the pci module away */ 1508 put_module(B_PCI_MODULE_NAME); 1509 put_module(B_ISA_MODULE_NAME); 1510 1511 /* put the agp module away if it's there */ 1512 if (agp_bus) 1513 put_module(B_AGP_MODULE_NAME); 1514 } 1515 1516